Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27143

1

T1

1

T2

26

T3

12

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23826

1

T1

1

T2

26

T3

12

auto[ADC_CTRL_FILTER_COND_OUT]

3317

1

T5

2

T6

13

T9

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21367

1

T3

12

T5

115

T7

2

auto[1]

5776

1

T1

1

T2

26

T4

8

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23175

1

T1

1

T2

13

T3

12

auto[1]

3968

1

T2

13

T4

7

T5

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	287	1			T35	23		T37	23		T120	1
values[0]	20	1			T58	3		T132	1		T217	11
values[1]	684	1			T5	2		T7	11		T43	19
values[2]	917	1			T119	6		T141	1		T27	21
values[3]	746	1			T118	1		T46	3		T27	16
values[4]	601	1			T46	23		T38	5		T22	13
values[5]	646	1			T6	13		T35	26		T43	8
values[6]	789	1			T2	26		T37	29		T141	1
values[7]	641	1			T5	1		T119	25		T38	9
values[8]	552	1			T37	6		T23	9		T162	13
values[9]	3210	1			T1	1		T4	8		T8	17
minimum	18050	1			T3	12		T5	112		T7	2

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	698	1			T5	2		T7	11		T43	19
values[1]	994	1			T141	1		T27	21		T128	18
values[2]	628	1			T118	1		T46	3		T27	16
values[3]	596	1			T46	23		T38	5		T22	13
values[4]	754	1			T6	13		T35	26		T43	8
values[5]	625	1			T2	26		T5	1		T37	29
values[6]	3128	1			T1	1		T4	8		T8	17
values[7]	499	1			T9	2		T23	9		T162	13
values[8]	839	1			T35	23		T37	23		T24	7
values[9]	154	1			T46	34		T57	14		T210	28
minimum	18228	1			T3	12		T5	112		T7	2

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22925

1

T1

1

T2

14

T3

12

auto[1]

4218

1

T2

12

T6

7

T8

15

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T7	1		T43	4		T119	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T5	1		T192	12		T89	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T141	1		T27	10		T129	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	316	1			T128	1		T13	16		T40	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T27	14		T30	12		T57	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T118	1		T46	3		T149	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T46	13		T38	2		T22	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T149	1		T172	1		T31	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T43	8		T23	7		T161	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T6	8		T35	13		T119	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T2	13		T5	1		T37	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T119	13		T23	7		T120	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1657	1			T1	1		T4	1		T8	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T37	1		T38	5		T22	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T23	5		T162	7		T58	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T9	2		T89	1		T123	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T35	11		T24	7		T120	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T37	15		T207	1		T191	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T46	17		T155	1		T328	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T57	7		T210	15		T226	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17952	1			T3	12		T5	112		T9	140
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T58	3		T88	8		T132	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T7	10		T43	15		T206	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T5	1		T192	9		T89	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T27	11		T129	11		T143	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T128	17		T13	12		T123	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T27	2		T30	13		T57	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T88	1		T211	2		T242	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T46	10		T38	3		T206	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T31	8		T212	11		T222	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T23	13		T31	8		T214	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T6	5		T35	13		T119	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T2	13		T37	17		T57	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T119	12		T23	4		T215	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1014	1			T4	7		T127	25		T29	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T37	5		T38	4		T27	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T23	4		T162	6		T58	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T89	8		T123	1		T329	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T35	12		T206	5		T162	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T37	8		T191	1		T152	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T46	17		T216	10		T330	20
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T57	7		T210	13		T226	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T7	2		T9	3		T38	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T331	18		T219	1		T272	12

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T35	11		T120	1		T162	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T37	15		T207	1		T209	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T217	11		T179	3		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T58	3		T132	1		T332	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T7	1		T43	4		T12	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T5	1		T192	12		T88	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T119	6		T141	1		T27	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T128	1		T40	5		T48	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T27	14		T30	12		T57	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T118	1		T46	3		T13	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T46	13		T38	2		T22	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T88	1		T172	1		T31	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T43	8		T206	1		T121	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T6	8		T35	13		T119	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T2	13		T37	12		T141	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T23	7		T120	1		T215	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T5	1		T176	1		T139	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T119	13		T38	5		T22	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T23	5		T162	7		T58	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T37	1		T123	1		T15	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1773	1			T1	1		T4	1		T8	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T9	2		T57	7		T89	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17910	1			T3	12		T5	112		T9	140
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T35	12		T162	16		T236	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T37	8		T209	9		T210	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T7	10		T43	15		T12	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T5	1		T192	9		T291	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T27	11		T206	12		T129	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T128	17		T89	13		T123	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T27	2		T30	13		T57	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T13	12		T211	2		T242	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T46	10		T38	3		T122	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T88	1		T31	8		T212	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T206	9		T31	8		T214	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T6	5		T35	13		T119	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T2	13		T37	17		T23	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T23	4		T215	13		T62	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T176	9		T139	6		T241	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T119	12		T38	4		T27	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T23	4		T162	6		T58	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T37	5		T123	1		T16	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1040	1			T4	7		T127	25		T46	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T57	7		T89	8		T191	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T7	2		T9	3		T38	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T7	11		T43	16		T119	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T5	2		T192	10		T89	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T141	1		T27	12		T129	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T128	18		T13	16		T40	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T27	3		T30	14		T57	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T118	1		T46	1		T149	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T46	11		T38	5		T22	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T149	1		T172	1		T31	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T43	1		T23	14		T161	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T6	6		T35	14		T119	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T2	14		T5	1		T37	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T119	13		T23	5		T120	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1351	1			T1	1		T4	8		T8	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T37	6		T38	5		T22	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T23	5		T162	7		T58	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T9	2		T89	9		T123	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T35	13		T24	1		T120	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T37	9		T207	1		T191	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T46	18		T155	1		T328	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T57	8		T210	14		T226	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18097	1			T3	12		T5	112		T7	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T58	1		T88	1		T132	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T43	3		T119	5		T95	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T192	11		T134	12		T266	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T27	9		T129	9		T143	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T13	12		T40	1		T123	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T27	13		T30	11		T57	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T46	2		T211	3		T242	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T46	12		T22	12		T142	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T31	10		T222	5		T21	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T43	7		T23	6		T161	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T6	7		T35	12		T119	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T2	12		T37	11		T57	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T119	12		T23	6		T17	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1320	1			T8	15		T42	33		T44	39
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T38	4		T22	16		T27	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T23	4		T162	6		T58	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T223	13		T317	14		T256	20
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T35	10		T24	6		T58	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T37	14		T191	1		T225	23
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T46	16		T330	15		T333	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T57	6		T210	14		T226	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T205	12		T213	12		T181	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T58	2		T88	7		T277	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T35	13		T120	1		T162	17
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T37	9		T207	1		T209	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T217	1		T179	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T58	1		T132	1		T332	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T7	11		T43	16		T12	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T5	2		T192	10		T88	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T119	1		T141	1		T27	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T128	18		T40	4		T48	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T27	3		T30	14		T57	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T118	1		T46	1		T13	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T46	11		T38	5		T22	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T88	2		T172	1		T31	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T43	1		T206	10		T121	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T6	6		T35	14		T119	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T2	14		T37	18		T141	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T23	5		T120	1		T215	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T5	1		T176	10		T139	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T119	13		T38	5		T22	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T23	5		T162	7		T58	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T37	6		T123	2		T15	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1401	1			T1	1		T4	8		T8	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T9	2		T57	8		T89	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18050	1			T3	12		T5	112		T7	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T35	10		T236	15		T285	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T37	14		T210	14		T226	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T217	10		T179	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T58	2		T332	1		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T43	3		T95	1		T41	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T192	11		T88	7		T277	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T119	5		T27	9		T129	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T40	1		T123	11		T143	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T27	13		T30	11		T57	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T46	2		T13	12		T211	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T46	12		T22	12		T142	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T31	10		T222	5		T21	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T43	7		T161	12		T31	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T6	7		T35	12		T119	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T2	12		T37	11		T23	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T23	6		T228	17		T62	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T163	23		T136	4		T334	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T119	12		T38	4		T22	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T23	4		T162	6		T58	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T16	3		T236	9		T134	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1412	1			T8	15		T42	33		T44	39
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T57	6		T191	1		T225	23

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22925

1

T1

1

T2

14

T3

12

auto[1]

auto[0]

4218

1

T2

12

T6

7

T8

15