Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27143

1

T1

1

T2

26

T3

12

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23946

1

T1

1

T3

12

T4

8

auto[ADC_CTRL_FILTER_COND_OUT]

3197

1

T2

26

T5

3

T7

11

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21016

1

T2

26

T3

12

T5

115

auto[1]

6127

1

T1

1

T4

8

T7

11

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23175

1

T1

1

T2

13

T3

12

auto[1]

3968

1

T2

13

T4

7

T5

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	137	1			T5	1		T149	1		T227	20
values[0]	23	1			T57	4		T308	1		T231	17
values[1]	628	1			T6	13		T37	29		T118	1
values[2]	579	1			T46	3		T119	31		T27	21
values[3]	845	1			T5	2		T9	1		T43	19
values[4]	3057	1			T1	1		T4	8		T8	17
values[5]	684	1			T38	5		T128	18		T139	3
values[6]	592	1			T46	34		T22	30		T23	11
values[7]	776	1			T2	26		T7	11		T119	25
values[8]	691	1			T43	8		T30	25		T176	10
values[9]	1081	1			T35	49		T37	29		T46	23
minimum	18050	1			T3	12		T5	112		T7	2

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	621	1			T6	13		T37	23		T118	1
values[1]	708	1			T5	2		T9	1		T119	6
values[2]	750	1			T43	19		T141	1		T23	9
values[3]	3050	1			T1	1		T4	8		T8	17
values[4]	706	1			T38	5		T23	11		T128	18
values[5]	602	1			T46	34		T22	30		T24	7
values[6]	819	1			T2	26		T7	11		T119	25
values[7]	602	1			T43	8		T23	20		T30	25
values[8]	937	1			T5	1		T35	23		T37	29
values[9]	153	1			T35	26		T57	15		T149	1
minimum	18195	1			T3	12		T5	112		T7	2

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22925

1

T1

1

T2

14

T3

12

auto[1]

4218

1

T2

12

T6

7

T8

15

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T6	8		T37	15		T206	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T118	1		T46	3		T119	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T94	1		T233	11		T246	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T5	1		T9	1		T119	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T43	4		T23	5		T58	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T141	1		T27	12		T192	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1785	1			T1	1		T4	1		T8	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T9	1		T215	1		T149	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T38	2		T23	7		T88	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T128	1		T139	1		T95	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T46	17		T22	30		T27	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T24	7		T120	1		T58	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T13	16		T120	1		T162	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T2	13		T7	1		T119	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T23	7		T176	1		T148	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T43	8		T30	12		T57	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T37	12		T38	5		T12	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T5	1		T35	11		T46	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T35	13		T57	13		T149	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T130	1		T230	6		T234	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17957	1			T3	12		T5	112		T9	140
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T57	2		T135	1		T222	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T6	5		T37	8		T206	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T119	12		T27	11		T241	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T236	11		T133	10		T213	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T5	1		T139	6		T31	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T43	15		T23	4		T143	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T27	14		T192	9		T162	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1026	1			T4	7		T127	25		T29	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T215	13		T123	1		T214	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T38	3		T23	4		T88	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T128	17		T139	2		T123	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T46	17		T27	2		T206	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T58	5		T133	11		T234	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T13	12		T162	6		T224	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T2	13		T7	10		T119	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T23	13		T176	9		T41	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T30	13		T57	7		T89	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T37	17		T38	4		T12	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T35	12		T46	10		T227	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T35	13		T57	2		T239	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T234	10		T335	13		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T7	2		T9	3		T37	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T57	2		T222	2		T291	10

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T149	1		T217	11		T189	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T5	1		T227	9		T228	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T308	1		T168	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T57	2		T231	9		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T6	8		T37	16		T206	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T118	1		T141	1		T241	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T94	1		T229	1		T233	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T46	3		T119	19		T27	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T43	4		T23	5		T58	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T5	1		T9	1		T141	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1770	1			T1	1		T4	1		T8	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T9	1		T215	1		T149	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T38	2		T48	1		T184	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T128	1		T139	1		T95	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T46	17		T22	30		T23	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T24	7		T120	1		T123	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T120	1		T162	7		T94	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T2	13		T7	1		T119	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T176	1		T13	16		T148	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T43	8		T30	12		T121	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T35	13		T37	12		T38	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T35	11		T46	13		T89	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17910	1			T3	12		T5	112		T9	140
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T189	5		T239	6		T307	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T227	11		T336	6		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T57	2		T231	8		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T6	5		T37	13		T206	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T241	2		T152	2		T242	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T236	11		T213	3		T243	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T119	12		T27	11		T139	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T43	15		T23	4		T221	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T5	1		T27	14		T192	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1024	1			T4	7		T127	25		T29	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T215	13		T123	1		T214	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T38	3		T88	1		T18	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T128	17		T139	2		T238	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T46	17		T23	4		T27	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T123	1		T234	5		T247	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T162	6		T143	7		T224	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T2	13		T7	10		T119	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T176	9		T13	12		T41	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T30	13		T89	8		T16	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T35	13		T37	17		T38	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T35	12		T46	10		T89	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T7	2		T9	3		T38	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T6	6		T37	9		T206	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T118	1		T46	1		T119	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T94	1		T233	1		T246	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T5	2		T9	1		T119	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T43	16		T23	5		T58	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T141	1		T27	15		T192	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1383	1			T1	1		T4	8		T8	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T9	1		T215	14		T149	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T38	5		T23	5		T88	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T128	18		T139	3		T95	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T46	18		T22	2		T27	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T24	1		T120	1		T58	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T13	16		T120	1		T162	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T2	14		T7	11		T119	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T23	14		T176	10		T148	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T43	1		T30	14		T57	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T37	18		T38	5		T12	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T5	1		T35	13		T46	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T35	14		T57	3		T149	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T130	1		T230	1		T234	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18085	1			T3	12		T5	112		T7	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T57	3		T135	1		T222	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T6	7		T37	14		T142	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T46	2		T119	12		T27	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T233	10		T246	2		T236	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T119	5		T161	12		T31	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T43	3		T23	4		T58	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T27	11		T192	11		T40	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1428	1			T8	15		T42	33		T44	39
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T214	13		T211	3		T163	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T23	6		T88	7		T129	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T95	9		T225	5		T281	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T46	16		T22	28		T27	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T24	6		T58	4		T250	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T13	12		T162	6		T224	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T2	12		T119	12		T58	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T23	6		T41	1		T17	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T43	7		T30	11		T57	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T37	11		T38	4		T14	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T35	10		T46	12		T227	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T35	12		T57	12		T248	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T230	5		T234	8		T337	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T209	1		T305	13		T153	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T57	1		T222	5		T231	8

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T149	1		T217	1		T189	9
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T5	1		T227	12		T228	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T308	1		T168	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T57	3		T231	9		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T6	6		T37	15		T206	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T118	1		T141	1		T241	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T94	1		T229	1		T233	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T46	1		T119	14		T27	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T43	16		T23	5		T58	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T5	2		T9	1		T141	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1370	1			T1	1		T4	8		T8	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T9	1		T215	14		T149	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T38	5		T48	1		T184	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T128	18		T139	3		T95	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T46	18		T22	2		T23	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T24	1		T120	1		T123	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T120	1		T162	7		T94	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T2	14		T7	11		T119	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T176	10		T13	16		T148	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T43	1		T30	14		T121	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	292	1			T35	14		T37	18		T38	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	322	1			T35	13		T46	11		T89	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18050	1			T3	12		T5	112		T7	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T217	10		T189	1		T265	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T227	8		T228	7		T182	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T57	1		T231	8		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T6	7		T37	14		T142	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T152	3		T249	3		T242	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T233	10		T246	2		T236	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T46	2		T119	17		T27	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T43	3		T23	4		T58	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T27	11		T192	11		T228	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1424	1			T8	15		T42	33		T44	39
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T40	1		T214	13		T237	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T88	7		T18	1		T262	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T95	9		T225	5		T236	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T46	16		T22	28		T23	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T24	6		T250	8		T234	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T162	6		T143	3		T224	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T2	12		T119	12		T57	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T13	12		T41	1		T130	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T43	7		T30	11		T95	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T35	12		T37	11		T38	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T35	10		T46	12		T230	5

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22925

1

T1

1

T2

14

T3

12

auto[1]

auto[0]

4218

1

T2

12

T6

7

T8

15