Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27143

1

T1

1

T2

26

T3

12

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23624

1

T1

1

T3

12

T4

8

auto[ADC_CTRL_FILTER_COND_OUT]

3519

1

T2

26

T5

1

T6

13

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20721

1

T3

12

T5

115

T6

13

auto[1]

6422

1

T1

1

T2

26

T4

8

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23175

1

T1

1

T2

13

T3

12

auto[1]

3968

1

T2

13

T4

7

T5

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	394	1			T46	23		T57	14		T17	6
values[0]	88	1			T7	11		T16	9		T134	14
values[1]	581	1			T43	19		T27	21		T176	10
values[2]	644	1			T2	26		T43	8		T118	1
values[3]	793	1			T5	2		T6	13		T35	26
values[4]	576	1			T141	1		T23	9		T24	7
values[5]	3138	1			T1	1		T4	8		T8	17
values[6]	574	1			T5	1		T119	25		T38	5
values[7]	629	1			T9	1		T57	15		T120	1
values[8]	821	1			T119	25		T215	14		T206	13
values[9]	855	1			T12	5		T30	25		T128	18
minimum	18050	1			T3	12		T5	112		T7	2

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	518	1			T43	27		T176	10		T149	1
values[1]	750	1			T2	26		T5	2		T37	6
values[2]	750	1			T6	13		T35	26		T37	52
values[3]	2970	1			T1	1		T4	8		T8	17
values[4]	637	1			T9	1		T35	23		T46	3
values[5]	646	1			T5	1		T119	25		T38	5
values[6]	665	1			T9	1		T57	15		T206	6
values[7]	839	1			T119	25		T215	14		T206	13
values[8]	907	1			T46	23		T12	5		T30	25
values[9]	131	1			T17	6		T241	7		T338	1
minimum	18330	1			T3	12		T5	112		T7	13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22925

1

T1

1

T2

14

T3

12

auto[1]

4218

1

T2

12

T6

7

T8

15

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T43	8		T176	1		T149	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T43	4		T122	1		T143	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T5	1		T37	1		T118	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T2	13		T141	1		T13	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T37	15		T46	17		T141	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T6	8		T35	13		T37	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1642	1			T1	1		T4	1		T8	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T23	5		T24	7		T120	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T46	3		T119	6		T23	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T9	1		T35	11		T162	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T38	2		T88	1		T172	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T5	1		T119	13		T22	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T9	1		T40	5		T148	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T57	13		T206	1		T184	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T215	1		T121	1		T58	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T119	13		T206	1		T58	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T12	3		T30	12		T207	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T46	13		T128	1		T57	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T17	4		T338	1		T204	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T241	1		T244	12		T339	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17962	1			T3	12		T5	112		T7	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T237	12		T134	14		T243	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T176	9		T89	8		T211	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T43	15		T122	9		T143	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T5	1		T37	5		T23	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T2	13		T13	12		T192	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T37	8		T46	17		T162	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T6	5		T35	13		T37	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	968	1			T4	7		T127	25		T29	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T23	4		T214	10		T191	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T23	13		T27	16		T57	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T35	12		T162	16		T227	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T38	3		T88	1		T31	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T119	12		T14	3		T209	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T31	8		T129	11		T151	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T57	2		T206	5		T123	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T215	13		T58	5		T143	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T119	12		T206	12		T58	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T12	2		T30	13		T143	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T46	10		T128	17		T57	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T17	2		T204	1		T340	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T241	6		T244	2		T339	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T7	12		T9	3		T38	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T237	13		T243	8		T301	11

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T17	4		T129	5		T234	9
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T46	13		T57	7		T185	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T7	1		T16	5		T231	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T134	14		T326	11		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T27	10		T176	1		T149	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T43	4		T122	1		T143	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T43	8		T118	1		T94	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T2	13		T141	1		T13	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T5	1		T37	16		T46	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T6	8		T35	13		T37	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T141	1		T57	2		T206	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T23	5		T24	7		T120	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1716	1			T1	1		T4	1		T8	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T9	1		T35	11		T162	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T38	2		T88	1		T172	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T5	1		T119	13		T22	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T9	1		T40	5		T148	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T57	13		T120	1		T206	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T215	1		T121	1		T58	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T119	13		T206	1		T58	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T12	3		T30	12		T207	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T128	1		T58	3		T184	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17910	1			T3	12		T5	112		T9	140
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T17	2		T234	10		T341	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T46	10		T57	7		T285	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T7	10		T16	4		T231	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T326	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T27	11		T176	9		T89	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T43	15		T122	9		T143	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T151	2		T152	2		T245	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T2	13		T13	12		T142	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T5	1		T37	13		T46	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T6	5		T35	13		T37	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T57	2		T206	9		T41	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T23	4		T89	13		T214	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1035	1			T4	7		T127	25		T23	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T35	12		T162	16		T227	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T38	3		T88	1		T31	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T119	12		T14	3		T210	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T31	8		T129	11		T224	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T57	2		T206	5		T209	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T215	13		T58	5		T143	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T119	12		T206	12		T58	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T12	2		T30	13		T143	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T128	17		T123	11		T214	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T7	2		T9	3		T38	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T43	1		T176	10		T149	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T43	16		T122	10		T143	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T5	2		T37	6		T118	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T2	14		T141	1		T13	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T37	9		T46	18		T141	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T6	6		T35	14		T37	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1307	1			T1	1		T4	8		T8	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T23	5		T24	1		T120	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T46	1		T119	1		T23	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T9	1		T35	13		T162	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T38	5		T88	2		T172	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T5	1		T119	13		T22	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T9	1		T40	4		T148	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T57	3		T206	6		T184	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T215	14		T121	1		T58	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T119	13		T206	13		T58	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T12	5		T30	14		T207	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T46	11		T128	18		T57	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T17	4		T338	1		T204	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T241	7		T244	3		T339	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18109	1			T3	12		T5	112		T7	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T237	14		T134	1		T243	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T43	7		T211	3		T225	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T43	3		T143	3		T277	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T23	6		T95	10		T152	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T2	12		T13	12		T192	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T37	14		T46	16		T22	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T6	7		T35	12		T37	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1303	1			T8	15		T42	33		T44	39
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T23	4		T24	6		T161	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T46	2		T119	5		T23	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T35	10		T227	8		T217	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T31	5		T228	17		T224	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T119	12		T22	12		T14	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T40	1		T31	10		T129	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T57	12		T225	15		T262	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T58	4		T88	7		T143	20
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T119	12		T58	13		T130	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T30	11		T129	4		T143	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T46	12		T57	6		T58	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T17	2		T340	15		T177	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T244	11		T342	2		T273	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T27	9		T16	3		T209	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T237	11		T134	13		T243	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T17	4		T129	1		T234	11
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T46	11		T57	8		T185	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T7	11		T16	6		T231	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T134	1		T326	12		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T27	12		T176	10		T149	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T43	16		T122	10		T143	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T43	1		T118	1		T94	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T2	14		T141	1		T13	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T5	2		T37	15		T46	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T6	6		T35	14		T37	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T141	1		T57	3		T206	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T23	5		T24	1		T120	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1372	1			T1	1		T4	8		T8	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T9	1		T35	13		T162	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T38	5		T88	2		T172	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T5	1		T119	13		T22	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T9	1		T40	4		T148	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T57	3		T120	1		T206	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T215	14		T121	1		T58	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T119	13		T206	13		T58	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T12	5		T30	14		T207	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	310	1			T128	18		T58	1		T184	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18050	1			T3	12		T5	112		T7	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T17	2		T129	4		T234	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T46	12		T57	6		T285	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T16	3		T231	4		T312	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T134	13		T326	10		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T27	9		T95	9		T211	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T43	3		T143	3		T237	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T43	7		T95	1		T152	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T2	12		T13	12		T142	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T37	14		T46	16		T22	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T6	7		T35	12		T37	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T57	1		T41	1		T153	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T23	4		T24	6		T161	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1379	1			T8	15		T42	33		T44	39
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T35	10		T227	8		T191	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T31	5		T228	17		T163	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T119	12		T22	12		T14	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T40	1		T31	10		T129	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T57	12		T225	15		T262	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T58	4		T88	7		T143	20
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T119	12		T58	13		T130	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T30	11		T143	4		T225	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T58	2		T123	11		T214	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22925

1

T1

1

T2

14

T3

12

auto[1]

auto[0]

4218

1

T2

12

T6

7

T8

15