Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27143

1

T1

1

T2

26

T3

12

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23671

1

T1

1

T3

12

T4

8

auto[ADC_CTRL_FILTER_COND_OUT]

3472

1

T2

26

T5

1

T6

13

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20792

1

T3

12

T5

115

T6

13

auto[1]

6351

1

T1

1

T2

26

T4

8

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23175

1

T1

1

T2

13

T3

12

auto[1]

3968

1

T2

13

T4

7

T5

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	69	1			T57	14		T129	5		T244	14
values[0]	68	1			T7	11		T16	9		T231	7
values[1]	555	1			T43	19		T27	21		T149	1
values[2]	701	1			T2	26		T43	8		T141	1
values[3]	771	1			T5	2		T6	13		T35	26
values[4]	580	1			T141	1		T23	9		T24	7
values[5]	3081	1			T1	1		T4	8		T8	17
values[6]	640	1			T5	1		T119	25		T38	5
values[7]	698	1			T9	1		T57	15		T120	1
values[8]	732	1			T119	25		T215	14		T206	13
values[9]	1198	1			T46	23		T12	5		T30	25
minimum	18050	1			T3	12		T5	112		T7	2

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	765	1			T7	11		T43	19		T27	21
values[1]	744	1			T2	26		T5	2		T37	6
values[2]	737	1			T6	13		T35	26		T37	52
values[3]	2971	1			T1	1		T4	8		T8	17
values[4]	646	1			T9	1		T35	23		T46	3
values[5]	641	1			T5	1		T119	25		T38	5
values[6]	670	1			T9	1		T57	15		T206	6
values[7]	789	1			T215	14		T206	13		T58	32
values[8]	884	1			T46	23		T119	25		T12	5
values[9]	201	1			T17	6		T185	1		T241	7
minimum	18095	1			T3	12		T5	112		T7	2

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22925

1

T1

1

T2

14

T3

12

auto[1]

4218

1

T2

12

T6

7

T8

15

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T7	1		T43	4		T27	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T122	1		T143	4		T237	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T5	1		T37	1		T43	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T2	13		T141	1		T13	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T37	15		T46	17		T141	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T6	8		T35	13		T37	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1634	1			T1	1		T4	1		T8	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T23	5		T24	7		T120	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T46	3		T119	6		T23	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T9	1		T35	11		T162	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T38	2		T88	1		T148	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T5	1		T119	13		T22	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T9	1		T121	1		T40	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T57	13		T206	1		T184	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T215	1		T58	5		T88	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T206	1		T58	14		T15	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T12	3		T30	12		T207	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T46	13		T119	13		T128	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T17	4		T233	11		T338	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T185	1		T241	1		T132	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17930	1			T3	12		T5	112		T9	140
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T134	14		T260	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T7	10		T43	15		T27	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T122	9		T143	7		T237	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T5	1		T37	5		T23	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T2	13		T13	12		T192	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T37	8		T46	17		T162	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T6	5		T35	13		T37	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	974	1			T4	7		T127	25		T29	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T23	4		T214	10		T205	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T23	13		T27	16		T57	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T35	12		T162	16		T227	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T38	3		T88	1		T31	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T119	12		T14	3		T209	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T31	8		T129	11		T151	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T57	2		T206	5		T123	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T215	13		T58	5		T143	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T206	12		T58	8		T130	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T12	2		T30	13		T143	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T46	10		T119	12		T128	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T17	2		T298	1		T204	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T241	6		T244	2		T342	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T7	2		T9	3		T38	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T260	7		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T129	5		T343	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T57	7		T244	12		T145	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T7	1		T16	5		T231	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T309	1		T248	13		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T43	4		T27	10		T149	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T122	1		T143	4		T237	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T43	8		T176	1		T89	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T2	13		T141	1		T13	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T5	1		T37	16		T118	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T6	8		T35	13		T37	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T141	1		T57	2		T206	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T23	5		T24	7		T120	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1689	1			T1	1		T4	1		T8	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T9	1		T35	11		T149	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T38	2		T88	1		T172	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T5	1		T119	13		T22	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T9	1		T40	5		T148	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T57	13		T120	1		T206	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T215	1		T121	1		T58	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T119	13		T206	1		T58	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	327	1			T12	3		T30	12		T207	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T46	13		T128	1		T58	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17910	1			T3	12		T5	112		T9	140
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T343	19		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T57	7		T244	2		T339	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T7	10		T16	4		T231	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T309	1		T248	13		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T43	15		T27	11		T211	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T122	9		T143	7		T237	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T176	9		T89	8		T151	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T2	13		T13	12		T142	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T5	1		T37	13		T46	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T6	5		T35	13		T37	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T57	2		T206	9		T41	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T23	4		T214	10		T242	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1028	1			T4	7		T127	25		T23	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T35	12		T227	11		T191	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T38	3		T88	1		T31	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T119	12		T14	3		T162	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T31	8		T129	11		T224	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T57	2		T206	5		T209	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T215	13		T58	5		T143	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T119	12		T206	12		T58	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T12	2		T30	13		T17	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T46	10		T128	17		T123	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T7	2		T9	3		T38	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T7	11		T43	16		T27	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T122	10		T143	8		T237	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T5	2		T37	6		T43	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T2	14		T141	1		T13	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T37	9		T46	18		T141	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T6	6		T35	14		T37	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1312	1			T1	1		T4	8		T8	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T23	5		T24	1		T120	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T46	1		T119	1		T23	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T9	1		T35	13		T162	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T38	5		T88	2		T148	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T5	1		T119	13		T22	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T9	1		T121	1		T40	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T57	3		T206	6		T184	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T215	14		T58	6		T88	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T206	13		T58	9		T15	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T12	5		T30	14		T207	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T46	11		T119	13		T128	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T17	4		T233	1		T338	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T185	1		T241	7		T132	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18057	1			T3	12		T5	112		T7	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T134	1		T260	8		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T43	3		T27	9		T95	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T143	3		T237	11		T277	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T43	7		T23	6		T95	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T2	12		T13	12		T192	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T37	14		T46	16		T22	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T6	7		T35	12		T37	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1296	1			T8	15		T42	33		T44	39
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T23	4		T24	6		T161	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T46	2		T119	5		T23	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T35	10		T227	8		T191	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T31	5		T228	17		T224	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T119	12		T22	12		T14	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T40	1		T31	10		T129	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T57	12		T225	15		T262	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T58	4		T88	7		T143	20
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T58	13		T130	14		T236	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T30	11		T129	4		T143	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T46	12		T119	12		T57	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T17	2		T233	10		T298	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T244	11		T342	2		T336	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T231	4		T344	11		T345	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T134	13		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T129	1		T343	20		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T57	8		T244	3		T145	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T7	11		T16	6		T231	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T309	2		T248	14		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T43	16		T27	12		T149	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T122	10		T143	8		T237	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T43	1		T176	10		T89	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T2	14		T141	1		T13	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T5	2		T37	15		T118	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T6	6		T35	14		T37	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T141	1		T57	3		T206	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T23	5		T24	1		T120	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1361	1			T1	1		T4	8		T8	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T9	1		T35	13		T149	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T38	5		T88	2		T172	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T5	1		T119	13		T22	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T9	1		T40	4		T148	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T57	3		T120	1		T206	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T215	14		T121	1		T58	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T119	13		T206	13		T58	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	331	1			T12	5		T30	14		T207	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	363	1			T46	11		T128	18		T58	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18050	1			T3	12		T5	112		T7	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T129	4		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T57	6		T244	11		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T16	3		T231	4		T312	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T248	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T43	3		T27	9		T95	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T143	3		T237	11		T217	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T43	7		T95	1		T225	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T2	12		T13	12		T142	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T37	14		T46	16		T22	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T6	7		T35	12		T37	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T57	1		T41	1		T153	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T23	4		T24	6		T161	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1356	1			T8	15		T42	33		T44	39
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T35	10		T227	8		T191	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T31	5		T228	17		T163	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T119	12		T22	12		T14	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T40	1		T31	10		T129	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T57	12		T225	15		T262	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T58	4		T88	7		T143	20
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T119	12		T58	13		T130	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T30	11		T17	2		T143	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T46	12		T58	2		T123	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22925

1

T1

1

T2

14

T3

12

auto[1]

auto[0]

4218

1

T2

12

T6

7

T8

15