Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T6	6		T37	15		T206	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T118	1		T46	1		T119	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T184	1		T94	1		T233	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T5	2		T9	1		T119	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T43	16		T23	5		T58	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T141	1		T27	15		T192	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1394	1			T1	1		T4	8		T8	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T215	14		T149	1		T214	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T38	5		T23	5		T88	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T9	1		T128	18		T139	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T46	18		T22	2		T27	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T2	14		T24	1		T120	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T13	16		T120	1		T162	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T7	11		T119	13		T120	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T23	14		T176	10		T14	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T43	1		T30	14		T57	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T37	18		T38	5		T12	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T5	1		T35	13		T46	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T35	14		T57	3		T149	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T132	1		T230	1		T234	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18050	1			T3	12		T5	112		T7	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T235	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T6	7		T37	14		T142	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T46	2		T119	12		T27	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T233	10		T246	2		T236	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T119	5		T161	12		T31	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T43	3		T23	4		T58	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T27	11		T192	11		T40	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1453	1			T8	15		T42	33		T44	39
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T214	13		T237	11		T211	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T23	6		T88	7		T129	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T95	9		T225	5		T247	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T46	16		T22	28		T27	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T2	12		T24	6		T58	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T13	12		T162	6		T224	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T119	12		T58	13		T95	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T23	6		T14	3		T41	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T43	7		T30	11		T57	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T37	11		T38	4		T17	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T35	10		T46	12		T227	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T35	12		T57	12		T248	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T230	5		T234	8		T182	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T229	1		T230	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T231	9		T232	13		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T6	6		T37	15		T206	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T118	1		T141	1		T57	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T94	1		T229	1		T233	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T46	1		T119	14		T141	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T43	16		T23	5		T58	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T5	2		T9	1		T27	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1366	1			T1	1		T4	8		T8	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T9	1		T215	14		T40	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T38	5		T27	3		T48	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T128	18		T139	3		T95	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T22	2		T23	5		T206	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T24	1		T120	1		T58	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T46	18		T120	1		T162	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T2	14		T7	11		T119	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T38	5		T176	10		T13	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T43	1		T30	14		T121	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	338	1			T35	14		T37	18		T12	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	348	1			T5	1		T35	13		T46	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18050	1			T3	12		T5	112		T7	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T230	5		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T231	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T6	7		T37	14		T142	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T57	1		T249	3		T242	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T233	10		T246	2		T243	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T46	2		T119	17		T27	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T43	3		T23	4		T58	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T27	11		T192	11		T228	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1428	1			T8	15		T42	33		T44	39
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T40	1		T214	13		T237	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T27	13		T88	7		T18	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T95	9		T225	5		T236	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T22	28		T23	6		T123	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T24	6		T58	4		T250	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T46	16		T162	6		T224	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T2	12		T119	12		T57	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T38	4		T13	12		T41	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T43	7		T30	11		T95	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T35	12		T37	11		T23	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T35	10		T46	12		T227	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22925

1

T1

1

T2

14

T3

12

auto[1]

auto[0]

4218

1

T2

12

T6

7

T8

15