Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27143

1

T1

1

T2

26

T3

12

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23794

1

T1

1

T3

12

T4

8

auto[ADC_CTRL_FILTER_COND_OUT]

3349

1

T2

26

T5

3

T6

13

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21235

1

T2

26

T3

12

T5

114

auto[1]

5908

1

T1

1

T4

8

T5

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23175

1

T1

1

T2

13

T3

12

auto[1]

3968

1

T2

13

T4

7

T5

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	3	1			T251	3		-	-		-	-
values[0]	38	1			T225	6		T252	1		T253	4
values[1]	767	1			T5	2		T7	11		T37	6
values[2]	834	1			T2	26		T35	26		T46	57
values[3]	791	1			T9	1		T119	25		T38	9
values[4]	563	1			T12	5		T23	11		T162	17
values[5]	3090	1			T1	1		T4	8		T5	1
values[6]	558	1			T6	13		T35	23		T141	1
values[7]	825	1			T37	29		T43	8		T118	1
values[8]	633	1			T9	1		T43	19		T119	25
values[9]	991	1			T37	23		T22	13		T27	16
minimum	18050	1			T3	12		T5	112		T7	2

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	839	1			T5	2		T7	11		T37	6
values[1]	991	1			T2	26		T35	26		T46	57
values[2]	693	1			T9	1		T141	1		T121	1
values[3]	2986	1			T1	1		T4	8		T8	17
values[4]	616	1			T5	1		T46	3		T23	11
values[5]	689	1			T6	13		T35	23		T141	1
values[6]	782	1			T37	29		T43	8		T118	1
values[7]	497	1			T9	1		T43	19		T38	5
values[8]	785	1			T22	13		T27	16		T128	18
values[9]	136	1			T37	23		T150	1		T17	3
minimum	18129	1			T3	12		T5	112		T7	2

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22925

1

T1

1

T2

14

T3

12

auto[1]

4218

1

T2

12

T6

7

T8

15

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T37	1		T120	2		T58	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T5	1		T7	1		T119	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T22	17		T23	7		T27	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T2	13		T35	13		T46	30
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T121	1		T58	3		T17	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T9	1		T141	1		T162	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1700	1			T1	1		T4	1		T8	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T13	16		T31	6		T143	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T46	3		T24	7		T95	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T5	1		T23	7		T215	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T35	11		T23	5		T27	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T6	8		T141	1		T176	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T118	1		T119	13		T185	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T37	12		T43	8		T139	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T9	1		T43	4		T38	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T40	5		T214	14		T254	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T57	7		T58	5		T89	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T22	13		T27	14		T128	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T17	2		T129	5		T134	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T37	15		T150	1		T255	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17938	1			T3	12		T5	112		T9	140
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T256	7		T257	11		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T37	5		T58	8		T209	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T5	1		T7	10		T139	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T23	13		T27	14		T57	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T2	13		T35	13		T46	27
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T17	2		T143	13		T191	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T162	16		T214	9		T236	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1002	1			T4	7		T127	25		T12	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T13	12		T31	8		T143	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T123	1		T221	4		T217	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T23	4		T215	13		T206	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T35	12		T23	4		T27	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T6	5		T176	9		T41	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T119	12		T211	2		T152	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T37	17		T139	6		T122	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T43	15		T38	3		T57	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T214	10		T245	4		T234	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T57	7		T58	5		T89	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T27	2		T128	17		T241	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T17	1		T222	2		T258	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T37	8		T255	4		T259	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T7	2		T9	3		T38	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T257	11		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T251	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T225	6		T252	1		T253	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T37	1		T120	1		T58	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T5	1		T7	1		T119	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T27	12		T57	13		T120	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T2	13		T35	13		T46	30
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T22	17		T23	7		T121	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T9	1		T119	13		T38	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T12	3		T130	15		T185	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T23	7		T162	1		T31	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1715	1			T1	1		T4	1		T8	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T5	1		T13	16		T206	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T35	11		T23	5		T30	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T6	8		T141	1		T215	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T118	1		T27	10		T224	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T37	12		T43	8		T176	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T9	1		T43	4		T119	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T184	1		T214	14		T254	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	340	1			T57	9		T89	1		T17	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T37	15		T22	13		T27	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17910	1			T3	12		T5	112		T9	140
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T251	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T253	3		T260	7		T219	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T37	5		T58	8		T209	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T5	1		T7	10		T139	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T27	14		T57	2		T261	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T2	13		T35	13		T46	27
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T23	13		T31	8		T17	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T119	12		T38	4		T192	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T12	2		T130	12		T262	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T23	4		T162	16		T31	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1022	1			T4	7		T127	25		T29	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T13	12		T206	5		T263	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T35	12		T23	4		T30	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T6	5		T215	13		T139	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T27	11		T224	6		T211	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T37	17		T176	9		T122	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T43	15		T119	12		T38	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T214	10		T152	2		T245	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T57	9		T89	13		T17	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T37	8		T27	2		T128	17
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T7	2		T9	3		T38	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T37	6		T120	2		T58	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T5	2		T7	11		T119	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T22	1		T23	14		T27	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T2	14		T35	14		T46	29
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T121	1		T58	1		T17	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T9	1		T141	1		T162	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1349	1			T1	1		T4	8		T8	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T13	16		T31	9		T143	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T46	1		T24	1		T95	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T5	1		T23	5		T215	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T35	13		T23	5		T27	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T6	6		T141	1		T176	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T118	1		T119	13		T185	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T37	18		T43	1		T139	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T9	1		T43	16		T38	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T40	4		T214	11		T254	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T57	8		T58	6		T89	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T22	1		T27	3		T128	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T17	2		T129	1		T134	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T37	9		T150	1		T255	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18075	1			T3	12		T5	112		T7	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T256	1		T257	12		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T58	13		T228	7		T225	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T119	5		T225	8		T209	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T22	16		T23	6		T27	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T2	12		T35	12		T46	28
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T58	2		T17	2		T143	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T161	12		T214	12		T236	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1353	1			T8	15		T42	33		T44	39
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T13	12		T31	5		T143	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T46	2		T24	6		T95	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T23	6		T95	1		T62	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T35	10		T23	4		T27	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T6	7		T41	1		T217	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T119	12		T211	3		T153	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T37	11		T43	7		T227	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T43	3		T57	1		T14	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T40	1		T214	13		T246	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T57	6		T58	4		T18	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T22	12		T27	13		T88	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T17	1		T129	4		T134	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T37	14		T264	2		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T265	13		T188	12		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T256	6		T257	10		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	8	40	83.33	8

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T251	3		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T225	1		T252	1		T253	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T37	6		T120	1		T58	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T5	2		T7	11		T119	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T27	15		T57	3		T120	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T2	14		T35	14		T46	29
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T22	1		T23	14		T121	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T9	1		T119	13		T38	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T12	5		T130	13		T185	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T23	5		T162	17		T31	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1370	1			T1	1		T4	8		T8	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T5	1		T13	16		T206	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T35	13		T23	5		T30	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T6	6		T141	1		T215	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T118	1		T27	12		T224	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T37	18		T43	1		T176	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T9	1		T43	16		T119	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T184	1		T214	11		T254	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	303	1			T57	11		T89	14		T17	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T37	9		T22	1		T27	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18050	1			T3	12		T5	112		T7	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T225	5		T219	16		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T58	13		T124	7		T250	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T119	5		T225	8		T163	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T27	11		T57	12		T228	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T2	12		T35	12		T46	28
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T22	16		T23	6		T58	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T119	12		T38	4		T192	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T130	14		T262	7		T244	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T23	6		T31	5		T143	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1367	1			T8	15		T42	33		T44	39
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T13	12		T263	1		T266	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T35	10		T23	4		T30	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T6	7		T95	1		T41	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T27	9		T224	3		T211	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T37	11		T43	7		T227	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T43	3		T119	12		T14	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T214	13		T152	3		T246	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T57	7		T17	1		T129	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T37	14		T22	12		T27	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22925

1

T1

1

T2

14

T3

12

auto[1]

auto[0]

4218

1

T2

12

T6

7

T8

15