Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27143

1

T1

1

T2

26

T3

12

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23641

1

T1

1

T2

26

T3

12

auto[ADC_CTRL_FILTER_COND_OUT]

3502

1

T6

13

T7

11

T9

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20884

1

T2

26

T3

12

T5

112

auto[1]

6259

1

T1

1

T4

8

T5

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23175

1

T1

1

T2

13

T3

12

auto[1]

3968

1

T2

13

T4

7

T5

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	22	1			T214	22		-	-		-	-
values[0]	85	1			T132	1		T217	11		T267	9
values[1]	551	1			T35	23		T37	23		T119	25
values[2]	816	1			T7	11		T9	1		T119	31
values[3]	704	1			T35	26		T139	3		T40	5
values[4]	773	1			T5	1		T9	1		T46	34
values[5]	657	1			T43	19		T46	3		T141	1
values[6]	620	1			T141	1		T57	15		T149	2
values[7]	514	1			T22	17		T122	10		T227	20
values[8]	3090	1			T1	1		T2	26		T4	8
values[9]	1261	1			T5	2		T6	13		T37	6
minimum	18050	1			T3	12		T5	112		T7	2

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	815	1			T37	23		T119	25		T23	11
values[1]	925	1			T7	11		T9	1		T35	23
values[2]	553	1			T5	1		T9	1		T35	26
values[3]	862	1			T43	19		T46	34		T141	1
values[4]	506	1			T46	3		T24	7		T206	6
values[5]	656	1			T141	1		T22	17		T57	15
values[6]	3035	1			T1	1		T4	8		T8	17
values[7]	744	1			T2	26		T5	2		T6	13
values[8]	800	1			T43	8		T22	13		T27	21
values[9]	195	1			T37	6		T118	1		T23	9
minimum	18052	1			T3	12		T5	112		T7	2

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22925

1

T1

1

T2

14

T3

12

auto[1]

4218

1

T2

12

T6

7

T8

15

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T119	13		T128	1		T206	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T37	15		T23	7		T57	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T215	1		T139	1		T143	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	334	1			T7	1		T9	1		T35	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T5	1		T35	13		T40	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T9	1		T27	14		T162	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T141	1		T27	12		T192	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T43	4		T46	17		T206	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T46	3		T24	7		T206	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T123	1		T17	2		T225	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T141	1		T149	1		T150	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T22	17		T57	13		T184	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1717	1			T1	1		T4	1		T8	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T46	13		T227	9		T94	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T2	13		T5	1		T37	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T6	8		T38	2		T12	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T57	7		T121	1		T142	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T43	8		T22	13		T27	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T37	1		T118	1		T23	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T58	5		T209	2		T268	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17912	1			T3	12		T5	112		T9	140
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T119	12		T128	17		T206	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T37	8		T23	4		T57	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T215	13		T139	2		T143	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T7	10		T35	12		T119	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T35	13		T41	3		T31	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T27	2		T162	16		T214	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T27	14		T192	9		T123	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T43	15		T46	17		T206	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T206	5		T204	17		T269	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T123	1		T17	1		T135	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T143	4		T224	6		T217	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T57	2		T123	11		T16	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1031	1			T4	7		T127	25		T38	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T46	10		T227	11		T191	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T2	13		T5	1		T37	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T6	5		T38	3		T12	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T57	7		T142	5		T214	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T27	11		T89	13		T211	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T37	5		T23	4		T263	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T58	5		T209	1		T270	17
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T7	2		T9	3		T38	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T214	13		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T267	1		T187	1		T271	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T132	1		T217	11		T235	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T119	13		T128	1		T206	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T35	11		T37	15		T23	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T215	1		T129	10		T143	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T7	1		T9	1		T119	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T35	13		T139	1		T40	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T148	1		T214	14		T152	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T5	1		T192	12		T161	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T9	1		T46	17		T27	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T46	3		T141	1		T24	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T43	4		T129	5		T225	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T141	1		T149	2		T172	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T57	13		T184	1		T148	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T122	1		T224	4		T243	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T22	17		T227	9		T94	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1743	1			T1	1		T2	13		T4	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T46	13		T12	3		T139	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	311	1			T5	1		T37	1		T118	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	356	1			T6	8		T43	8		T38	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17910	1			T3	12		T5	112		T9	140
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T214	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T267	8		T187	10		T272	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T235	11		T273	7		T274	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T119	12		T128	17		T206	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T35	12		T37	8		T23	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T215	13		T129	11		T143	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T7	10		T119	12		T30	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T35	13		T139	2		T41	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T214	10		T152	2		T210	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T192	9		T123	1		T31	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T46	17		T27	2		T206	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T27	14		T206	5		T143	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T43	15		T135	13		T193	21
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T217	11		T244	4		T189	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T57	2		T123	12		T17	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T122	9		T224	6		T243	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T227	11		T16	4		T191	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1024	1			T2	13		T4	7		T37	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T46	10		T12	2		T139	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	295	1			T5	1		T37	5		T23	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T6	5		T38	3		T27	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T7	2		T9	3		T38	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T119	13		T128	18		T206	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T37	9		T23	5		T57	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T215	14		T139	3		T143	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	330	1			T7	11		T9	1		T35	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T5	1		T35	14		T40	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T9	1		T27	3		T162	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T141	1		T27	15		T192	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T43	16		T46	18		T206	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T46	1		T24	1		T206	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T123	2		T17	2		T225	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T141	1		T149	1		T150	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T22	1		T57	3		T184	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1379	1			T1	1		T4	8		T8	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T46	11		T227	12		T94	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T2	14		T5	2		T37	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T6	6		T38	5		T12	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T57	8		T121	1		T142	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T43	1		T22	1		T27	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T37	6		T118	1		T23	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T58	6		T209	2		T268	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18052	1			T3	12		T5	112		T7	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T119	12		T129	9		T223	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T37	14		T23	6		T57	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T143	3		T228	7		T237	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T35	10		T119	17		T30	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T35	12		T40	1		T41	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T27	13		T214	13		T152	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T27	11		T192	11		T161	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T43	3		T46	16		T129	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T46	2		T24	6		T88	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T17	1		T225	15		T246	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T143	4		T224	3		T163	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T22	16		T57	12		T123	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1369	1			T8	15		T42	33		T44	39
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T46	12		T227	8		T191	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T2	12		T37	11		T23	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T6	7		T95	9		T31	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T57	6		T142	8		T214	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T43	7		T22	12		T27	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T23	4		T263	1		T275	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T58	4		T209	1		T270	15

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T214	10		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T267	9		T187	11		T271	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T132	1		T217	1		T235	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T119	13		T128	18		T206	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T35	13		T37	9		T23	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T215	14		T129	12		T143	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T7	11		T9	1		T119	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T35	14		T139	3		T40	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T148	1		T214	11		T152	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T5	1		T192	10		T161	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T9	1		T46	18		T27	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T46	1		T141	1		T24	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T43	16		T129	1		T225	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T141	1		T149	2		T172	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T57	3		T184	1		T148	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T122	10		T224	7		T243	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T22	1		T227	12		T94	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1367	1			T1	1		T2	14		T4	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T46	11		T12	5		T139	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	375	1			T5	2		T37	6		T118	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	358	1			T6	6		T43	1		T38	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18050	1			T3	12		T5	112		T7	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T214	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T272	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T217	10		T273	6		T274	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T119	12		T223	11		T136	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T35	10		T37	14		T23	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T129	9		T143	3		T228	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T119	17		T30	11		T14	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T35	12		T40	1		T41	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T214	13		T152	3		T210	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T192	11		T161	12		T31	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T46	16		T27	13		T225	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T46	2		T24	6		T27	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T43	3		T129	4		T225	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T163	16		T217	9		T244	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T57	12		T123	11		T17	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T224	3		T243	9		T266	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T22	16		T227	8		T16	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1400	1			T2	12		T8	15		T37	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T46	12		T95	9		T133	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T23	4		T57	6		T142	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T6	7		T43	7		T22	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22925

1

T1

1

T2

14

T3

12

auto[1]

auto[0]

4218

1

T2

12

T6

7

T8

15