Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27143

1

T1

1

T2

26

T3

12

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

24025

1

T1

1

T3

12

T4

8

auto[ADC_CTRL_FILTER_COND_OUT]

3118

1

T2

26

T6

13

T9

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21154

1

T2

26

T3

12

T5

108

auto[1]

5989

1

T1

1

T4

8

T5

7

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23175

1

T1

1

T2

13

T3

12

auto[1]

3968

1

T2

13

T4

7

T5

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	453	1			T5	4		T9	6		T10	10
values[0]	18	1			T50	1		T153	6		T216	11
values[1]	590	1			T43	19		T118	1		T38	5
values[2]	3000	1			T1	1		T2	26		T4	8
values[3]	556	1			T9	1		T119	6		T224	10
values[4]	666	1			T5	2		T38	9		T22	13
values[5]	553	1			T37	6		T119	25		T141	1
values[6]	560	1			T7	11		T37	23		T43	8
values[7]	797	1			T46	34		T27	26		T30	25
values[8]	900	1			T9	1		T141	1		T23	9
values[9]	1389	1			T5	1		T6	13		T35	26
minimum	17661	1			T3	12		T5	108		T7	2

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	751	1			T43	19		T118	1		T38	5
values[1]	3111	1			T1	1		T2	26		T4	8
values[2]	432	1			T119	6		T22	13		T40	5
values[3]	686	1			T5	2		T37	6		T38	9
values[4]	614	1			T7	11		T37	23		T119	25
values[5]	750	1			T43	8		T46	34		T24	7
values[6]	676	1			T23	9		T57	14		T162	13
values[7]	776	1			T9	1		T141	1		T13	28
values[8]	986	1			T5	1		T6	13		T35	26
values[9]	309	1			T37	29		T46	3		T211	6
minimum	18052	1			T3	12		T5	112		T7	2

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22925

1

T1

1

T2

14

T3

12

auto[1]

4218

1

T2

12

T6

7

T8

15

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T43	4		T38	2		T48	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T118	1		T23	7		T176	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1701	1			T1	1		T4	1		T8	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T2	13		T9	1		T35	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T119	6		T22	13		T40	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T17	2		T241	1		T276	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T5	1		T37	1		T38	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T27	10		T215	1		T206	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T7	1		T37	15		T139	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T119	13		T94	1		T95	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T46	17		T24	7		T30	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T43	8		T27	12		T120	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T57	7		T149	1		T207	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T23	5		T162	7		T185	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T13	16		T184	1		T214	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T9	1		T141	1		T120	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	349	1			T5	1		T35	13		T12	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T6	8		T119	13		T57	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T46	3		T211	4		T209	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T37	12		T152	5		T277	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17911	1			T3	12		T5	112		T9	140
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T278	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T43	15		T38	3		T89	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T23	13		T176	9		T143	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1053	1			T4	7		T127	25		T46	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T2	13		T35	12		T206	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T245	4		T279	13		T280	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T17	1		T241	6		T133	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T5	1		T37	5		T38	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T27	11		T215	13		T206	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T7	10		T37	8		T139	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T119	12		T217	11		T281	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T46	17		T30	13		T122	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T27	14		T227	11		T236	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T57	7		T17	2		T237	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T23	4		T162	6		T209	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T13	12		T214	10		T282	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T192	9		T18	1		T262	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T35	13		T12	2		T23	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T6	5		T119	12		T57	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T211	2		T209	9		T283	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T37	17		T152	2		T243	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T7	2		T9	3		T38	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	399	1			T5	4		T9	6		T10	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T37	12		T284	2		T187	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T50	1		T153	6		T216	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T43	4		T38	2		T48	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T118	1		T184	1		T123	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1688	1			T1	1		T4	1		T8	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T2	13		T35	11		T23	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T119	6		T224	4		T245	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T9	1		T241	1		T133	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T5	1		T38	5		T22	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T27	10		T215	1		T206	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T37	1		T141	1		T121	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T119	13		T94	1		T95	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T7	1		T37	15		T24	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T43	8		T120	1		T185	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T46	17		T30	12		T57	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T27	12		T227	9		T148	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T150	1		T17	4		T214	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T9	1		T141	1		T23	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	510	1			T5	1		T35	13		T46	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T6	8		T119	13		T57	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17521	1			T3	12		T5	108		T9	134
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T129	11		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T37	17		T284	5		T187	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T216	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T43	15		T38	3		T16	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T123	1		T143	13		T151	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1029	1			T4	7		T127	25		T46	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T2	13		T35	12		T23	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T224	6		T245	4		T247	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T241	6		T133	10		T196	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T5	1		T38	4		T128	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T27	11		T215	13		T206	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T37	5		T58	5		T31	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T119	12		T217	11		T285	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T7	10		T37	8		T139	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T283	15		T280	12		T286	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T46	17		T30	13		T57	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T27	14		T227	11		T209	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T17	2		T214	10		T151	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T23	4		T162	6		T262	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	339	1			T35	13		T12	2		T23	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T6	5		T119	12		T57	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T7	2		T9	3		T38	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T43	16		T38	5		T48	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T118	1		T23	14		T176	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1396	1			T1	1		T4	8		T8	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T2	14		T9	1		T35	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T119	1		T22	1		T40	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T17	2		T241	7		T276	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T5	2		T37	6		T38	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T27	12		T215	14		T206	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T7	11		T37	9		T139	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T119	13		T94	1		T95	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T46	18		T24	1		T30	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T43	1		T27	15		T120	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T57	8		T149	1		T207	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T23	5		T162	7		T185	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T13	16		T184	1		T214	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T9	1		T141	1		T120	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T5	1		T35	14		T12	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T6	6		T119	13		T57	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T46	1		T211	3		T209	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T37	18		T152	4		T277	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18051	1			T3	12		T5	112		T7	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T278	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T43	3		T95	1		T16	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T23	6		T143	20		T133	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1358	1			T8	15		T42	33		T44	39
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T2	12		T35	10		T225	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T119	5		T22	12		T40	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T17	1		T133	8		T181	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T38	4		T58	13		T62	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T27	9		T130	14		T225	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T37	14		T58	4		T31	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T119	12		T95	9		T225	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T46	16		T24	6		T30	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T43	7		T27	11		T227	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T57	6		T17	2		T237	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T23	4		T162	6		T209	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T13	12		T214	13		T282	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T192	11		T129	4		T18	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T35	12		T22	16		T23	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T6	7		T119	12		T57	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T46	2		T211	3		T124	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T37	11		T152	3		T277	2

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	401	1			T5	4		T9	6		T10	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T37	18		T284	7		T187	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T50	1		T153	1		T216	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T43	16		T38	5		T48	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T118	1		T184	1		T123	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1373	1			T1	1		T4	8		T8	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T2	14		T35	13		T23	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T119	1		T224	7		T245	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T9	1		T241	7		T133	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T5	2		T38	5		T22	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T27	12		T215	14		T206	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T37	6		T141	1		T121	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T119	13		T94	1		T95	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T7	11		T37	9		T24	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T43	1		T120	1		T185	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T46	18		T30	14		T57	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T27	15		T227	12		T148	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T150	1		T17	4		T214	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T9	1		T141	1		T23	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	434	1			T5	1		T35	14		T46	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	302	1			T6	6		T119	13		T57	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17661	1			T3	12		T5	108		T7	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T129	9		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T37	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T153	5		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T43	3		T95	1		T16	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T143	20		T133	10		T287	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1344	1			T8	15		T42	33		T44	39
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T2	12		T35	10		T23	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T119	5		T224	3		T247	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T133	8		T181	11		T208	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T38	4		T22	12		T40	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T27	9		T17	1		T130	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T58	4		T31	10		T228	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T119	12		T95	9		T225	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T37	14		T24	6		T143	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T43	7		T153	5		T288	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T46	16		T30	11		T57	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T27	11		T227	8		T233	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T17	2		T214	13		T282	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T23	4		T162	6		T262	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	415	1			T35	12		T46	2		T22	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T6	7		T119	12		T57	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22925

1

T1

1

T2

14

T3

12

auto[1]

auto[0]

4218

1

T2

12

T6

7

T8

15