Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27143

1

T1

1

T2

26

T3

12

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23980

1

T1

1

T3

12

T4

8

auto[ADC_CTRL_FILTER_COND_OUT]

3163

1

T2

26

T6

13

T9

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20880

1

T3

12

T5

108

T6

13

auto[1]

6263

1

T1

1

T2

26

T4

8

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23175

1

T1

1

T2

13

T3

12

auto[1]

3968

1

T2

13

T4

7

T5

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	719	1			T5	4		T6	13		T9	6
values[0]	1	1			T50	1		-	-		-	-
values[1]	633	1			T43	19		T118	1		T38	5
values[2]	3018	1			T1	1		T2	26		T4	8
values[3]	485	1			T9	1		T119	6		T57	4
values[4]	721	1			T5	2		T38	9		T22	13
values[5]	529	1			T7	11		T37	6		T119	25
values[6]	589	1			T37	23		T43	8		T46	34
values[7]	762	1			T27	26		T30	25		T57	14
values[8]	826	1			T9	1		T141	1		T23	9
values[9]	1199	1			T5	1		T35	26		T46	3
minimum	17661	1			T3	12		T5	108		T7	2

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	655	1			T35	23		T43	19		T118	1
values[1]	3059	1			T1	1		T2	26		T4	8
values[2]	458	1			T119	6		T215	14		T40	5
values[3]	699	1			T5	2		T37	6		T38	9
values[4]	621	1			T7	11		T37	23		T119	25
values[5]	727	1			T43	8		T46	34		T24	7
values[6]	679	1			T23	9		T30	25		T57	14
values[7]	805	1			T9	1		T141	1		T13	28
values[8]	1118	1			T5	1		T6	13		T35	26
values[9]	189	1			T37	29		T46	3		T16	2
minimum	18133	1			T3	12		T5	112		T7	2

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22925

1

T1

1

T2

14

T3

12

auto[1]

4218

1

T2

12

T6

7

T8

15

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T43	4		T48	1		T89	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T35	11		T118	1		T23	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1678	1			T1	1		T4	1		T8	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T2	13		T9	1		T206	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T119	6		T40	5		T185	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T215	1		T17	2		T241	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T5	1		T37	1		T38	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T141	1		T22	13		T128	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T7	1		T37	15		T139	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T119	13		T95	10		T143	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T46	17		T24	7		T120	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T43	8		T27	12		T120	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T23	5		T30	12		T57	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T162	7		T149	1		T237	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T9	1		T192	12		T58	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T141	1		T13	16		T120	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	366	1			T5	1		T12	3		T22	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T6	8		T35	13		T119	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T46	3		T16	2		T211	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T37	12		T209	2		T289	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17931	1			T3	12		T5	112		T9	140
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T287	3		T255	1		T248	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T43	15		T89	13		T16	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T35	12		T23	13		T176	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1004	1			T4	7		T127	25		T46	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T2	13		T206	12		T31	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T245	4		T133	10		T247	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T215	13		T17	1		T241	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T5	1		T37	5		T38	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T128	17		T206	9		T130	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T7	10		T37	8		T139	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T119	12		T143	7		T217	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T46	17		T227	11		T89	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T27	14		T122	9		T236	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T23	4		T30	13		T57	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T162	6		T237	13		T209	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T192	9		T214	10		T151	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T13	12		T18	1		T282	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T12	2		T23	4		T123	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T6	5		T35	13		T119	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T211	2		T243	8		T283	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T37	17		T209	9		T284	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T7	2		T9	3		T38	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T287	5		T248	9		T290	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	481	1			T5	4		T9	6		T10	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T6	8		T37	12		T119	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T50	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T43	4		T38	2		T27	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T118	1		T184	1		T249	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1672	1			T1	1		T4	1		T8	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T2	13		T35	11		T23	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T119	6		T57	2		T245	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T9	1		T224	4		T241	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T5	1		T38	5		T27	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T22	13		T128	1		T215	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T7	1		T37	1		T58	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T119	13		T141	1		T121	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T37	15		T46	17		T24	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T43	8		T120	1		T143	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T30	12		T57	7		T227	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T27	12		T149	1		T122	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T9	1		T23	5		T184	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T141	1		T120	1		T162	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	407	1			T5	1		T46	3		T12	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T35	13		T57	13		T13	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17521	1			T3	12		T5	108		T9	134
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T211	2		T242	7		T263	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T6	5		T37	17		T119	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T43	15		T38	3		T27	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T133	21		T287	5		T244	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1009	1			T4	7		T127	25		T46	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T2	13		T35	12		T23	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T57	2		T245	4		T133	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T224	6		T241	6		T291	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T5	1		T38	4		T27	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T128	17		T215	13		T206	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T7	10		T37	5		T58	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T119	12		T217	11		T285	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T37	8		T46	17		T139	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T143	7		T244	4		T292	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T30	13		T57	7		T227	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T27	14		T122	9		T237	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T23	4		T17	2		T214	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T162	6		T282	6		T262	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T12	2		T23	4		T192	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T35	13		T57	2		T13	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T7	2		T9	3		T38	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T43	16		T48	1		T89	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T35	13		T118	1		T23	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1345	1			T1	1		T4	8		T8	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T2	14		T9	1		T206	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T119	1		T40	4		T185	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T215	14		T17	2		T241	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T5	2		T37	6		T38	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T141	1		T22	1		T128	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T7	11		T37	9		T139	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T119	13		T95	1		T143	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T46	18		T24	1		T120	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T43	1		T27	15		T120	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T23	5		T30	14		T57	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T162	7		T149	1		T237	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T9	1		T192	10		T58	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T141	1		T13	16		T120	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	312	1			T5	1		T12	5		T22	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T6	6		T35	14		T119	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T46	1		T16	2		T211	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T37	18		T209	11		T289	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18086	1			T3	12		T5	112		T7	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T287	6		T255	1		T248	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T43	3		T16	3		T143	24
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T35	10		T23	6		T249	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1337	1			T8	15		T42	33		T44	39
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T2	12		T31	5		T224	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T119	5		T40	1		T133	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T17	1		T293	12		T190	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T38	4		T27	9		T58	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T22	12		T130	14		T144	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T37	14		T58	4		T31	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T119	12		T95	9		T143	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T46	16		T24	6		T227	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T43	7		T27	11		T236	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T23	4		T30	11		T57	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T162	6		T237	11		T209	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T192	11		T58	2		T214	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T13	12		T129	4		T18	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	301	1			T22	16		T23	6		T161	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T6	7		T35	12		T119	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T46	2		T211	3		T124	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T37	11		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T95	1		T234	5		T146	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T287	2		T248	10		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	482	1			T5	4		T9	6		T10	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T6	6		T37	18		T119	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T50	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T43	16		T38	5		T27	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T118	1		T184	1		T249	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1352	1			T1	1		T4	8		T8	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T2	14		T35	13		T23	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T119	1		T57	3		T245	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T9	1		T224	7		T241	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T5	2		T38	5		T27	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T22	1		T128	18		T215	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T7	11		T37	6		T58	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T119	13		T141	1		T121	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T37	9		T46	18		T24	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T43	1		T120	1		T143	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T30	14		T57	8		T227	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T27	15		T149	1		T122	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T9	1		T23	5		T184	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T141	1		T120	1		T162	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	321	1			T5	1		T46	1		T12	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	319	1			T35	14		T57	3		T13	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17661	1			T3	12		T5	108		T7	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T88	7		T211	3		T277	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T6	7		T37	11		T119	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T43	3		T27	13		T95	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T249	3		T133	19		T287	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1329	1			T8	15		T42	33		T44	39
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T2	12		T35	10		T23	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T119	5		T57	1		T133	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T224	3		T225	5		T293	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T38	4		T27	9		T40	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T22	12		T17	1		T130	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T58	4		T31	10		T62	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T119	12		T95	9		T225	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T37	14		T46	16		T24	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T43	7		T143	3		T228	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T30	11		T57	6		T227	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T27	11		T237	11		T209	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T23	4		T17	2		T214	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T162	6		T282	5		T262	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	345	1			T46	2		T22	16		T23	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T35	12		T57	12		T13	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22925

1

T1

1

T2

14

T3

12

auto[1]

auto[0]

4218

1

T2

12

T6

7

T8

15