Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27143

1

T1

1

T2

26

T3

12

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23915

1

T1

1

T3

12

T4

8

auto[ADC_CTRL_FILTER_COND_OUT]

3228

1

T2

26

T5

1

T6

13

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21056

1

T2

26

T3

12

T5

112

auto[1]

6087

1

T1

1

T4

8

T5

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23175

1

T1

1

T2

13

T3

12

auto[1]

3968

1

T2

13

T4

7

T5

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	152	1			T120	1		T89	14		T17	3
values[0]	10	1			T225	6		T253	4		-	-
values[1]	793	1			T5	2		T7	11		T37	6
values[2]	876	1			T2	26		T35	26		T46	57
values[3]	746	1			T9	1		T119	25		T38	9
values[4]	574	1			T12	5		T162	17		T31	14
values[5]	3096	1			T1	1		T4	8		T5	1
values[6]	541	1			T6	13		T35	23		T141	1
values[7]	871	1			T37	29		T43	8		T118	1
values[8]	543	1			T9	1		T43	19		T119	25
values[9]	891	1			T37	23		T22	13		T27	16
minimum	18050	1			T3	12		T5	112		T7	2

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	790	1			T5	2		T7	11		T119	6
values[1]	891	1			T2	26		T35	26		T46	57
values[2]	725	1			T9	1		T38	9		T141	1
values[3]	3058	1			T1	1		T4	8		T8	17
values[4]	529	1			T5	1		T46	3		T24	7
values[5]	615	1			T6	13		T35	23		T141	1
values[6]	846	1			T37	29		T43	8		T118	1
values[7]	524	1			T9	1		T43	19		T38	5
values[8]	798	1			T22	13		T27	16		T128	18
values[9]	112	1			T37	23		T129	5		T132	1
minimum	18255	1			T3	12		T5	112		T7	2

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22925

1

T1

1

T2

14

T3

12

auto[1]

4218

1

T2

12

T6

7

T8

15

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T5	1		T120	1		T184	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T7	1		T119	6		T120	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T46	17		T22	17		T23	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T2	13		T35	13		T46	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T121	1		T17	4		T143	21
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T9	1		T38	5		T141	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1667	1			T1	1		T4	1		T8	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T23	7		T13	16		T162	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T24	7		T95	10		T123	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T5	1		T46	3		T215	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T35	11		T23	5		T30	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T6	8		T141	1		T176	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T37	12		T118	1		T119	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T43	8		T139	1		T122	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T9	1		T43	4		T38	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T206	1		T40	5		T214	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T57	7		T89	1		T17	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T22	13		T27	14		T128	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T129	5		T132	1		T134	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T37	15		T264	3		-	-
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17988	1			T3	12		T5	112		T9	140
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T149	1		T88	1		T294	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T5	1		T209	10		T213	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T7	10		T139	2		T58	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T46	17		T23	13		T27	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T2	13		T35	13		T46	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T17	2		T143	13		T191	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T38	4		T214	9		T236	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	982	1			T4	7		T127	25		T12	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T23	4		T13	12		T162	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T123	1		T221	4		T295	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T215	13		T206	5		T123	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T35	12		T23	4		T30	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T6	5		T176	9		T41	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T37	17		T119	12		T27	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T139	6		T122	9		T227	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T43	15		T38	3		T57	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T206	9		T214	10		T234	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T57	7		T89	13		T17	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T27	2		T128	17		T58	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T222	2		T258	10		T283	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T37	8		T264	4		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T7	2		T9	3		T37	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T88	1		T294	3		T189	5

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T89	1		T17	2		T129	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T120	1		T241	1		T223	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T225	6		T253	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T5	1		T37	1		T184	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T7	1		T119	6		T120	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T46	17		T22	17		T27	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T2	13		T35	13		T46	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T23	7		T121	1		T48	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T9	1		T119	13		T38	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T12	3		T185	1		T262	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T162	1		T31	6		T143	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1702	1			T1	1		T4	1		T8	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T5	1		T46	3		T23	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T35	11		T23	5		T30	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T6	8		T141	1		T176	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T37	12		T118	1		T27	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T43	8		T139	1		T122	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T9	1		T43	4		T119	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T206	1		T40	5		T184	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	320	1			T57	9		T143	5		T151	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T37	15		T22	13		T27	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17910	1			T3	12		T5	112		T9	140
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T89	13		T17	1		T241	6
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T241	2		T226	10		T296	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T253	3		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T5	1		T37	5		T212	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T7	10		T139	2		T58	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T46	17		T27	14		T57	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T2	13		T35	13		T46	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T23	13		T31	8		T17	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T119	12		T38	4		T192	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T12	2		T262	9		T135	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T162	16		T31	8		T143	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1006	1			T4	7		T127	25		T29	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T23	4		T13	12		T206	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T35	12		T23	4		T30	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T6	5		T176	9		T215	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T37	17		T27	11		T129	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T139	6		T122	9		T227	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T43	15		T119	12		T38	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T206	9		T214	10		T285	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T57	9		T143	4		T151	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T37	8		T27	2		T128	17
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T7	2		T9	3		T38	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T5	2		T120	1		T184	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T7	11		T119	1		T120	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T46	18		T22	1		T23	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T2	14		T35	14		T46	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T121	1		T17	4		T143	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T9	1		T38	5		T141	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1326	1			T1	1		T4	8		T8	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T23	5		T13	16		T162	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T24	1		T95	1		T123	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T5	1		T46	1		T215	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T35	13		T23	5		T30	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T6	6		T141	1		T176	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T37	18		T118	1		T119	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T43	1		T139	7		T122	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T9	1		T43	16		T38	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T206	10		T40	4		T214	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T57	8		T89	14		T17	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T22	1		T27	3		T128	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T129	1		T132	1		T134	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T37	9		T264	5		-	-
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18140	1			T3	12		T5	112		T7	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T149	1		T88	2		T294	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T228	7		T209	1		T124	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T119	5		T58	13		T225	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T46	16		T22	16		T23	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T2	12		T35	12		T46	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T17	2		T143	20		T191	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T38	4		T161	12		T58	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1323	1			T8	15		T42	33		T44	39
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T23	6		T13	12		T31	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T24	6		T95	9		T233	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T46	2		T95	1		T62	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T35	10		T23	4		T30	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T6	7		T41	1		T297	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T37	11		T119	12		T27	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T43	7		T227	8		T142	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T43	3		T57	1		T14	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T40	1		T214	13		T246	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T57	6		T17	1		T18	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T22	12		T27	13		T58	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T129	4		T134	2		T222	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T37	14		T264	2		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T225	5		T244	11		T298	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T294	2		T189	1		T256	6

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T89	14		T17	2		T129	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T120	1		T241	3		T223	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T225	1		T253	4		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T5	2		T37	6		T184	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T7	11		T119	1		T120	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T46	18		T22	1		T27	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T2	14		T35	14		T46	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T23	14		T121	1		T48	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T9	1		T119	13		T38	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T12	5		T185	1		T262	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T162	17		T31	9		T143	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1354	1			T1	1		T4	8		T8	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T5	1		T46	1		T23	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T35	13		T23	5		T30	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T6	6		T141	1		T176	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T37	18		T118	1		T27	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T43	1		T139	7		T122	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T9	1		T43	16		T119	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T206	10		T40	4		T184	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T57	11		T143	5		T151	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T37	9		T22	1		T27	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18050	1			T3	12		T5	112		T7	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T17	1		T129	4		T299	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T223	11		T296	12		T264	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T225	5		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T124	7		T250	8		T213	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T119	5		T58	13		T225	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T46	16		T22	16		T27	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T2	12		T35	12		T46	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T23	6		T31	10		T17	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T119	12		T38	4		T192	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T262	7		T244	4		T208	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T31	5		T143	3		T130	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1354	1			T8	15		T42	33		T44	39
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T46	2		T23	6		T13	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T35	10		T23	4		T30	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T6	7		T41	1		T62	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T37	11		T27	9		T129	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T43	7		T227	8		T142	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T43	3		T119	12		T14	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T40	1		T214	13		T246	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T57	7		T143	4		T18	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T37	14		T22	12		T27	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22925

1

T1

1

T2

14

T3

12

auto[1]

auto[0]

4218

1

T2

12

T6

7

T8

15