Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27143

1

T1

1

T2

26

T3

12

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23606

1

T1

1

T2

26

T3

12

auto[ADC_CTRL_FILTER_COND_OUT]

3537

1

T6

13

T7

11

T9

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20810

1

T2

26

T3

12

T5

112

auto[1]

6333

1

T1

1

T4

8

T5

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23175

1

T1

1

T2

13

T3

12

auto[1]

3968

1

T2

13

T4

7

T5

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	242	1			T118	1		T27	21		T57	14
values[0]	34	1			T166	1		T187	11		T290	3
values[1]	637	1			T35	23		T37	23		T119	25
values[2]	831	1			T7	11		T9	1		T119	31
values[3]	641	1			T35	26		T139	3		T40	5
values[4]	761	1			T5	1		T9	1		T46	34
values[5]	621	1			T43	19		T46	3		T24	7
values[6]	634	1			T141	1		T57	15		T206	6
values[7]	593	1			T38	9		T22	17		T122	10
values[8]	3122	1			T1	1		T2	26		T4	8
values[9]	977	1			T5	2		T6	13		T37	6
minimum	18050	1			T3	12		T5	112		T7	2

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	679	1			T37	23		T119	25		T23	11
values[1]	847	1			T7	11		T9	1		T35	23
values[2]	595	1			T5	1		T9	1		T35	26
values[3]	837	1			T43	19		T46	34		T141	1
values[4]	531	1			T46	3		T24	7		T206	6
values[5]	603	1			T141	1		T22	17		T57	15
values[6]	3023	1			T1	1		T4	8		T8	17
values[7]	791	1			T2	26		T5	2		T6	13
values[8]	840	1			T43	8		T22	13		T27	21
values[9]	172	1			T37	6		T118	1		T23	9
minimum	18225	1			T3	12		T5	112		T7	2

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22925

1

T1

1

T2

14

T3

12

auto[1]

4218

1

T2

12

T6

7

T8

15

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T119	13		T128	1		T215	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T37	15		T23	7		T14	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T143	4		T228	8		T151	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T7	1		T9	1		T35	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T5	1		T35	13		T139	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T9	1		T27	14		T162	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T141	1		T27	12		T192	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T43	4		T46	17		T206	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T46	3		T24	7		T206	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T123	1		T17	2		T225	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T141	1		T149	1		T224	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T22	17		T57	13		T149	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1694	1			T1	1		T4	1		T8	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T227	9		T94	1		T16	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T2	13		T5	1		T37	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T6	8		T46	13		T38	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T57	7		T121	1		T142	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T43	8		T22	13		T27	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T37	1		T118	1		T23	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T280	1		T268	1		T270	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17962	1			T3	12		T5	112		T9	140
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T57	2		T94	1		T124	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T119	12		T128	17		T215	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T37	8		T23	4		T14	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T143	7		T151	6		T281	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T7	10		T35	12		T119	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T35	13		T139	2		T31	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T27	2		T162	16		T41	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T27	14		T192	9		T123	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T43	15		T46	17		T206	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T206	5		T143	4		T62	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T123	1		T17	1		T135	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T224	6		T217	11		T295	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T57	2		T123	11		T18	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1015	1			T4	7		T127	25		T38	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T227	11		T16	4		T191	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T2	13		T5	1		T37	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T6	5		T46	10		T38	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T57	7		T142	5		T50	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T27	11		T58	5		T89	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T37	5		T23	4		T214	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T270	17		T300	10		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T7	2		T9	3		T38	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T57	2		T301	7		T302	11

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T118	1		T57	7		T121	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T27	10		T120	1		T58	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T166	1		T187	1		T290	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T119	13		T128	1		T206	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T35	11		T37	15		T23	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T215	1		T129	10		T143	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T7	1		T9	1		T119	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T35	13		T139	1		T40	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T148	1		T41	4		T214	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T5	1		T141	1		T27	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T9	1		T46	17		T27	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T46	3		T24	7		T88	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T43	4		T129	5		T229	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T141	1		T206	1		T149	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T57	13		T149	1		T184	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T38	5		T122	1		T224	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T22	17		T227	9		T94	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1727	1			T1	1		T2	13		T4	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T46	13		T12	3		T139	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T5	1		T37	1		T23	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	311	1			T6	8		T43	8		T38	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17910	1			T3	12		T5	112		T9	140
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T57	7		T214	9		T263	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T27	11		T58	5		T270	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T187	10		T290	2		T303	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T119	12		T128	17		T206	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T35	12		T37	8		T23	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T215	13		T129	11		T143	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T7	10		T119	12		T30	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T35	13		T139	2		T237	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T41	3		T214	10		T152	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T27	14		T192	9		T123	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T46	17		T27	2		T206	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T143	4		T62	1		T280	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T43	15		T135	13		T304	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T206	5		T217	11		T295	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T57	2		T123	12		T17	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T38	4		T122	9		T224	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T227	11		T16	4		T191	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	994	1			T2	13		T4	7		T37	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T46	10		T12	2		T139	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T5	1		T37	5		T23	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T6	5		T38	3		T89	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T7	2		T9	3		T38	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T119	13		T128	18		T215	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T37	9		T23	5		T14	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T143	8		T228	1		T151	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	317	1			T7	11		T9	1		T35	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T5	1		T35	14		T139	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T9	1		T27	3		T162	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T141	1		T27	15		T192	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T43	16		T46	18		T206	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T46	1		T24	1		T206	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T123	2		T17	2		T225	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T141	1		T149	1		T224	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T22	1		T57	3		T149	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1359	1			T1	1		T4	8		T8	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T227	12		T94	1		T16	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T2	14		T5	2		T37	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T6	6		T46	11		T38	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T57	8		T121	1		T142	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T43	1		T22	1		T27	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T37	6		T118	1		T23	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T280	1		T268	1		T270	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18126	1			T3	12		T5	112		T7	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T57	3		T94	1		T124	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T119	12		T129	9		T223	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T37	14		T23	6		T14	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T143	3		T228	7		T305	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T35	10		T119	17		T30	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T35	12		T40	1		T31	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T27	13		T41	1		T214	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T27	11		T192	11		T161	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T43	3		T46	16		T129	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T46	2		T24	6		T88	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T17	1		T225	15		T153	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T224	3		T163	16		T217	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T22	16		T57	12		T123	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1350	1			T8	15		T42	33		T44	39
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T227	8		T16	3		T191	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T2	12		T37	11		T23	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T6	7		T46	12		T95	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T57	6		T142	8		T277	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T43	7		T22	12		T27	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T23	4		T214	12		T275	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T270	15		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T306	15		T270	5		T307	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T57	1		T217	10		T301	6

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T118	1		T57	8		T121	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T27	12		T120	1		T58	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T166	1		T187	11		T290	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T119	13		T128	18		T206	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T35	13		T37	9		T23	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T215	14		T129	12		T143	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T7	11		T9	1		T119	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T35	14		T139	3		T40	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T148	1		T41	6		T214	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T5	1		T141	1		T27	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T9	1		T46	18		T27	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T46	1		T24	1		T88	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T43	16		T129	1		T229	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T141	1		T206	6		T149	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T57	3		T149	1		T184	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T38	5		T122	10		T224	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T22	1		T227	12		T94	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1335	1			T1	1		T2	14		T4	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T46	11		T12	5		T139	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T5	2		T37	6		T23	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T6	6		T43	1		T38	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18050	1			T3	12		T5	112		T7	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T57	6		T214	12		T263	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T27	9		T58	4		T270	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T303	15		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T119	12		T223	11		T136	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T35	10		T37	14		T23	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T129	9		T143	3		T228	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T119	17		T30	11		T95	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T35	12		T40	1		T237	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T41	1		T214	13		T152	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T27	11		T192	11		T161	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T46	16		T27	13		T225	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T46	2		T24	6		T88	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T43	3		T129	4		T225	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T163	16		T217	9		T295	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T57	12		T123	11		T17	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T38	4		T224	3		T243	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T22	16		T227	8		T16	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1386	1			T2	12		T8	15		T37	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T46	12		T95	9		T242	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T23	4		T142	8		T17	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T6	7		T43	7		T22	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22925

1

T1

1

T2

14

T3

12

auto[1]

auto[0]

4218

1

T2

12

T6

7

T8

15