Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27143

1

T1

1

T2

26

T3

12

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23766

1

T1

1

T3

12

T4

8

auto[ADC_CTRL_FILTER_COND_OUT]

3377

1

T2

26

T6

13

T35

49

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21092

1

T2

26

T3

12

T5

115

auto[1]

6051

1

T1

1

T4

8

T6

13

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23175

1

T1

1

T2

13

T3

12

auto[1]

3968

1

T2

13

T4

7

T5

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	344	1			T9	1		T35	49		T141	1
values[0]	64	1			T121	1		T129	5		T283	32
values[1]	827	1			T119	25		T23	20		T27	26
values[2]	3096	1			T1	1		T4	8		T8	17
values[3]	561	1			T5	2		T38	5		T120	1
values[4]	692	1			T6	13		T37	52		T215	14
values[5]	940	1			T7	11		T9	1		T37	6
values[6]	697	1			T5	1		T43	19		T119	31
values[7]	487	1			T46	3		T38	9		T162	13
values[8]	604	1			T2	26		T43	8		T46	23
values[9]	781	1			T118	1		T141	1		T22	13
minimum	18050	1			T3	12		T5	112		T7	2

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	806	1			T23	20		T27	26		T122	10
values[1]	3061	1			T1	1		T4	8		T8	17
values[2]	570	1			T5	2		T37	52		T38	5
values[3]	687	1			T6	13		T57	4		T215	14
values[4]	929	1			T7	11		T9	1		T37	6
values[5]	653	1			T5	1		T46	3		T119	25
values[6]	541	1			T43	8		T46	23		T38	9
values[7]	513	1			T2	26		T141	1		T12	5
values[8]	881	1			T9	1		T35	49		T118	1
values[9]	180	1			T120	1		T233	11		T261	26
minimum	18322	1			T3	12		T5	112		T7	2

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22925

1

T1

1

T2

14

T3

12

auto[1]

4218

1

T2

12

T6

7

T8

15

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T23	12		T27	12		T122	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T95	2		T31	11		T50	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1664	1			T1	1		T4	1		T8	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T46	17		T13	16		T162	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T5	1		T37	15		T38	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T37	12		T206	1		T94	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T57	2		T31	6		T249	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T6	8		T215	1		T58	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T7	1		T9	1		T37	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T43	4		T119	6		T22	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T5	1		T119	13		T161	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T46	3		T30	12		T184	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T43	8		T206	1		T162	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T46	13		T38	5		T40	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T141	1		T12	3		T14	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T2	13		T23	7		T57	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T9	1		T22	13		T24	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T35	24		T118	1		T141	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T233	11		T261	13		T308	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T120	1		T164	15		T309	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17989	1			T3	12		T5	112		T9	140
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T121	1		T129	5		T283	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T23	8		T27	14		T122	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T31	8		T50	14		T209	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	982	1			T4	7		T127	25		T27	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T46	17		T13	12		T162	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T5	1		T37	8		T38	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T37	17		T206	9		T152	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T57	2		T31	8		T294	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T6	5		T215	13		T244	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T7	10		T37	5		T41	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T43	15		T27	2		T128	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T119	12		T58	8		T16	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T30	13		T214	9		T151	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T206	5		T162	6		T139	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T46	10		T38	4		T123	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T12	2		T14	3		T58	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T2	13		T23	13		T57	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T57	2		T143	13		T209	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T35	25		T192	9		T206	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T261	13		T247	15		T286	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T309	18		T232	2		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T7	2		T9	3		T119	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T283	15		T310	4		T311	4

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T9	1		T221	3		T223	14
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T35	24		T141	1		T192	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T121	1		T129	5		T283	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T119	13		T23	12		T27	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T31	11		T50	1		T225	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1724	1			T1	1		T4	1		T8	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T46	17		T13	16		T162	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T5	1		T38	2		T120	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T206	1		T94	1		T185	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T37	15		T139	1		T124	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T6	8		T37	12		T215	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T7	1		T9	1		T37	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	313	1			T22	17		T128	1		T120	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T5	1		T119	13		T184	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T43	4		T119	6		T27	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T162	7		T161	13		T58	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T46	3		T38	5		T40	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T43	8		T12	3		T206	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T2	13		T46	13		T23	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T141	1		T22	13		T24	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T118	1		T120	1		T206	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17910	1			T3	12		T5	112		T9	140
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T221	1		T263	1		T247	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T35	25		T192	9		T269	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T283	15		T240	11		T284	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T119	12		T23	8		T27	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T31	8		T50	14		T209	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1015	1			T4	7		T127	25		T27	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T46	17		T13	12		T162	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T5	1		T38	3		T89	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T206	9		T18	1		T152	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T37	8		T139	2		T283	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T6	5		T37	17		T215	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T7	10		T37	5		T57	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T128	17		T227	11		T224	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T119	12		T16	4		T242	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T43	15		T27	2		T30	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T162	6		T58	8		T17	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T38	4		T123	1		T241	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T12	2		T206	5		T14	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T2	13		T46	10		T23	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T57	2		T143	13		T209	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T206	12		T88	1		T123	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T7	2		T9	3		T38	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T23	10		T27	15		T122	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T95	1		T31	9		T50	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1322	1			T1	1		T4	8		T8	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T46	18		T13	16		T162	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T5	2		T37	9		T38	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T37	18		T206	10		T94	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T57	3		T31	9		T249	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T6	6		T215	14		T58	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T7	11		T9	1		T37	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	320	1			T43	16		T119	1		T22	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T5	1		T119	13		T161	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T46	1		T30	14		T184	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T43	1		T206	6		T162	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T46	11		T38	5		T40	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T141	1		T12	5		T14	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T2	14		T23	14		T57	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T9	1		T22	1		T24	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T35	27		T118	1		T141	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T233	1		T261	14		T308	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T120	1		T164	1		T309	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18134	1			T3	12		T5	112		T7	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T121	1		T129	1		T283	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T23	10		T27	11		T142	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T95	1		T31	10		T225	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1324	1			T8	15		T42	33		T44	39
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T46	16		T13	12		T18	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T37	14		T143	3		T250	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T37	11		T152	3		T62	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T57	1		T31	5		T249	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T6	7		T58	2		T228	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T95	9		T41	1		T17	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T43	3		T119	5		T22	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T119	12		T161	12		T58	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T46	2		T30	11		T214	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T43	7		T162	6		T17	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T46	12		T38	4		T40	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T14	3		T58	4		T123	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T2	12		T23	6		T57	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T22	12		T24	6		T57	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T35	22		T192	11		T237	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T233	10		T261	12		T247	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T164	14		T309	9		T312	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T119	12		T214	13		T295	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T129	4		T283	16		T310	8

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T9	1		T221	3		T223	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T35	27		T141	1		T192	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T121	1		T129	1		T283	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T119	13		T23	10		T27	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T31	9		T50	15		T225	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1362	1			T1	1		T4	8		T8	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T46	18		T13	16		T162	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T5	2		T38	5		T120	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T206	10		T94	1		T185	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T37	9		T139	3		T124	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T6	6		T37	18		T215	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T7	11		T9	1		T37	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T22	1		T128	18		T120	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T5	1		T119	13		T184	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T43	16		T119	1		T27	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T162	7		T161	1		T58	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T46	1		T38	5		T40	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T43	1		T12	5		T206	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T2	14		T46	11		T23	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T141	1		T22	1		T24	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T118	1		T120	1		T206	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18050	1			T3	12		T5	112		T7	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T221	1		T223	13		T263	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T35	22		T192	11		T182	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T129	4		T283	16		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T119	12		T23	10		T27	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T31	10		T225	15		T133	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1377	1			T8	15		T42	33		T44	39
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T46	16		T13	12		T95	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T143	3		T250	8		T236	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T18	1		T152	3		T213	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T37	14		T124	7		T230	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T6	7		T37	11		T228	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T57	1		T41	1		T31	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T22	16		T227	8		T58	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T119	12		T95	9		T16	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T43	3		T119	5		T27	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T162	6		T161	12		T58	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T46	2		T38	4		T40	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T43	7		T14	3		T58	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T2	12		T46	12		T23	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T22	12		T24	6		T57	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T237	11		T277	2		T236	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22925

1

T1

1

T2

14

T3

12

auto[1]

auto[0]

4218

1

T2

12

T6

7

T8

15