Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.69 99.07 96.67 100.00 100.00 98.83 98.33 90.94


Total test records in report: 920
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
T798 /workspace/coverage/default/25.adc_ctrl_filters_both.2393090327 Jul 18 06:33:36 PM PDT 24 Jul 18 06:35:28 PM PDT 24 166650817260 ps
T180 /workspace/coverage/default/44.adc_ctrl_filters_wakeup.2909840887 Jul 18 06:37:32 PM PDT 24 Jul 18 06:39:41 PM PDT 24 538441158235 ps
T799 /workspace/coverage/default/45.adc_ctrl_lowpower_counter.435283393 Jul 18 06:37:48 PM PDT 24 Jul 18 06:38:03 PM PDT 24 21214736513 ps
T800 /workspace/coverage/default/39.adc_ctrl_alert_test.2793274906 Jul 18 06:36:50 PM PDT 24 Jul 18 06:36:53 PM PDT 24 415059347 ps
T333 /workspace/coverage/default/16.adc_ctrl_filters_both.287336064 Jul 18 06:32:27 PM PDT 24 Jul 18 06:39:32 PM PDT 24 181159676781 ps
T801 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.4078992659 Jul 18 05:58:24 PM PDT 24 Jul 18 05:58:33 PM PDT 24 498201028 ps
T111 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.386933315 Jul 18 05:58:17 PM PDT 24 Jul 18 05:58:24 PM PDT 24 427801625 ps
T97 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.3708135573 Jul 18 05:58:28 PM PDT 24 Jul 18 05:58:39 PM PDT 24 361781621 ps
T63 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.1905211636 Jul 18 05:58:37 PM PDT 24 Jul 18 05:58:47 PM PDT 24 526826007 ps
T802 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.2410532456 Jul 18 05:58:36 PM PDT 24 Jul 18 05:58:45 PM PDT 24 622524774 ps
T803 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.3631885163 Jul 18 05:58:38 PM PDT 24 Jul 18 05:58:46 PM PDT 24 357692716 ps
T98 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.4198126798 Jul 18 05:58:16 PM PDT 24 Jul 18 05:58:24 PM PDT 24 1545365893 ps
T804 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.2688104306 Jul 18 05:58:22 PM PDT 24 Jul 18 05:58:30 PM PDT 24 435269498 ps
T805 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.1485270318 Jul 18 05:58:27 PM PDT 24 Jul 18 05:58:37 PM PDT 24 538162320 ps
T55 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.2076285147 Jul 18 05:58:34 PM PDT 24 Jul 18 05:58:45 PM PDT 24 474177550 ps
T99 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.319954119 Jul 18 05:58:24 PM PDT 24 Jul 18 05:58:33 PM PDT 24 1252209470 ps
T806 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.3311194634 Jul 18 05:58:38 PM PDT 24 Jul 18 05:58:47 PM PDT 24 367686490 ps
T64 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.1940561905 Jul 18 05:58:14 PM PDT 24 Jul 18 05:58:22 PM PDT 24 603428881 ps
T807 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.1820845138 Jul 18 05:58:30 PM PDT 24 Jul 18 05:58:40 PM PDT 24 383373363 ps
T96 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.1692796150 Jul 18 05:58:40 PM PDT 24 Jul 18 05:58:47 PM PDT 24 608947400 ps
T808 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.587902889 Jul 18 05:58:34 PM PDT 24 Jul 18 05:58:45 PM PDT 24 491439480 ps
T809 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.3422407377 Jul 18 05:58:26 PM PDT 24 Jul 18 05:58:36 PM PDT 24 582621350 ps
T810 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.1274960297 Jul 18 05:58:38 PM PDT 24 Jul 18 05:58:47 PM PDT 24 329355650 ps
T84 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.1617715663 Jul 18 05:58:39 PM PDT 24 Jul 18 05:58:46 PM PDT 24 520549378 ps
T59 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.1051549008 Jul 18 05:58:25 PM PDT 24 Jul 18 05:58:51 PM PDT 24 8004829090 ps
T811 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.2715614579 Jul 18 05:58:27 PM PDT 24 Jul 18 05:58:36 PM PDT 24 480803062 ps
T60 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.656067894 Jul 18 05:58:34 PM PDT 24 Jul 18 05:58:47 PM PDT 24 4391305562 ps
T61 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.2059347552 Jul 18 05:58:24 PM PDT 24 Jul 18 05:58:38 PM PDT 24 8143956909 ps
T100 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.3311357578 Jul 18 05:58:13 PM PDT 24 Jul 18 05:58:22 PM PDT 24 321811559 ps
T812 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.941003704 Jul 18 05:58:34 PM PDT 24 Jul 18 05:58:44 PM PDT 24 358168548 ps
T813 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.1049435882 Jul 18 05:58:38 PM PDT 24 Jul 18 05:58:46 PM PDT 24 537755061 ps
T56 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.1254125126 Jul 18 05:58:13 PM PDT 24 Jul 18 05:58:21 PM PDT 24 325947482 ps
T112 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.4031939615 Jul 18 05:58:28 PM PDT 24 Jul 18 05:58:39 PM PDT 24 334575783 ps
T81 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.1900479412 Jul 18 05:58:16 PM PDT 24 Jul 18 05:58:23 PM PDT 24 562469662 ps
T113 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.375606729 Jul 18 05:58:24 PM PDT 24 Jul 18 05:58:34 PM PDT 24 439540867 ps
T52 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.495569669 Jul 18 05:58:29 PM PDT 24 Jul 18 05:58:53 PM PDT 24 5223337086 ps
T814 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.1575869955 Jul 18 05:58:31 PM PDT 24 Jul 18 05:58:40 PM PDT 24 353660522 ps
T83 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.2737572525 Jul 18 05:58:25 PM PDT 24 Jul 18 05:58:35 PM PDT 24 620159393 ps
T53 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.399926346 Jul 18 05:58:22 PM PDT 24 Jul 18 05:58:34 PM PDT 24 4139553459 ps
T68 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.3753284911 Jul 18 05:58:27 PM PDT 24 Jul 18 05:58:40 PM PDT 24 4321481024 ps
T815 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.3649734917 Jul 18 05:59:33 PM PDT 24 Jul 18 05:59:48 PM PDT 24 431349191 ps
T816 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.2632294852 Jul 18 05:58:25 PM PDT 24 Jul 18 05:58:33 PM PDT 24 386891788 ps
T817 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.854803170 Jul 18 05:58:23 PM PDT 24 Jul 18 05:58:32 PM PDT 24 1305047906 ps
T69 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.1045150783 Jul 18 05:58:35 PM PDT 24 Jul 18 05:58:47 PM PDT 24 390567528 ps
T114 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.2071908236 Jul 18 05:58:24 PM PDT 24 Jul 18 05:58:34 PM PDT 24 2035855090 ps
T818 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.1160402594 Jul 18 05:58:38 PM PDT 24 Jul 18 05:58:47 PM PDT 24 524131724 ps
T54 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.2533469190 Jul 18 05:58:17 PM PDT 24 Jul 18 05:58:59 PM PDT 24 16298581715 ps
T819 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.488195706 Jul 18 05:58:27 PM PDT 24 Jul 18 05:58:38 PM PDT 24 474895216 ps
T70 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.948950981 Jul 18 05:58:22 PM PDT 24 Jul 18 05:58:31 PM PDT 24 514579598 ps
T820 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.1539633290 Jul 18 05:58:34 PM PDT 24 Jul 18 05:58:44 PM PDT 24 302669358 ps
T73 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.951247742 Jul 18 05:58:26 PM PDT 24 Jul 18 05:58:36 PM PDT 24 644972486 ps
T79 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.440239779 Jul 18 05:58:29 PM PDT 24 Jul 18 05:58:59 PM PDT 24 8153821591 ps
T821 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.2297121609 Jul 18 05:58:36 PM PDT 24 Jul 18 05:58:45 PM PDT 24 443074237 ps
T82 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.3988042966 Jul 18 05:58:38 PM PDT 24 Jul 18 05:59:06 PM PDT 24 8567084125 ps
T822 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.283783851 Jul 18 05:58:33 PM PDT 24 Jul 18 05:58:43 PM PDT 24 530978549 ps
T823 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.156101317 Jul 18 05:58:28 PM PDT 24 Jul 18 05:58:41 PM PDT 24 2047737824 ps
T74 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.2780473745 Jul 18 05:58:27 PM PDT 24 Jul 18 05:58:59 PM PDT 24 8988477192 ps
T71 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.1912588814 Jul 18 05:58:21 PM PDT 24 Jul 18 05:58:29 PM PDT 24 315253706 ps
T824 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.1238049533 Jul 18 05:58:26 PM PDT 24 Jul 18 05:58:39 PM PDT 24 866340783 ps
T825 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.1941870833 Jul 18 05:58:37 PM PDT 24 Jul 18 05:58:45 PM PDT 24 495647642 ps
T826 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.4022194409 Jul 18 05:58:16 PM PDT 24 Jul 18 05:58:26 PM PDT 24 4460432061 ps
T827 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.2178130736 Jul 18 05:58:19 PM PDT 24 Jul 18 05:58:26 PM PDT 24 316116956 ps
T828 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.566695916 Jul 18 05:58:26 PM PDT 24 Jul 18 05:58:36 PM PDT 24 490941604 ps
T72 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.591700900 Jul 18 05:58:33 PM PDT 24 Jul 18 05:58:54 PM PDT 24 8874642128 ps
T829 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.887600200 Jul 18 05:58:34 PM PDT 24 Jul 18 05:58:45 PM PDT 24 434044325 ps
T830 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.2515051151 Jul 18 05:58:17 PM PDT 24 Jul 18 05:58:34 PM PDT 24 4277046318 ps
T831 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.2841880039 Jul 18 05:58:13 PM PDT 24 Jul 18 05:58:23 PM PDT 24 1996928328 ps
T832 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.2429151614 Jul 18 05:58:28 PM PDT 24 Jul 18 05:58:37 PM PDT 24 461560603 ps
T833 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.2747654173 Jul 18 05:58:21 PM PDT 24 Jul 18 05:58:28 PM PDT 24 748588376 ps
T834 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.1864133494 Jul 18 05:58:36 PM PDT 24 Jul 18 05:58:45 PM PDT 24 292012626 ps
T835 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.3715960879 Jul 18 05:58:38 PM PDT 24 Jul 18 05:58:47 PM PDT 24 329875199 ps
T836 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.1418648808 Jul 18 05:58:27 PM PDT 24 Jul 18 05:58:40 PM PDT 24 4369965846 ps
T80 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.3196551933 Jul 18 05:58:23 PM PDT 24 Jul 18 05:58:32 PM PDT 24 411492768 ps
T101 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.141083561 Jul 18 05:58:33 PM PDT 24 Jul 18 05:58:42 PM PDT 24 562367981 ps
T78 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.2584890011 Jul 18 05:58:28 PM PDT 24 Jul 18 05:58:40 PM PDT 24 555524941 ps
T837 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.528923607 Jul 18 05:58:30 PM PDT 24 Jul 18 05:58:41 PM PDT 24 505434805 ps
T102 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.1575331086 Jul 18 05:58:17 PM PDT 24 Jul 18 05:58:24 PM PDT 24 481985854 ps
T346 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.1650838743 Jul 18 05:58:36 PM PDT 24 Jul 18 05:58:51 PM PDT 24 8456528371 ps
T838 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.3457113435 Jul 18 05:58:30 PM PDT 24 Jul 18 05:58:40 PM PDT 24 446861428 ps
T104 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.3863093064 Jul 18 05:58:27 PM PDT 24 Jul 18 05:58:38 PM PDT 24 509007449 ps
T839 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.1873891428 Jul 18 05:58:21 PM PDT 24 Jul 18 05:58:29 PM PDT 24 1841918060 ps
T840 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.1374281441 Jul 18 05:58:23 PM PDT 24 Jul 18 05:58:31 PM PDT 24 494070336 ps
T103 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.484522144 Jul 18 05:58:21 PM PDT 24 Jul 18 05:58:28 PM PDT 24 443743216 ps
T105 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.1974424255 Jul 18 05:58:31 PM PDT 24 Jul 18 05:58:41 PM PDT 24 544114572 ps
T841 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.2033468620 Jul 18 05:58:32 PM PDT 24 Jul 18 05:58:41 PM PDT 24 404548731 ps
T842 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.3495612858 Jul 18 05:58:33 PM PDT 24 Jul 18 05:59:02 PM PDT 24 7856998501 ps
T843 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.2463849103 Jul 18 05:58:34 PM PDT 24 Jul 18 05:58:45 PM PDT 24 382891492 ps
T106 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.376760189 Jul 18 05:58:14 PM PDT 24 Jul 18 05:59:57 PM PDT 24 23500647003 ps
T844 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.3133996531 Jul 18 05:58:15 PM PDT 24 Jul 18 05:58:23 PM PDT 24 528746739 ps
T845 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.564531412 Jul 18 05:58:24 PM PDT 24 Jul 18 05:58:33 PM PDT 24 665767327 ps
T107 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.1763062448 Jul 18 05:58:24 PM PDT 24 Jul 18 05:58:33 PM PDT 24 460821451 ps
T846 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.4131806020 Jul 18 05:58:19 PM PDT 24 Jul 18 05:58:26 PM PDT 24 541317552 ps
T847 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.76290289 Jul 18 05:58:35 PM PDT 24 Jul 18 05:58:44 PM PDT 24 373715724 ps
T848 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.2465352313 Jul 18 05:58:35 PM PDT 24 Jul 18 05:58:46 PM PDT 24 452684996 ps
T849 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.929625422 Jul 18 05:58:34 PM PDT 24 Jul 18 05:58:44 PM PDT 24 362718182 ps
T850 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.3931204891 Jul 18 05:58:25 PM PDT 24 Jul 18 05:58:39 PM PDT 24 2667817977 ps
T851 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.1570052908 Jul 18 05:58:31 PM PDT 24 Jul 18 05:58:42 PM PDT 24 535063987 ps
T852 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.997602900 Jul 18 05:58:30 PM PDT 24 Jul 18 05:58:40 PM PDT 24 448339903 ps
T853 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.1210872409 Jul 18 05:58:20 PM PDT 24 Jul 18 05:58:30 PM PDT 24 8458650659 ps
T854 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.1248157967 Jul 18 05:58:27 PM PDT 24 Jul 18 05:58:38 PM PDT 24 1019655557 ps
T855 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.1926848443 Jul 18 05:58:40 PM PDT 24 Jul 18 05:58:57 PM PDT 24 4486405591 ps
T856 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.3751928107 Jul 18 05:58:22 PM PDT 24 Jul 18 05:58:29 PM PDT 24 616970990 ps
T857 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.2939242837 Jul 18 05:58:31 PM PDT 24 Jul 18 05:58:41 PM PDT 24 351775803 ps
T858 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.480674343 Jul 18 05:58:28 PM PDT 24 Jul 18 05:58:40 PM PDT 24 384137598 ps
T859 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.3346722527 Jul 18 05:58:28 PM PDT 24 Jul 18 05:58:40 PM PDT 24 437623866 ps
T860 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.823900738 Jul 18 05:58:35 PM PDT 24 Jul 18 05:58:45 PM PDT 24 414777943 ps
T861 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.3019529950 Jul 18 05:58:23 PM PDT 24 Jul 18 05:58:32 PM PDT 24 454707883 ps
T862 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.3272695143 Jul 18 05:58:27 PM PDT 24 Jul 18 05:58:37 PM PDT 24 366563469 ps
T863 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.139453138 Jul 18 05:58:38 PM PDT 24 Jul 18 05:58:47 PM PDT 24 414541928 ps
T864 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.3812015239 Jul 18 05:58:18 PM PDT 24 Jul 18 05:58:24 PM PDT 24 2418192866 ps
T108 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.2731841537 Jul 18 05:58:15 PM PDT 24 Jul 18 05:58:24 PM PDT 24 1021124640 ps
T865 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.1442649408 Jul 18 05:58:29 PM PDT 24 Jul 18 05:58:39 PM PDT 24 307157396 ps
T866 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.2468029166 Jul 18 05:58:23 PM PDT 24 Jul 18 05:59:51 PM PDT 24 25980885999 ps
T867 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.3965383001 Jul 18 05:58:22 PM PDT 24 Jul 18 05:58:29 PM PDT 24 471566433 ps
T868 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.816116194 Jul 18 05:58:26 PM PDT 24 Jul 18 05:58:36 PM PDT 24 590566161 ps
T869 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.1352356992 Jul 18 05:58:21 PM PDT 24 Jul 18 05:58:34 PM PDT 24 7939807913 ps
T870 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.2873343682 Jul 18 05:58:22 PM PDT 24 Jul 18 05:58:29 PM PDT 24 466068331 ps
T871 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.1396682907 Jul 18 05:58:27 PM PDT 24 Jul 18 05:58:49 PM PDT 24 4918915344 ps
T109 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.2964090949 Jul 18 05:58:18 PM PDT 24 Jul 18 05:58:25 PM PDT 24 410369091 ps
T872 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.274042103 Jul 18 05:58:34 PM PDT 24 Jul 18 05:58:44 PM PDT 24 444415172 ps
T873 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.1736532176 Jul 18 05:58:17 PM PDT 24 Jul 18 05:58:23 PM PDT 24 380356950 ps
T874 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.3966356919 Jul 18 05:58:24 PM PDT 24 Jul 18 05:58:36 PM PDT 24 4419113526 ps
T875 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.1022173913 Jul 18 05:58:27 PM PDT 24 Jul 18 05:58:36 PM PDT 24 565722295 ps
T876 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.1881874845 Jul 18 05:58:25 PM PDT 24 Jul 18 05:58:35 PM PDT 24 2332542145 ps
T877 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.4046037552 Jul 18 05:58:23 PM PDT 24 Jul 18 05:58:33 PM PDT 24 404340962 ps
T878 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.1890338600 Jul 18 05:58:40 PM PDT 24 Jul 18 05:58:51 PM PDT 24 4181857940 ps
T879 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.1270573791 Jul 18 05:58:39 PM PDT 24 Jul 18 05:58:47 PM PDT 24 416901801 ps
T880 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.3216837828 Jul 18 06:00:03 PM PDT 24 Jul 18 06:00:11 PM PDT 24 601996036 ps
T881 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.1480134083 Jul 18 05:58:23 PM PDT 24 Jul 18 05:58:32 PM PDT 24 707415129 ps
T882 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.892217429 Jul 18 05:58:15 PM PDT 24 Jul 18 05:58:22 PM PDT 24 451921384 ps
T85 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.1902989047 Jul 18 05:58:23 PM PDT 24 Jul 18 05:58:49 PM PDT 24 8084133940 ps
T883 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.4029820079 Jul 18 05:58:13 PM PDT 24 Jul 18 05:58:22 PM PDT 24 520960639 ps
T884 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.2958725408 Jul 18 05:58:22 PM PDT 24 Jul 18 05:58:29 PM PDT 24 352201910 ps
T885 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.1023633237 Jul 18 05:58:23 PM PDT 24 Jul 18 05:58:37 PM PDT 24 1317064776 ps
T886 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.4041825266 Jul 18 05:58:31 PM PDT 24 Jul 18 05:58:41 PM PDT 24 319658005 ps
T887 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.3062246966 Jul 18 05:58:15 PM PDT 24 Jul 18 05:58:39 PM PDT 24 13766006064 ps
T888 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.2844678502 Jul 18 05:58:19 PM PDT 24 Jul 18 05:58:26 PM PDT 24 658968802 ps
T889 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.2102654645 Jul 18 05:58:27 PM PDT 24 Jul 18 05:58:48 PM PDT 24 4481450226 ps
T890 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.545528775 Jul 18 05:58:18 PM PDT 24 Jul 18 05:58:26 PM PDT 24 318823245 ps
T891 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.1622599057 Jul 18 05:58:35 PM PDT 24 Jul 18 05:58:44 PM PDT 24 510252056 ps
T892 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.2215894687 Jul 18 05:58:22 PM PDT 24 Jul 18 05:58:30 PM PDT 24 529877327 ps
T893 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.3592764422 Jul 18 05:58:33 PM PDT 24 Jul 18 05:58:46 PM PDT 24 2178263038 ps
T894 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.4264798754 Jul 18 05:58:17 PM PDT 24 Jul 18 05:58:24 PM PDT 24 1200116648 ps
T895 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.2127625334 Jul 18 05:58:13 PM PDT 24 Jul 18 05:58:22 PM PDT 24 339227266 ps
T110 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.2615046579 Jul 18 05:58:23 PM PDT 24 Jul 18 05:58:32 PM PDT 24 498135383 ps
T896 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.1924346797 Jul 18 05:58:15 PM PDT 24 Jul 18 05:58:22 PM PDT 24 557882755 ps
T897 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.2666248798 Jul 18 05:58:13 PM PDT 24 Jul 18 05:58:22 PM PDT 24 644134000 ps
T898 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.2029539402 Jul 18 05:58:28 PM PDT 24 Jul 18 05:58:47 PM PDT 24 3603195472 ps
T899 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.1060595961 Jul 18 05:58:18 PM PDT 24 Jul 18 05:58:25 PM PDT 24 5429869446 ps
T900 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.279131905 Jul 18 05:58:18 PM PDT 24 Jul 18 05:58:25 PM PDT 24 727195884 ps
T901 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.1607463905 Jul 18 05:58:26 PM PDT 24 Jul 18 05:59:23 PM PDT 24 23837669806 ps
T902 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.2017731498 Jul 18 05:58:38 PM PDT 24 Jul 18 05:58:48 PM PDT 24 3937637997 ps
T903 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.1048825639 Jul 18 05:58:18 PM PDT 24 Jul 18 05:58:35 PM PDT 24 4721868773 ps
T904 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.1345058442 Jul 18 05:58:15 PM PDT 24 Jul 18 05:58:22 PM PDT 24 537662414 ps
T905 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.3815594613 Jul 18 05:58:24 PM PDT 24 Jul 18 05:58:32 PM PDT 24 642940808 ps
T906 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.3924346130 Jul 18 05:58:31 PM PDT 24 Jul 18 05:58:41 PM PDT 24 495751899 ps
T907 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.4186474608 Jul 18 05:58:26 PM PDT 24 Jul 18 05:58:37 PM PDT 24 496536232 ps
T908 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.377809176 Jul 18 05:58:31 PM PDT 24 Jul 18 05:58:49 PM PDT 24 4351291792 ps
T909 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.4069192762 Jul 18 05:58:34 PM PDT 24 Jul 18 05:58:46 PM PDT 24 902839406 ps
T910 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.4171996951 Jul 18 05:58:22 PM PDT 24 Jul 18 05:58:36 PM PDT 24 3998282986 ps
T911 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.2902231025 Jul 18 05:58:26 PM PDT 24 Jul 18 05:58:38 PM PDT 24 4150005696 ps
T912 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.3165212948 Jul 18 05:58:31 PM PDT 24 Jul 18 05:58:41 PM PDT 24 439420931 ps
T913 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.2793543190 Jul 18 05:58:24 PM PDT 24 Jul 18 05:58:43 PM PDT 24 3806907172 ps
T914 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.661316781 Jul 18 06:00:28 PM PDT 24 Jul 18 06:00:36 PM PDT 24 527306525 ps
T915 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.874249820 Jul 18 05:58:17 PM PDT 24 Jul 18 05:58:23 PM PDT 24 763765888 ps
T916 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.2858487945 Jul 18 05:58:34 PM PDT 24 Jul 18 05:58:44 PM PDT 24 343819797 ps
T917 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.2010764574 Jul 18 05:58:36 PM PDT 24 Jul 18 05:58:46 PM PDT 24 438395530 ps
T918 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.4122597072 Jul 18 05:58:27 PM PDT 24 Jul 18 05:58:57 PM PDT 24 8185977593 ps
T919 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.801228043 Jul 18 05:58:22 PM PDT 24 Jul 18 05:58:34 PM PDT 24 4140981312 ps
T920 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.1564135845 Jul 18 05:58:22 PM PDT 24 Jul 18 05:58:29 PM PDT 24 529551979 ps

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.1924140949
Short name T9
Test name
Test status
Simulation time 417868045907 ps
CPU time 1251.87 seconds
Started Jul 18 06:32:31 PM PDT 24
Finished Jul 18 06:53:25 PM PDT 24
Peak memory 202120 kb
Host smart-159c25ef-6a26-4a4f-a885-1636c3ce93c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924140949 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all
.1924140949
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.111185746
Short name T46
Test name
Test status
Simulation time 531644845089 ps
CPU time 342.66 seconds
Started Jul 18 06:36:51 PM PDT 24
Finished Jul 18 06:42:35 PM PDT 24
Peak memory 201908 kb
Host smart-0d52fdbf-36dc-4c54-850f-636b95b62bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111185746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.111185746
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.2920321782
Short name T5
Test name
Test status
Simulation time 251848338351 ps
CPU time 233.89 seconds
Started Jul 18 06:32:03 PM PDT 24
Finished Jul 18 06:35:59 PM PDT 24
Peak memory 210684 kb
Host smart-f0f2f6cf-dbee-4b99-9d93-73b0ef0b1b94
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920321782 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.2920321782
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.4176819937
Short name T17
Test name
Test status
Simulation time 91552604355 ps
CPU time 50.5 seconds
Started Jul 18 06:36:35 PM PDT 24
Finished Jul 18 06:37:27 PM PDT 24
Peak memory 210064 kb
Host smart-265a6fa7-4700-4836-bd75-197cadc0b53c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176819937 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.4176819937
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.807958954
Short name T37
Test name
Test status
Simulation time 539085466608 ps
CPU time 369.35 seconds
Started Jul 18 06:33:40 PM PDT 24
Finished Jul 18 06:39:50 PM PDT 24
Peak memory 201700 kb
Host smart-a3840546-6bed-4a21-8d4c-9417c5bbb464
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807958954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all.
807958954
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.789595462
Short name T143
Test name
Test status
Simulation time 510546745563 ps
CPU time 295.97 seconds
Started Jul 18 06:32:26 PM PDT 24
Finished Jul 18 06:37:24 PM PDT 24
Peak memory 201740 kb
Host smart-e55a2e41-5414-4f47-93b0-abdbd8a71196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789595462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.789595462
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.715114435
Short name T27
Test name
Test status
Simulation time 494913775277 ps
CPU time 616.63 seconds
Started Jul 18 06:31:47 PM PDT 24
Finished Jul 18 06:42:08 PM PDT 24
Peak memory 201820 kb
Host smart-afcdee32-56c2-41c3-8f55-a223e2842b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715114435 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.715114435
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.510601444
Short name T50
Test name
Test status
Simulation time 650372893675 ps
CPU time 739.47 seconds
Started Jul 18 06:33:25 PM PDT 24
Finished Jul 18 06:45:47 PM PDT 24
Peak memory 210300 kb
Host smart-7cff8fd4-c193-471f-af45-5e957501d9bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510601444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all.
510601444
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.112604419
Short name T58
Test name
Test status
Simulation time 521206685729 ps
CPU time 235.32 seconds
Started Jul 18 06:33:38 PM PDT 24
Finished Jul 18 06:37:35 PM PDT 24
Peak memory 201700 kb
Host smart-af8368f8-03d5-4129-83dd-59fc566e9ed7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112604419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gati
ng.112604419
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.979122404
Short name T35
Test name
Test status
Simulation time 357923431209 ps
CPU time 430.41 seconds
Started Jul 18 06:32:39 PM PDT 24
Finished Jul 18 06:39:52 PM PDT 24
Peak memory 201728 kb
Host smart-4f41d78f-b220-4dfd-a2e4-c27b40a9c95f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979122404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.979122404
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.3309574289
Short name T57
Test name
Test status
Simulation time 513880071285 ps
CPU time 938.62 seconds
Started Jul 18 06:38:00 PM PDT 24
Finished Jul 18 06:53:40 PM PDT 24
Peak memory 201756 kb
Host smart-0a926e6f-7431-4988-a4b7-6588c6d680ab
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309574289 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gat
ing.3309574289
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.1045150783
Short name T69
Test name
Test status
Simulation time 390567528 ps
CPU time 3.15 seconds
Started Jul 18 05:58:35 PM PDT 24
Finished Jul 18 05:58:47 PM PDT 24
Peak memory 217748 kb
Host smart-97e414a9-7f68-4fa1-83a9-d47c0465b54f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045150783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.1045150783
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.2110183468
Short name T65
Test name
Test status
Simulation time 8600304125 ps
CPU time 21.89 seconds
Started Jul 18 06:31:43 PM PDT 24
Finished Jul 18 06:32:09 PM PDT 24
Peak memory 218308 kb
Host smart-42c31396-34bc-4b61-8d7b-b5626a901724
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110183468 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.2110183468
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.1342198989
Short name T214
Test name
Test status
Simulation time 335097117957 ps
CPU time 198.93 seconds
Started Jul 18 06:32:36 PM PDT 24
Finished Jul 18 06:35:58 PM PDT 24
Peak memory 201780 kb
Host smart-bf83ec93-1e62-40b8-a334-622d1664af4e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342198989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gat
ing.1342198989
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.3999747598
Short name T213
Test name
Test status
Simulation time 496235100005 ps
CPU time 1173.78 seconds
Started Jul 18 06:32:28 PM PDT 24
Finished Jul 18 06:52:05 PM PDT 24
Peak memory 201732 kb
Host smart-28dbff79-ad93-448f-8262-2fa7a4c9b173
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999747598 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all
.3999747598
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.303077239
Short name T8
Test name
Test status
Simulation time 390785166589 ps
CPU time 176.88 seconds
Started Jul 18 06:35:31 PM PDT 24
Finished Jul 18 06:38:30 PM PDT 24
Peak memory 201804 kb
Host smart-d4e2d992-598e-4469-892e-0e4a85a6ae66
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303077239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
adc_ctrl_filters_wakeup_fixed.303077239
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.2793525959
Short name T119
Test name
Test status
Simulation time 521611280178 ps
CPU time 299.05 seconds
Started Jul 18 06:32:09 PM PDT 24
Finished Jul 18 06:37:13 PM PDT 24
Peak memory 201820 kb
Host smart-2e670d56-c8bb-4b5e-a3ee-bc1c3c4a10ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793525959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.2793525959
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.2076285147
Short name T55
Test name
Test status
Simulation time 474177550 ps
CPU time 1.82 seconds
Started Jul 18 05:58:34 PM PDT 24
Finished Jul 18 05:58:45 PM PDT 24
Peak memory 201372 kb
Host smart-c07c3452-29c4-425f-ab1c-a425e1bab5c0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076285147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.2076285147
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.3211110433
Short name T225
Test name
Test status
Simulation time 567390853977 ps
CPU time 390.28 seconds
Started Jul 18 06:37:04 PM PDT 24
Finished Jul 18 06:43:35 PM PDT 24
Peak memory 201820 kb
Host smart-4ce49e9f-e00b-424e-97ba-f3ccbeb7d70b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211110433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters
_wakeup.3211110433
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.1339385897
Short name T244
Test name
Test status
Simulation time 487276232127 ps
CPU time 981.58 seconds
Started Jul 18 06:32:28 PM PDT 24
Finished Jul 18 06:48:52 PM PDT 24
Peak memory 201716 kb
Host smart-114ed592-2864-4923-9c88-e433469df793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339385897 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.1339385897
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.130064569
Short name T222
Test name
Test status
Simulation time 505107554732 ps
CPU time 277.55 seconds
Started Jul 18 06:32:32 PM PDT 24
Finished Jul 18 06:37:12 PM PDT 24
Peak memory 201748 kb
Host smart-ba8dda4f-1e92-453b-bc35-4408924094de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130064569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.130064569
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.2478254234
Short name T236
Test name
Test status
Simulation time 507669540644 ps
CPU time 1205.8 seconds
Started Jul 18 06:34:04 PM PDT 24
Finished Jul 18 06:54:11 PM PDT 24
Peak memory 201748 kb
Host smart-6006a014-3803-47b8-8219-67be14225218
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478254234 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gat
ing.2478254234
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.1367166268
Short name T129
Test name
Test status
Simulation time 344221153813 ps
CPU time 188.43 seconds
Started Jul 18 06:33:23 PM PDT 24
Finished Jul 18 06:36:33 PM PDT 24
Peak memory 201812 kb
Host smart-ea47dc05-d71f-49a0-9fef-862b40250b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367166268 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.1367166268
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.2059347552
Short name T61
Test name
Test status
Simulation time 8143956909 ps
CPU time 7.09 seconds
Started Jul 18 05:58:24 PM PDT 24
Finished Jul 18 05:58:38 PM PDT 24
Peak memory 201772 kb
Host smart-d915959a-5620-4eb4-9ad8-9fc20c91308b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059347552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_in
tg_err.2059347552
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.2099387404
Short name T16
Test name
Test status
Simulation time 198546131853 ps
CPU time 82.61 seconds
Started Jul 18 06:31:46 PM PDT 24
Finished Jul 18 06:33:13 PM PDT 24
Peak memory 210100 kb
Host smart-512add27-7e9a-48bc-b0c9-52fb52627139
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099387404 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.2099387404
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.266627634
Short name T217
Test name
Test status
Simulation time 548220702578 ps
CPU time 326.43 seconds
Started Jul 18 06:32:23 PM PDT 24
Finished Jul 18 06:37:51 PM PDT 24
Peak memory 201816 kb
Host smart-3573422f-05f4-40c9-9410-fa41ea39c4a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266627634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.266627634
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.3701352653
Short name T243
Test name
Test status
Simulation time 374583982291 ps
CPU time 85.94 seconds
Started Jul 18 06:36:01 PM PDT 24
Finished Jul 18 06:37:29 PM PDT 24
Peak memory 201752 kb
Host smart-d227aa7b-2b78-4768-a892-333f3a711502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701352653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.3701352653
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.2302841967
Short name T120
Test name
Test status
Simulation time 479037121015 ps
CPU time 1093.18 seconds
Started Jul 18 06:35:02 PM PDT 24
Finished Jul 18 06:53:17 PM PDT 24
Peak memory 201648 kb
Host smart-89297d3f-162c-4684-a057-037445bc4bfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302841967 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.2302841967
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.4232530395
Short name T169
Test name
Test status
Simulation time 353256020 ps
CPU time 0.83 seconds
Started Jul 18 06:32:03 PM PDT 24
Finished Jul 18 06:32:07 PM PDT 24
Peak memory 201748 kb
Host smart-2a1a04d2-9273-44b1-b6f9-8eff9b997172
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232530395 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.4232530395
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.1026149627
Short name T248
Test name
Test status
Simulation time 495304485029 ps
CPU time 1097.62 seconds
Started Jul 18 06:33:25 PM PDT 24
Finished Jul 18 06:51:45 PM PDT 24
Peak memory 201812 kb
Host smart-b39725af-e72d-461e-a182-acde0290f437
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026149627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gat
ing.1026149627
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.168514544
Short name T204
Test name
Test status
Simulation time 438958556501 ps
CPU time 424.93 seconds
Started Jul 18 06:32:03 PM PDT 24
Finished Jul 18 06:39:11 PM PDT 24
Peak memory 210520 kb
Host smart-8e4ec785-1dec-4283-97ac-15641d78d853
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168514544 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.168514544
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.2775384904
Short name T315
Test name
Test status
Simulation time 161865874501 ps
CPU time 78.73 seconds
Started Jul 18 06:34:41 PM PDT 24
Finished Jul 18 06:36:01 PM PDT 24
Peak memory 201748 kb
Host smart-c429fbc1-0690-40f9-ac0d-877636b7abb3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775384904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gat
ing.2775384904
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.3793650111
Short name T240
Test name
Test status
Simulation time 482973828237 ps
CPU time 191.2 seconds
Started Jul 18 06:34:42 PM PDT 24
Finished Jul 18 06:37:54 PM PDT 24
Peak memory 201736 kb
Host smart-adf0f47c-bbeb-471f-a59f-b184cf2a57f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793650111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.3793650111
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.730758049
Short name T223
Test name
Test status
Simulation time 363152373865 ps
CPU time 54.02 seconds
Started Jul 18 06:31:41 PM PDT 24
Finished Jul 18 06:32:37 PM PDT 24
Peak memory 201756 kb
Host smart-eb66b025-b189-4ba1-a558-a698051ba087
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730758049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_w
akeup.730758049
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.2068325140
Short name T187
Test name
Test status
Simulation time 491959168262 ps
CPU time 289.79 seconds
Started Jul 18 06:33:51 PM PDT 24
Finished Jul 18 06:38:43 PM PDT 24
Peak memory 201804 kb
Host smart-13f11f92-122c-4530-b75a-5c126e45bfa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068325140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.2068325140
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.1598755735
Short name T176
Test name
Test status
Simulation time 157763178318 ps
CPU time 91.49 seconds
Started Jul 18 06:32:25 PM PDT 24
Finished Jul 18 06:33:58 PM PDT 24
Peak memory 201824 kb
Host smart-eb09b40c-5c87-4b51-a053-dca83a1939dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598755735 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.1598755735
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.1947377351
Short name T232
Test name
Test status
Simulation time 489063353138 ps
CPU time 1090.04 seconds
Started Jul 18 06:31:45 PM PDT 24
Finished Jul 18 06:50:00 PM PDT 24
Peak memory 201644 kb
Host smart-cac18da0-5c3e-4d76-a4e8-0d87fe0f4d49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947377351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.1947377351
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.2690732376
Short name T192
Test name
Test status
Simulation time 370797658316 ps
CPU time 1416.47 seconds
Started Jul 18 06:34:05 PM PDT 24
Finished Jul 18 06:57:44 PM PDT 24
Peak memory 210372 kb
Host smart-b147e785-16b9-499d-b8d5-2e712886aee9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690732376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all
.2690732376
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.3532797402
Short name T234
Test name
Test status
Simulation time 540482279919 ps
CPU time 633.5 seconds
Started Jul 18 06:36:34 PM PDT 24
Finished Jul 18 06:47:08 PM PDT 24
Peak memory 201744 kb
Host smart-7b5a3952-818a-49f5-81f8-09738b0cf7ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532797402 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.3532797402
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.3133996531
Short name T844
Test name
Test status
Simulation time 528746739 ps
CPU time 2.69 seconds
Started Jul 18 05:58:15 PM PDT 24
Finished Jul 18 05:58:23 PM PDT 24
Peak memory 209976 kb
Host smart-735cdb3c-a2e2-438d-ad06-8d18cfa1cfeb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133996531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.3133996531
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.748609856
Short name T4
Test name
Test status
Simulation time 161364998989 ps
CPU time 102.34 seconds
Started Jul 18 06:32:28 PM PDT 24
Finished Jul 18 06:34:13 PM PDT 24
Peak memory 201700 kb
Host smart-7036443f-7d79-464b-b4e9-d3452a2b8e85
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=748609856 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrup
t_fixed.748609856
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.1023011130
Short name T136
Test name
Test status
Simulation time 543791989256 ps
CPU time 299.6 seconds
Started Jul 18 06:32:33 PM PDT 24
Finished Jul 18 06:37:36 PM PDT 24
Peak memory 201756 kb
Host smart-25c3d635-a388-4af3-b4fd-055c27ff2f1b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023011130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters
_wakeup.1023011130
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.1614192574
Short name T251
Test name
Test status
Simulation time 431206611634 ps
CPU time 1248.83 seconds
Started Jul 18 06:36:50 PM PDT 24
Finished Jul 18 06:57:40 PM PDT 24
Peak memory 202184 kb
Host smart-a7aa4ecb-90d1-48af-9c72-bad916355ffc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614192574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all
.1614192574
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.1018101323
Short name T260
Test name
Test status
Simulation time 493327995823 ps
CPU time 605.62 seconds
Started Jul 18 06:37:46 PM PDT 24
Finished Jul 18 06:47:54 PM PDT 24
Peak memory 201736 kb
Host smart-157a4cf7-b7e5-4ee3-bb29-8db6942fa72d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018101323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.1018101323
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.3899780816
Short name T610
Test name
Test status
Simulation time 351482712430 ps
CPU time 212.49 seconds
Started Jul 18 06:31:48 PM PDT 24
Finished Jul 18 06:35:24 PM PDT 24
Peak memory 201696 kb
Host smart-5135ca0b-ac7c-49cf-8d5d-4afafc250017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899780816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.3899780816
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.3470120037
Short name T23
Test name
Test status
Simulation time 530489531468 ps
CPU time 1263.58 seconds
Started Jul 18 06:32:06 PM PDT 24
Finished Jul 18 06:53:15 PM PDT 24
Peak memory 201748 kb
Host smart-3b4262ca-98c7-41e0-aef4-c2c30f9d0452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470120037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.3470120037
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.2309603900
Short name T270
Test name
Test status
Simulation time 514296257317 ps
CPU time 605.51 seconds
Started Jul 18 06:31:45 PM PDT 24
Finished Jul 18 06:41:55 PM PDT 24
Peak memory 202004 kb
Host smart-e6479407-84c8-4673-a00a-e522858ad74c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309603900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gati
ng.2309603900
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.894966646
Short name T230
Test name
Test status
Simulation time 165814943010 ps
CPU time 370.19 seconds
Started Jul 18 06:32:24 PM PDT 24
Finished Jul 18 06:38:36 PM PDT 24
Peak memory 201756 kb
Host smart-4cc72bdc-b930-44aa-9e26-da2a702c1c8f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894966646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_
wakeup.894966646
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.801366299
Short name T20
Test name
Test status
Simulation time 191823239956 ps
CPU time 169.51 seconds
Started Jul 18 06:31:46 PM PDT 24
Finished Jul 18 06:34:40 PM PDT 24
Peak memory 202612 kb
Host smart-ea68c9ac-0896-43d1-b60a-2f52ab32f06c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801366299 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.801366299
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.3305090022
Short name T152
Test name
Test status
Simulation time 265983493755 ps
CPU time 284.34 seconds
Started Jul 18 06:32:52 PM PDT 24
Finished Jul 18 06:37:37 PM PDT 24
Peak memory 210444 kb
Host smart-e04e3faa-829a-4f01-ace1-c6377afe2faa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305090022 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.3305090022
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.924453553
Short name T235
Test name
Test status
Simulation time 491268039627 ps
CPU time 281.72 seconds
Started Jul 18 06:32:51 PM PDT 24
Finished Jul 18 06:37:34 PM PDT 24
Peak memory 201752 kb
Host smart-74422fc9-f313-40d5-b5ab-59eaaef2a0e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924453553 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.924453553
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.1277988550
Short name T134
Test name
Test status
Simulation time 623681413839 ps
CPU time 359.24 seconds
Started Jul 18 06:33:11 PM PDT 24
Finished Jul 18 06:39:12 PM PDT 24
Peak memory 201752 kb
Host smart-c02f4406-5cfe-4e9f-9a47-ca2e9ad01300
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277988550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters
_wakeup.1277988550
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.1189573844
Short name T209
Test name
Test status
Simulation time 254234783253 ps
CPU time 150.21 seconds
Started Jul 18 06:35:31 PM PDT 24
Finished Jul 18 06:38:02 PM PDT 24
Peak memory 210424 kb
Host smart-4456704b-7bdb-4ddc-9b2c-2b212674b141
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189573844 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.1189573844
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.3054654092
Short name T257
Test name
Test status
Simulation time 185869955881 ps
CPU time 439.67 seconds
Started Jul 18 06:37:33 PM PDT 24
Finished Jul 18 06:44:54 PM PDT 24
Peak memory 201760 kb
Host smart-db8610b4-8724-4767-83f1-1aff3753fd67
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054654092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gat
ing.3054654092
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.2162567120
Short name T265
Test name
Test status
Simulation time 372260690235 ps
CPU time 192.15 seconds
Started Jul 18 06:32:02 PM PDT 24
Finished Jul 18 06:35:15 PM PDT 24
Peak memory 201832 kb
Host smart-f4955a7f-7cfa-4645-bc8b-0858d2c583cb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162567120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_
wakeup.2162567120
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.2533469190
Short name T54
Test name
Test status
Simulation time 16298581715 ps
CPU time 36.62 seconds
Started Jul 18 05:58:17 PM PDT 24
Finished Jul 18 05:58:59 PM PDT 24
Peak memory 201808 kb
Host smart-5a3753cc-26a1-4c66-ad29-952b69333d26
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533469190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_
bash.2533469190
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.616156396
Short name T228
Test name
Test status
Simulation time 359720381310 ps
CPU time 285.92 seconds
Started Jul 18 06:31:44 PM PDT 24
Finished Jul 18 06:36:34 PM PDT 24
Peak memory 201812 kb
Host smart-91300328-7e36-4d8c-8c5a-dc0481232812
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616156396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_w
akeup.616156396
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.1281972108
Short name T322
Test name
Test status
Simulation time 519926672976 ps
CPU time 1234.92 seconds
Started Jul 18 06:32:28 PM PDT 24
Finished Jul 18 06:53:06 PM PDT 24
Peak memory 201752 kb
Host smart-22067ca7-a9c1-4e96-b0fc-2a7754777702
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281972108 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters
_wakeup.1281972108
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.1688538888
Short name T198
Test name
Test status
Simulation time 96654228843 ps
CPU time 453.21 seconds
Started Jul 18 06:32:36 PM PDT 24
Finished Jul 18 06:40:12 PM PDT 24
Peak memory 202104 kb
Host smart-eabfad0f-2952-44b3-b714-876633e3706d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688538888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.1688538888
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.4157741603
Short name T312
Test name
Test status
Simulation time 584929353974 ps
CPU time 1401.18 seconds
Started Jul 18 06:37:19 PM PDT 24
Finished Jul 18 07:00:42 PM PDT 24
Peak memory 201800 kb
Host smart-5f57638a-b988-47d0-87d0-2cd7b6e68363
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157741603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters
_wakeup.4157741603
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.656067894
Short name T60
Test name
Test status
Simulation time 4391305562 ps
CPU time 4.18 seconds
Started Jul 18 05:58:34 PM PDT 24
Finished Jul 18 05:58:47 PM PDT 24
Peak memory 201796 kb
Host smart-d5dd82b5-a956-437e-b1bb-da4958ba5a4f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656067894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_in
tg_err.656067894
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.4265836634
Short name T231
Test name
Test status
Simulation time 501798948527 ps
CPU time 133.25 seconds
Started Jul 18 06:31:42 PM PDT 24
Finished Jul 18 06:33:58 PM PDT 24
Peak memory 201804 kb
Host smart-d2b45827-6ce7-44ae-bde0-6edad2c75ff1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265836634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gati
ng.4265836634
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.457474803
Short name T168
Test name
Test status
Simulation time 497517886266 ps
CPU time 271.53 seconds
Started Jul 18 06:32:07 PM PDT 24
Finished Jul 18 06:36:44 PM PDT 24
Peak memory 201748 kb
Host smart-766bfb01-8c02-46e1-a211-ba7c8fa6334a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457474803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.457474803
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.3389395803
Short name T197
Test name
Test status
Simulation time 94660460694 ps
CPU time 355.57 seconds
Started Jul 18 06:32:06 PM PDT 24
Finished Jul 18 06:38:07 PM PDT 24
Peak memory 202088 kb
Host smart-f7224cae-c4f0-46b3-8dc5-b534778ef4ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389395803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.3389395803
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.202055804
Short name T47
Test name
Test status
Simulation time 126445687362 ps
CPU time 738.24 seconds
Started Jul 18 06:32:26 PM PDT 24
Finished Jul 18 06:44:47 PM PDT 24
Peak memory 202092 kb
Host smart-6e214671-79d6-4def-bae8-f4c6504ea054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202055804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.202055804
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.894908469
Short name T203
Test name
Test status
Simulation time 293181368833 ps
CPU time 516.36 seconds
Started Jul 18 06:32:25 PM PDT 24
Finished Jul 18 06:41:03 PM PDT 24
Peak memory 202252 kb
Host smart-dcd57907-9d5e-46f9-85e4-1dee456e00df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894908469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all.
894908469
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.150325114
Short name T348
Test name
Test status
Simulation time 136600160335 ps
CPU time 241.08 seconds
Started Jul 18 06:32:34 PM PDT 24
Finished Jul 18 06:36:39 PM PDT 24
Peak memory 217820 kb
Host smart-8b9b3d1f-9d75-493a-a912-76198e9ef5a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150325114 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.150325114
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.2747762874
Short name T278
Test name
Test status
Simulation time 488905759118 ps
CPU time 548.23 seconds
Started Jul 18 06:31:46 PM PDT 24
Finished Jul 18 06:40:59 PM PDT 24
Peak memory 201752 kb
Host smart-a6b6f23e-2bd3-42ac-bf06-725c77d70a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747762874 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.2747762874
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.3981324518
Short name T90
Test name
Test status
Simulation time 80976777866 ps
CPU time 353.49 seconds
Started Jul 18 06:33:23 PM PDT 24
Finished Jul 18 06:39:19 PM PDT 24
Peak memory 202184 kb
Host smart-28fb0f5b-8d20-47d7-8c88-f83ff2ae70cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981324518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.3981324518
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.2773671428
Short name T219
Test name
Test status
Simulation time 592591369748 ps
CPU time 457.25 seconds
Started Jul 18 06:35:01 PM PDT 24
Finished Jul 18 06:42:40 PM PDT 24
Peak memory 201864 kb
Host smart-0b591d96-2cc2-4824-80e2-9ec764d34fdb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773671428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gat
ing.2773671428
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.2694493628
Short name T2
Test name
Test status
Simulation time 188306837302 ps
CPU time 221.69 seconds
Started Jul 18 06:31:42 PM PDT 24
Finished Jul 18 06:35:27 PM PDT 24
Peak memory 201768 kb
Host smart-769d6ed1-5765-4cf3-b50a-c2bf391662c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694493628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.2694493628
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.2478780441
Short name T253
Test name
Test status
Simulation time 489308158015 ps
CPU time 298 seconds
Started Jul 18 06:31:40 PM PDT 24
Finished Jul 18 06:36:39 PM PDT 24
Peak memory 201744 kb
Host smart-206ae0d1-9362-412c-8c23-d7ab22401098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478780441 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.2478780441
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.845034240
Short name T247
Test name
Test status
Simulation time 523322512331 ps
CPU time 921.76 seconds
Started Jul 18 06:32:07 PM PDT 24
Finished Jul 18 06:47:34 PM PDT 24
Peak memory 201788 kb
Host smart-ceb88537-deda-49d8-9420-e207feb0bffa
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845034240 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gati
ng.845034240
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.3616619175
Short name T320
Test name
Test status
Simulation time 170420872717 ps
CPU time 197.32 seconds
Started Jul 18 06:32:24 PM PDT 24
Finished Jul 18 06:35:43 PM PDT 24
Peak memory 201824 kb
Host smart-5a7220d2-9464-4460-b6c4-47d51d3c4a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616619175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.3616619175
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.3640817504
Short name T765
Test name
Test status
Simulation time 489876052512 ps
CPU time 274.77 seconds
Started Jul 18 06:32:20 PM PDT 24
Finished Jul 18 06:36:57 PM PDT 24
Peak memory 201744 kb
Host smart-7f1dd3a1-25cd-4233-a622-8f63d49b4c6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640817504 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.3640817504
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.3051661995
Short name T336
Test name
Test status
Simulation time 334930495602 ps
CPU time 79.1 seconds
Started Jul 18 06:32:36 PM PDT 24
Finished Jul 18 06:33:59 PM PDT 24
Peak memory 201772 kb
Host smart-b1b65a23-e5a4-457a-8ce3-44b0dcaf5e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051661995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.3051661995
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.2710172606
Short name T153
Test name
Test status
Simulation time 357704978140 ps
CPU time 854 seconds
Started Jul 18 06:33:09 PM PDT 24
Finished Jul 18 06:47:25 PM PDT 24
Peak memory 201828 kb
Host smart-281654af-ccb4-4ac4-a8ad-cca934f1c553
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710172606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters
_wakeup.2710172606
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.3864820387
Short name T294
Test name
Test status
Simulation time 72693557408 ps
CPU time 130.27 seconds
Started Jul 18 06:33:22 PM PDT 24
Finished Jul 18 06:35:35 PM PDT 24
Peak memory 211456 kb
Host smart-2915ec1f-acc1-447b-95ed-f91b513ec78b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864820387 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.3864820387
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.3533481821
Short name T22
Test name
Test status
Simulation time 373985135883 ps
CPU time 227.68 seconds
Started Jul 18 06:35:45 PM PDT 24
Finished Jul 18 06:39:35 PM PDT 24
Peak memory 201756 kb
Host smart-db10c207-5a4c-40be-a6a5-392926616654
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533481821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters
_wakeup.3533481821
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.3244983781
Short name T326
Test name
Test status
Simulation time 326819814550 ps
CPU time 192.49 seconds
Started Jul 18 06:36:51 PM PDT 24
Finished Jul 18 06:40:05 PM PDT 24
Peak memory 201736 kb
Host smart-168a4b83-4245-4975-ab79-c424903035d3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244983781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gat
ing.3244983781
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.3448236914
Short name T327
Test name
Test status
Simulation time 354913951719 ps
CPU time 768.56 seconds
Started Jul 18 06:37:33 PM PDT 24
Finished Jul 18 06:50:22 PM PDT 24
Peak memory 201908 kb
Host smart-577c56f2-7994-4618-9144-1030f281e90d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448236914 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.3448236914
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.4033058748
Short name T284
Test name
Test status
Simulation time 483577057017 ps
CPU time 312.6 seconds
Started Jul 18 06:37:32 PM PDT 24
Finished Jul 18 06:42:45 PM PDT 24
Peak memory 201820 kb
Host smart-c3bb30ae-9501-4a93-a3a9-607afc745c44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033058748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.4033058748
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.330323043
Short name T272
Test name
Test status
Simulation time 356257755847 ps
CPU time 428.05 seconds
Started Jul 18 06:37:48 PM PDT 24
Finished Jul 18 06:44:58 PM PDT 24
Peak memory 201752 kb
Host smart-4843b193-945e-482e-a3e5-f62f0211ae15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330323043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.330323043
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.2930916583
Short name T303
Test name
Test status
Simulation time 341072184021 ps
CPU time 794.78 seconds
Started Jul 18 06:32:06 PM PDT 24
Finished Jul 18 06:45:26 PM PDT 24
Peak memory 201748 kb
Host smart-da4b8439-048f-43c2-bb4c-80b29bb6a56d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930916583 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.2930916583
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.1624909730
Short name T353
Test name
Test status
Simulation time 101147914071 ps
CPU time 509.78 seconds
Started Jul 18 06:32:05 PM PDT 24
Finished Jul 18 06:40:40 PM PDT 24
Peak memory 202200 kb
Host smart-33246be0-a8ce-40d0-b08e-691f800e00a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624909730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.1624909730
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.2995540476
Short name T216
Test name
Test status
Simulation time 332804482807 ps
CPU time 55.76 seconds
Started Jul 18 06:32:04 PM PDT 24
Finished Jul 18 06:33:04 PM PDT 24
Peak memory 201796 kb
Host smart-2ad72843-a75d-4187-8153-46b8d632cda7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995540476 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.2995540476
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.2364002176
Short name T343
Test name
Test status
Simulation time 492098995867 ps
CPU time 1087.78 seconds
Started Jul 18 06:32:03 PM PDT 24
Finished Jul 18 06:50:13 PM PDT 24
Peak memory 201732 kb
Host smart-76b03641-ffa8-4645-acbc-619733ba58dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364002176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.2364002176
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.2731841537
Short name T108
Test name
Test status
Simulation time 1021124640 ps
CPU time 2.91 seconds
Started Jul 18 05:58:15 PM PDT 24
Finished Jul 18 05:58:24 PM PDT 24
Peak memory 201656 kb
Host smart-9208375b-b509-45a6-b9c3-9d516f515683
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731841537 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alia
sing.2731841537
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.2666248798
Short name T897
Test name
Test status
Simulation time 644134000 ps
CPU time 2.2 seconds
Started Jul 18 05:58:13 PM PDT 24
Finished Jul 18 05:58:22 PM PDT 24
Peak memory 201436 kb
Host smart-e402b000-e472-4a12-bce0-7f7bf30ecc8d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666248798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_r
eset.2666248798
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.1900479412
Short name T81
Test name
Test status
Simulation time 562469662 ps
CPU time 1.17 seconds
Started Jul 18 05:58:16 PM PDT 24
Finished Jul 18 05:58:23 PM PDT 24
Peak memory 201612 kb
Host smart-90ca5179-ab48-45f7-a485-b93dcf930449
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900479412 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.1900479412
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.1575331086
Short name T102
Test name
Test status
Simulation time 481985854 ps
CPU time 1.87 seconds
Started Jul 18 05:58:17 PM PDT 24
Finished Jul 18 05:58:24 PM PDT 24
Peak memory 201420 kb
Host smart-cda1f795-3081-43b6-afcf-ba0eefa485bb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575331086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.1575331086
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.3751928107
Short name T856
Test name
Test status
Simulation time 616970990 ps
CPU time 0.71 seconds
Started Jul 18 05:58:22 PM PDT 24
Finished Jul 18 05:58:29 PM PDT 24
Peak memory 201468 kb
Host smart-3dbf0bc0-a96e-4fd6-9f9a-f82e4e8d605f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751928107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.3751928107
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.2841880039
Short name T831
Test name
Test status
Simulation time 1996928328 ps
CPU time 2.83 seconds
Started Jul 18 05:58:13 PM PDT 24
Finished Jul 18 05:58:23 PM PDT 24
Peak memory 201524 kb
Host smart-faa1dd11-4d0f-4400-9a0f-3a8a7e683e22
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841880039 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_c
trl_same_csr_outstanding.2841880039
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.279131905
Short name T900
Test name
Test status
Simulation time 727195884 ps
CPU time 2.14 seconds
Started Jul 18 05:58:18 PM PDT 24
Finished Jul 18 05:58:25 PM PDT 24
Peak memory 201624 kb
Host smart-ab7a53a9-83db-4bd9-857d-0c4bfa5af815
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279131905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alias
ing.279131905
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.3062246966
Short name T887
Test name
Test status
Simulation time 13766006064 ps
CPU time 18.72 seconds
Started Jul 18 05:58:15 PM PDT 24
Finished Jul 18 05:58:39 PM PDT 24
Peak memory 201684 kb
Host smart-ac2e7e6a-2b76-4724-9203-63332b3e1cab
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062246966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_
bash.3062246966
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.319954119
Short name T99
Test name
Test status
Simulation time 1252209470 ps
CPU time 1.28 seconds
Started Jul 18 05:58:24 PM PDT 24
Finished Jul 18 05:58:33 PM PDT 24
Peak memory 201432 kb
Host smart-748dd8a8-349c-48de-b9b6-d19d0eb481ae
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319954119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_re
set.319954119
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.874249820
Short name T915
Test name
Test status
Simulation time 763765888 ps
CPU time 1.15 seconds
Started Jul 18 05:58:17 PM PDT 24
Finished Jul 18 05:58:23 PM PDT 24
Peak memory 201564 kb
Host smart-fafc7587-be27-4965-9e57-d60bbc6a573d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874249820 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.874249820
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.3311357578
Short name T100
Test name
Test status
Simulation time 321811559 ps
CPU time 1.55 seconds
Started Jul 18 05:58:13 PM PDT 24
Finished Jul 18 05:58:22 PM PDT 24
Peak memory 201452 kb
Host smart-44c46fff-fcd3-4461-9e6f-611bcf40e25b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311357578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.3311357578
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.4078992659
Short name T801
Test name
Test status
Simulation time 498201028 ps
CPU time 1.79 seconds
Started Jul 18 05:58:24 PM PDT 24
Finished Jul 18 05:58:33 PM PDT 24
Peak memory 201408 kb
Host smart-aa43c248-918a-40e7-9f88-7c9e1104315b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078992659 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.4078992659
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.3812015239
Short name T864
Test name
Test status
Simulation time 2418192866 ps
CPU time 1.23 seconds
Started Jul 18 05:58:18 PM PDT 24
Finished Jul 18 05:58:24 PM PDT 24
Peak memory 201600 kb
Host smart-c2abf12f-feb2-4fcb-b0e8-0a35a04ebd00
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812015239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_c
trl_same_csr_outstanding.3812015239
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.3196551933
Short name T80
Test name
Test status
Simulation time 411492768 ps
CPU time 3.08 seconds
Started Jul 18 05:58:23 PM PDT 24
Finished Jul 18 05:58:32 PM PDT 24
Peak memory 202060 kb
Host smart-e225c13c-6256-414a-b1c5-30e38262f9c2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196551933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.3196551933
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.1902989047
Short name T85
Test name
Test status
Simulation time 8084133940 ps
CPU time 20.31 seconds
Started Jul 18 05:58:23 PM PDT 24
Finished Jul 18 05:58:49 PM PDT 24
Peak memory 201700 kb
Host smart-22a7e9e5-4fe9-4ee2-9c68-d5485f0adf09
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902989047 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_in
tg_err.1902989047
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.2844678502
Short name T888
Test name
Test status
Simulation time 658968802 ps
CPU time 1.37 seconds
Started Jul 18 05:58:19 PM PDT 24
Finished Jul 18 05:58:26 PM PDT 24
Peak memory 201520 kb
Host smart-2b526d4d-419f-44ed-bbae-8187ab1cb0da
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844678502 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.2844678502
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.1763062448
Short name T107
Test name
Test status
Simulation time 460821451 ps
CPU time 1.8 seconds
Started Jul 18 05:58:24 PM PDT 24
Finished Jul 18 05:58:33 PM PDT 24
Peak memory 201376 kb
Host smart-2f2978b2-862b-4c77-8afd-ec928557fd6d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763062448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.1763062448
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.1022173913
Short name T875
Test name
Test status
Simulation time 565722295 ps
CPU time 0.74 seconds
Started Jul 18 05:58:27 PM PDT 24
Finished Jul 18 05:58:36 PM PDT 24
Peak memory 201376 kb
Host smart-6c814dc3-7544-46a9-84d1-e26c0c789437
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022173913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.1022173913
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.4022194409
Short name T826
Test name
Test status
Simulation time 4460432061 ps
CPU time 4.34 seconds
Started Jul 18 05:58:16 PM PDT 24
Finished Jul 18 05:58:26 PM PDT 24
Peak memory 201724 kb
Host smart-d44ae0ae-7545-40ac-8f7a-048724646cce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022194409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_
ctrl_same_csr_outstanding.4022194409
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.480674343
Short name T858
Test name
Test status
Simulation time 384137598 ps
CPU time 2.61 seconds
Started Jul 18 05:58:28 PM PDT 24
Finished Jul 18 05:58:40 PM PDT 24
Peak memory 201704 kb
Host smart-eaa83e2d-075d-4062-b138-72de12d159fe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480674343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.480674343
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.440239779
Short name T79
Test name
Test status
Simulation time 8153821591 ps
CPU time 21.17 seconds
Started Jul 18 05:58:29 PM PDT 24
Finished Jul 18 05:58:59 PM PDT 24
Peak memory 201752 kb
Host smart-159a3b2e-1d8c-4069-9a19-193ee6006961
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440239779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_in
tg_err.440239779
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.2747654173
Short name T833
Test name
Test status
Simulation time 748588376 ps
CPU time 1.26 seconds
Started Jul 18 05:58:21 PM PDT 24
Finished Jul 18 05:58:28 PM PDT 24
Peak memory 210052 kb
Host smart-6b873396-9e80-4ed4-8557-77d7adc13555
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747654173 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.2747654173
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.3863093064
Short name T104
Test name
Test status
Simulation time 509007449 ps
CPU time 1.99 seconds
Started Jul 18 05:58:27 PM PDT 24
Finished Jul 18 05:58:38 PM PDT 24
Peak memory 201388 kb
Host smart-30b1cf6e-7f60-4359-bc51-a6ba50a470f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863093064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.3863093064
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.892217429
Short name T882
Test name
Test status
Simulation time 451921384 ps
CPU time 0.87 seconds
Started Jul 18 05:58:15 PM PDT 24
Finished Jul 18 05:58:22 PM PDT 24
Peak memory 201420 kb
Host smart-6e398f23-a38d-49b1-96b2-1d56bcf624c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892217429 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.892217429
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.801228043
Short name T919
Test name
Test status
Simulation time 4140981312 ps
CPU time 5.91 seconds
Started Jul 18 05:58:22 PM PDT 24
Finished Jul 18 05:58:34 PM PDT 24
Peak memory 201732 kb
Host smart-213dc41f-8210-45b3-85ac-270439e0d765
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801228043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_c
trl_same_csr_outstanding.801228043
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.3346722527
Short name T859
Test name
Test status
Simulation time 437623866 ps
CPU time 2.05 seconds
Started Jul 18 05:58:28 PM PDT 24
Finished Jul 18 05:58:40 PM PDT 24
Peak memory 201728 kb
Host smart-3f95bb5b-59ff-462a-8d5c-f58a3cb93e77
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346722527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.3346722527
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.1396682907
Short name T871
Test name
Test status
Simulation time 4918915344 ps
CPU time 13.19 seconds
Started Jul 18 05:58:27 PM PDT 24
Finished Jul 18 05:58:49 PM PDT 24
Peak memory 201772 kb
Host smart-4b81b004-b738-49c3-887c-69f88642c433
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396682907 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_i
ntg_err.1396682907
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.1345058442
Short name T904
Test name
Test status
Simulation time 537662414 ps
CPU time 1.74 seconds
Started Jul 18 05:58:15 PM PDT 24
Finished Jul 18 05:58:22 PM PDT 24
Peak memory 201608 kb
Host smart-69d1ffa0-6912-471b-b270-9b5481dbf2b4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345058442 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.1345058442
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.3708135573
Short name T97
Test name
Test status
Simulation time 361781621 ps
CPU time 1.4 seconds
Started Jul 18 05:58:28 PM PDT 24
Finished Jul 18 05:58:39 PM PDT 24
Peak memory 201388 kb
Host smart-a49cbf7b-9036-4f03-a78f-ae16716aa8e9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708135573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.3708135573
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.2632294852
Short name T816
Test name
Test status
Simulation time 386891788 ps
CPU time 0.83 seconds
Started Jul 18 05:58:25 PM PDT 24
Finished Jul 18 05:58:33 PM PDT 24
Peak memory 201404 kb
Host smart-8c1bdbaa-386f-40c6-a4e3-0a447824d158
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632294852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.2632294852
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.156101317
Short name T823
Test name
Test status
Simulation time 2047737824 ps
CPU time 3.23 seconds
Started Jul 18 05:58:28 PM PDT 24
Finished Jul 18 05:58:41 PM PDT 24
Peak memory 201456 kb
Host smart-5da9cf69-c689-42ad-89c4-0048d11d5733
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156101317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_c
trl_same_csr_outstanding.156101317
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.1912588814
Short name T71
Test name
Test status
Simulation time 315253706 ps
CPU time 2.45 seconds
Started Jul 18 05:58:21 PM PDT 24
Finished Jul 18 05:58:29 PM PDT 24
Peak memory 201832 kb
Host smart-5449f6fa-8bf4-4bc5-ae21-de601d82c386
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912588814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.1912588814
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.1048825639
Short name T903
Test name
Test status
Simulation time 4721868773 ps
CPU time 11.14 seconds
Started Jul 18 05:58:18 PM PDT 24
Finished Jul 18 05:58:35 PM PDT 24
Peak memory 201856 kb
Host smart-54e22f28-6cec-40d8-acbc-eb28aa019679
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048825639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_i
ntg_err.1048825639
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.1692796150
Short name T96
Test name
Test status
Simulation time 608947400 ps
CPU time 1.15 seconds
Started Jul 18 05:58:40 PM PDT 24
Finished Jul 18 05:58:47 PM PDT 24
Peak memory 201824 kb
Host smart-62bd823b-28a8-4527-a3ea-0906d5dad8bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692796150 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.1692796150
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.386933315
Short name T111
Test name
Test status
Simulation time 427801625 ps
CPU time 1.65 seconds
Started Jul 18 05:58:17 PM PDT 24
Finished Jul 18 05:58:24 PM PDT 24
Peak memory 201472 kb
Host smart-a0f0294e-78da-4567-9d4f-c7411fa7b9b2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386933315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.386933315
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.3422407377
Short name T809
Test name
Test status
Simulation time 582621350 ps
CPU time 0.78 seconds
Started Jul 18 05:58:26 PM PDT 24
Finished Jul 18 05:58:36 PM PDT 24
Peak memory 201464 kb
Host smart-059003a7-6190-4c9c-946b-0f6fb9ac446c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422407377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.3422407377
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.1418648808
Short name T836
Test name
Test status
Simulation time 4369965846 ps
CPU time 3.54 seconds
Started Jul 18 05:58:27 PM PDT 24
Finished Jul 18 05:58:40 PM PDT 24
Peak memory 201824 kb
Host smart-0e571d43-abf6-49eb-a651-5ca19cb2fdf5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418648808 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_
ctrl_same_csr_outstanding.1418648808
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.2584890011
Short name T78
Test name
Test status
Simulation time 555524941 ps
CPU time 2.2 seconds
Started Jul 18 05:58:28 PM PDT 24
Finished Jul 18 05:58:40 PM PDT 24
Peak memory 201744 kb
Host smart-00f1770b-4a20-4c20-b90d-c4254aae7714
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584890011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.2584890011
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.2102654645
Short name T889
Test name
Test status
Simulation time 4481450226 ps
CPU time 12.33 seconds
Started Jul 18 05:58:27 PM PDT 24
Finished Jul 18 05:58:48 PM PDT 24
Peak memory 201744 kb
Host smart-d1799124-b56e-4ac6-ba21-d48a5fb299eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102654645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_i
ntg_err.2102654645
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.2939242837
Short name T857
Test name
Test status
Simulation time 351775803 ps
CPU time 1.19 seconds
Started Jul 18 05:58:31 PM PDT 24
Finished Jul 18 05:58:41 PM PDT 24
Peak memory 201552 kb
Host smart-c8693435-dea5-41ed-8b61-d5e10035724a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939242837 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.2939242837
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.141083561
Short name T101
Test name
Test status
Simulation time 562367981 ps
CPU time 1.06 seconds
Started Jul 18 05:58:33 PM PDT 24
Finished Jul 18 05:58:42 PM PDT 24
Peak memory 201384 kb
Host smart-2eb54af2-1947-4835-a24f-5261143a3ee3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141083561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.141083561
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.823900738
Short name T860
Test name
Test status
Simulation time 414777943 ps
CPU time 1.06 seconds
Started Jul 18 05:58:35 PM PDT 24
Finished Jul 18 05:58:45 PM PDT 24
Peak memory 201460 kb
Host smart-1567b830-9855-4ea0-914f-a620cd2b7ddf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823900738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.823900738
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.2017731498
Short name T902
Test name
Test status
Simulation time 3937637997 ps
CPU time 3.04 seconds
Started Jul 18 05:58:38 PM PDT 24
Finished Jul 18 05:58:48 PM PDT 24
Peak memory 201756 kb
Host smart-29dce858-41fc-4bac-912e-517d102c0b1c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017731498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_
ctrl_same_csr_outstanding.2017731498
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.4069192762
Short name T909
Test name
Test status
Simulation time 902839406 ps
CPU time 2.94 seconds
Started Jul 18 05:58:34 PM PDT 24
Finished Jul 18 05:58:46 PM PDT 24
Peak memory 201784 kb
Host smart-0ea0413d-31ba-4548-9f5f-ef74c1183e84
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069192762 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.4069192762
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.2780473745
Short name T74
Test name
Test status
Simulation time 8988477192 ps
CPU time 23.1 seconds
Started Jul 18 05:58:27 PM PDT 24
Finished Jul 18 05:58:59 PM PDT 24
Peak memory 201812 kb
Host smart-fc8d6a99-c561-4196-bba7-753dccce113f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780473745 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_i
ntg_err.2780473745
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.1617715663
Short name T84
Test name
Test status
Simulation time 520549378 ps
CPU time 1.09 seconds
Started Jul 18 05:58:39 PM PDT 24
Finished Jul 18 05:58:46 PM PDT 24
Peak memory 201584 kb
Host smart-2e82a3e4-4acf-4409-b3a8-59ed67e539fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617715663 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.1617715663
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.283783851
Short name T822
Test name
Test status
Simulation time 530978549 ps
CPU time 1 seconds
Started Jul 18 05:58:33 PM PDT 24
Finished Jul 18 05:58:43 PM PDT 24
Peak memory 201472 kb
Host smart-33387a2f-5303-47ed-b862-89f391eb3a3c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283783851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.283783851
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.274042103
Short name T872
Test name
Test status
Simulation time 444415172 ps
CPU time 0.81 seconds
Started Jul 18 05:58:34 PM PDT 24
Finished Jul 18 05:58:44 PM PDT 24
Peak memory 201432 kb
Host smart-9c63b28c-dcc1-42ba-ac70-6e5c3dacfdbd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274042103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.274042103
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.1890338600
Short name T878
Test name
Test status
Simulation time 4181857940 ps
CPU time 4.94 seconds
Started Jul 18 05:58:40 PM PDT 24
Finished Jul 18 05:58:51 PM PDT 24
Peak memory 201708 kb
Host smart-cd903c92-056c-4f00-bc29-f6a735f32b72
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890338600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_
ctrl_same_csr_outstanding.1890338600
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.3988042966
Short name T82
Test name
Test status
Simulation time 8567084125 ps
CPU time 20.48 seconds
Started Jul 18 05:58:38 PM PDT 24
Finished Jul 18 05:59:06 PM PDT 24
Peak memory 201288 kb
Host smart-4112d43b-d0e5-4359-a517-41ade9313ce9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988042966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_i
ntg_err.3988042966
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.1570052908
Short name T851
Test name
Test status
Simulation time 535063987 ps
CPU time 2.05 seconds
Started Jul 18 05:58:31 PM PDT 24
Finished Jul 18 05:58:42 PM PDT 24
Peak memory 201552 kb
Host smart-1193ee80-02c6-47eb-9c16-7dea8e6bc92e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570052908 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.1570052908
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.1974424255
Short name T105
Test name
Test status
Simulation time 544114572 ps
CPU time 1.88 seconds
Started Jul 18 05:58:31 PM PDT 24
Finished Jul 18 05:58:41 PM PDT 24
Peak memory 201420 kb
Host smart-4b252587-f49e-4080-8ea1-a2ae0f76139b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974424255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.1974424255
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.887600200
Short name T829
Test name
Test status
Simulation time 434044325 ps
CPU time 1.59 seconds
Started Jul 18 05:58:34 PM PDT 24
Finished Jul 18 05:58:45 PM PDT 24
Peak memory 201376 kb
Host smart-d5dccb1e-e82b-465c-8364-43e6d5969215
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887600200 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.887600200
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.495569669
Short name T52
Test name
Test status
Simulation time 5223337086 ps
CPU time 14.98 seconds
Started Jul 18 05:58:29 PM PDT 24
Finished Jul 18 05:58:53 PM PDT 24
Peak memory 201796 kb
Host smart-cd3b56ee-8914-4266-8ea4-4d600445f883
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495569669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_c
trl_same_csr_outstanding.495569669
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.816116194
Short name T868
Test name
Test status
Simulation time 590566161 ps
CPU time 2.18 seconds
Started Jul 18 05:58:26 PM PDT 24
Finished Jul 18 05:58:36 PM PDT 24
Peak memory 201808 kb
Host smart-29c5d157-1c19-4a46-b10b-ab9251808b68
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816116194 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.816116194
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.1650838743
Short name T346
Test name
Test status
Simulation time 8456528371 ps
CPU time 7.16 seconds
Started Jul 18 05:58:36 PM PDT 24
Finished Jul 18 05:58:51 PM PDT 24
Peak memory 201716 kb
Host smart-b80ef7c9-0f5a-4e1b-8535-2fa79810ee7d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650838743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_i
ntg_err.1650838743
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.3272695143
Short name T862
Test name
Test status
Simulation time 366563469 ps
CPU time 1.03 seconds
Started Jul 18 05:58:27 PM PDT 24
Finished Jul 18 05:58:37 PM PDT 24
Peak memory 201564 kb
Host smart-8fd2cce5-052a-4c97-b33d-2d00854905ce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272695143 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.3272695143
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.1270573791
Short name T879
Test name
Test status
Simulation time 416901801 ps
CPU time 0.78 seconds
Started Jul 18 05:58:39 PM PDT 24
Finished Jul 18 05:58:47 PM PDT 24
Peak memory 201396 kb
Host smart-08823487-faa7-48a5-876a-50a7dd61e3ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270573791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.1270573791
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.1575869955
Short name T814
Test name
Test status
Simulation time 353660522 ps
CPU time 0.75 seconds
Started Jul 18 05:58:31 PM PDT 24
Finished Jul 18 05:58:40 PM PDT 24
Peak memory 201412 kb
Host smart-36bdfca9-4406-4c71-98d5-db55cfb2d03e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575869955 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.1575869955
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.3592764422
Short name T893
Test name
Test status
Simulation time 2178263038 ps
CPU time 3.23 seconds
Started Jul 18 05:58:33 PM PDT 24
Finished Jul 18 05:58:46 PM PDT 24
Peak memory 201556 kb
Host smart-29dc8f94-aae5-4726-93f5-cada35264f16
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592764422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_
ctrl_same_csr_outstanding.3592764422
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.2465352313
Short name T848
Test name
Test status
Simulation time 452684996 ps
CPU time 2.51 seconds
Started Jul 18 05:58:35 PM PDT 24
Finished Jul 18 05:58:46 PM PDT 24
Peak memory 201728 kb
Host smart-b72a67be-fe15-4524-b553-a62ef3083de1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465352313 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.2465352313
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.3495612858
Short name T842
Test name
Test status
Simulation time 7856998501 ps
CPU time 19.22 seconds
Started Jul 18 05:58:33 PM PDT 24
Finished Jul 18 05:59:02 PM PDT 24
Peak memory 201800 kb
Host smart-dff02e62-4e9c-4c16-ae20-b6579c34db8d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495612858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_i
ntg_err.3495612858
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.1905211636
Short name T63
Test name
Test status
Simulation time 526826007 ps
CPU time 2.18 seconds
Started Jul 18 05:58:37 PM PDT 24
Finished Jul 18 05:58:47 PM PDT 24
Peak memory 201612 kb
Host smart-62075fbf-1827-4a2b-817f-bd749b1c5eb4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905211636 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.1905211636
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.488195706
Short name T819
Test name
Test status
Simulation time 474895216 ps
CPU time 1.09 seconds
Started Jul 18 05:58:27 PM PDT 24
Finished Jul 18 05:58:38 PM PDT 24
Peak memory 201696 kb
Host smart-b3add750-5ab3-492f-9d79-7ce16cc2bd14
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488195706 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.488195706
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.1485270318
Short name T805
Test name
Test status
Simulation time 538162320 ps
CPU time 0.95 seconds
Started Jul 18 05:58:27 PM PDT 24
Finished Jul 18 05:58:37 PM PDT 24
Peak memory 201460 kb
Host smart-e681bb4a-a3b4-4b8c-ba53-d235134ebdb8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485270318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.1485270318
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.377809176
Short name T908
Test name
Test status
Simulation time 4351291792 ps
CPU time 9.61 seconds
Started Jul 18 05:58:31 PM PDT 24
Finished Jul 18 05:58:49 PM PDT 24
Peak memory 201740 kb
Host smart-c9162d7d-645c-4435-912b-9184e00b1e05
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377809176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_c
trl_same_csr_outstanding.377809176
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.951247742
Short name T73
Test name
Test status
Simulation time 644972486 ps
CPU time 1.63 seconds
Started Jul 18 05:58:26 PM PDT 24
Finished Jul 18 05:58:36 PM PDT 24
Peak memory 201828 kb
Host smart-2f5116ae-07b1-446e-b514-a54940705141
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951247742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.951247742
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.528923607
Short name T837
Test name
Test status
Simulation time 505434805 ps
CPU time 2.11 seconds
Started Jul 18 05:58:30 PM PDT 24
Finished Jul 18 05:58:41 PM PDT 24
Peak memory 201612 kb
Host smart-9c80d2aa-df6d-4d8b-8e29-669d5e14acbe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528923607 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.528923607
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.76290289
Short name T847
Test name
Test status
Simulation time 373715724 ps
CPU time 0.81 seconds
Started Jul 18 05:58:35 PM PDT 24
Finished Jul 18 05:58:44 PM PDT 24
Peak memory 201428 kb
Host smart-87049f5c-575c-440b-b2bf-35d35977bea1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76290289 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.76290289
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.1926848443
Short name T855
Test name
Test status
Simulation time 4486405591 ps
CPU time 11.01 seconds
Started Jul 18 05:58:40 PM PDT 24
Finished Jul 18 05:58:57 PM PDT 24
Peak memory 201716 kb
Host smart-603bf63c-8ede-4dae-877d-3d21310d7edd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926848443 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_
ctrl_same_csr_outstanding.1926848443
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.3457113435
Short name T838
Test name
Test status
Simulation time 446861428 ps
CPU time 1.64 seconds
Started Jul 18 05:58:30 PM PDT 24
Finished Jul 18 05:58:40 PM PDT 24
Peak memory 201876 kb
Host smart-20b7cbea-082d-4f1e-9732-8dcb1a3006d9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457113435 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.3457113435
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.591700900
Short name T72
Test name
Test status
Simulation time 8874642128 ps
CPU time 12.26 seconds
Started Jul 18 05:58:33 PM PDT 24
Finished Jul 18 05:58:54 PM PDT 24
Peak memory 201752 kb
Host smart-44d7b09b-6f0e-4968-b76b-eb517262bb75
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591700900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_in
tg_err.591700900
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.4198126798
Short name T98
Test name
Test status
Simulation time 1545365893 ps
CPU time 2.5 seconds
Started Jul 18 05:58:16 PM PDT 24
Finished Jul 18 05:58:24 PM PDT 24
Peak memory 201792 kb
Host smart-93b3bca9-e3fa-44c1-8269-e4b2ce543364
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198126798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alia
sing.4198126798
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.1607463905
Short name T901
Test name
Test status
Simulation time 23837669806 ps
CPU time 49.29 seconds
Started Jul 18 05:58:26 PM PDT 24
Finished Jul 18 05:59:23 PM PDT 24
Peak memory 201712 kb
Host smart-3c5c4b05-90d6-46e2-bf19-81f54db20c57
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607463905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_
bash.1607463905
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.3216837828
Short name T880
Test name
Test status
Simulation time 601996036 ps
CPU time 2.17 seconds
Started Jul 18 06:00:03 PM PDT 24
Finished Jul 18 06:00:11 PM PDT 24
Peak memory 201436 kb
Host smart-a6ed54cf-ed66-4e67-8288-d5ba07c3a87f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216837828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_r
eset.3216837828
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.2737572525
Short name T83
Test name
Test status
Simulation time 620159393 ps
CPU time 1.65 seconds
Started Jul 18 05:58:25 PM PDT 24
Finished Jul 18 05:58:35 PM PDT 24
Peak memory 201612 kb
Host smart-509ae126-ec8e-4b00-8ddb-f12ec1cdab92
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737572525 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.2737572525
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.1924346797
Short name T896
Test name
Test status
Simulation time 557882755 ps
CPU time 1.06 seconds
Started Jul 18 05:58:15 PM PDT 24
Finished Jul 18 05:58:22 PM PDT 24
Peak memory 201460 kb
Host smart-183187ee-b60a-44e6-9ac1-b37e0086824d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924346797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.1924346797
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.2178130736
Short name T827
Test name
Test status
Simulation time 316116956 ps
CPU time 1.03 seconds
Started Jul 18 05:58:19 PM PDT 24
Finished Jul 18 05:58:26 PM PDT 24
Peak memory 201432 kb
Host smart-d04f86d8-3384-4d14-97b7-0d262ea6dcf6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178130736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.2178130736
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.4171996951
Short name T910
Test name
Test status
Simulation time 3998282986 ps
CPU time 8.34 seconds
Started Jul 18 05:58:22 PM PDT 24
Finished Jul 18 05:58:36 PM PDT 24
Peak memory 202008 kb
Host smart-09eca649-96f9-4c05-8b57-abb5e1994e4f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171996951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_c
trl_same_csr_outstanding.4171996951
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.1248157967
Short name T854
Test name
Test status
Simulation time 1019655557 ps
CPU time 2.63 seconds
Started Jul 18 05:58:27 PM PDT 24
Finished Jul 18 05:58:38 PM PDT 24
Peak memory 201832 kb
Host smart-a91b3372-fbfc-483c-b4ce-d8d9b3507c92
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248157967 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.1248157967
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.1210872409
Short name T853
Test name
Test status
Simulation time 8458650659 ps
CPU time 3.86 seconds
Started Jul 18 05:58:20 PM PDT 24
Finished Jul 18 05:58:30 PM PDT 24
Peak memory 201860 kb
Host smart-06c6b105-b1c7-4450-a76c-cfdf321fb580
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210872409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_in
tg_err.1210872409
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.1274960297
Short name T810
Test name
Test status
Simulation time 329355650 ps
CPU time 1.38 seconds
Started Jul 18 05:58:38 PM PDT 24
Finished Jul 18 05:58:47 PM PDT 24
Peak memory 200992 kb
Host smart-0fc3145f-b8a2-4775-a705-a3dcdee0d295
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274960297 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.1274960297
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.1864133494
Short name T834
Test name
Test status
Simulation time 292012626 ps
CPU time 1.25 seconds
Started Jul 18 05:58:36 PM PDT 24
Finished Jul 18 05:58:45 PM PDT 24
Peak memory 201424 kb
Host smart-61003fb9-e2b5-495a-a097-0690f07e7346
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864133494 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.1864133494
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.2715614579
Short name T811
Test name
Test status
Simulation time 480803062 ps
CPU time 0.91 seconds
Started Jul 18 05:58:27 PM PDT 24
Finished Jul 18 05:58:36 PM PDT 24
Peak memory 201492 kb
Host smart-523c20da-5578-4e38-82c5-5fbe23300ce9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715614579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.2715614579
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.2429151614
Short name T832
Test name
Test status
Simulation time 461560603 ps
CPU time 0.9 seconds
Started Jul 18 05:58:28 PM PDT 24
Finished Jul 18 05:58:37 PM PDT 24
Peak memory 201456 kb
Host smart-fe660b97-3acc-4454-8a2e-8f45817d4dea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429151614 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.2429151614
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.3715960879
Short name T835
Test name
Test status
Simulation time 329875199 ps
CPU time 1.48 seconds
Started Jul 18 05:58:38 PM PDT 24
Finished Jul 18 05:58:47 PM PDT 24
Peak memory 201388 kb
Host smart-a3679af6-5d25-4554-a155-9d59a292f91b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715960879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.3715960879
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.1049435882
Short name T813
Test name
Test status
Simulation time 537755061 ps
CPU time 1.14 seconds
Started Jul 18 05:58:38 PM PDT 24
Finished Jul 18 05:58:46 PM PDT 24
Peak memory 201432 kb
Host smart-fb4b3d06-60dc-4634-8332-1225133a6c5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049435882 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.1049435882
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.139453138
Short name T863
Test name
Test status
Simulation time 414541928 ps
CPU time 1.69 seconds
Started Jul 18 05:58:38 PM PDT 24
Finished Jul 18 05:58:47 PM PDT 24
Peak memory 201464 kb
Host smart-a0d872d1-e0c4-4fe7-8c08-87b51244c5a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139453138 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.139453138
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.3631885163
Short name T803
Test name
Test status
Simulation time 357692716 ps
CPU time 0.73 seconds
Started Jul 18 05:58:38 PM PDT 24
Finished Jul 18 05:58:46 PM PDT 24
Peak memory 201444 kb
Host smart-b83170fd-a3f9-43c3-a8cd-fac3b6ec0f0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631885163 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.3631885163
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.2410532456
Short name T802
Test name
Test status
Simulation time 622524774 ps
CPU time 0.73 seconds
Started Jul 18 05:58:36 PM PDT 24
Finished Jul 18 05:58:45 PM PDT 24
Peak memory 201388 kb
Host smart-d43eb57b-f50a-45fa-98c2-1ba945db8256
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410532456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.2410532456
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.661316781
Short name T914
Test name
Test status
Simulation time 527306525 ps
CPU time 1.05 seconds
Started Jul 18 06:00:28 PM PDT 24
Finished Jul 18 06:00:36 PM PDT 24
Peak memory 201448 kb
Host smart-686e4e6c-fb3e-43df-aeb5-6dcbec585dd1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661316781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.661316781
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.1238049533
Short name T824
Test name
Test status
Simulation time 866340783 ps
CPU time 3.74 seconds
Started Jul 18 05:58:26 PM PDT 24
Finished Jul 18 05:58:39 PM PDT 24
Peak memory 201688 kb
Host smart-fcfcea50-3804-4f35-91fd-32683dcf599e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238049533 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alia
sing.1238049533
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.376760189
Short name T106
Test name
Test status
Simulation time 23500647003 ps
CPU time 96.35 seconds
Started Jul 18 05:58:14 PM PDT 24
Finished Jul 18 05:59:57 PM PDT 24
Peak memory 201728 kb
Host smart-50cb9ab6-768b-4669-837f-b6149f33cbf0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376760189 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_b
ash.376760189
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.854803170
Short name T817
Test name
Test status
Simulation time 1305047906 ps
CPU time 1.51 seconds
Started Jul 18 05:58:23 PM PDT 24
Finished Jul 18 05:58:32 PM PDT 24
Peak memory 201476 kb
Host smart-9f22eda1-e80a-40e0-a55b-451d2b01d0f6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854803170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_re
set.854803170
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.4029820079
Short name T883
Test name
Test status
Simulation time 520960639 ps
CPU time 1.96 seconds
Started Jul 18 05:58:13 PM PDT 24
Finished Jul 18 05:58:22 PM PDT 24
Peak memory 201556 kb
Host smart-b3c65213-b95a-4cbb-86f6-b3198686abb4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029820079 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.4029820079
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.1254125126
Short name T56
Test name
Test status
Simulation time 325947482 ps
CPU time 1.3 seconds
Started Jul 18 05:58:13 PM PDT 24
Finished Jul 18 05:58:21 PM PDT 24
Peak memory 201504 kb
Host smart-e1f39fb9-cbb2-432e-9a37-5ac1a556992a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254125126 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.1254125126
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.1736532176
Short name T873
Test name
Test status
Simulation time 380356950 ps
CPU time 1.44 seconds
Started Jul 18 05:58:17 PM PDT 24
Finished Jul 18 05:58:23 PM PDT 24
Peak memory 201492 kb
Host smart-3de79957-5d13-40d6-8b1e-da323aa9015b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736532176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.1736532176
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.3966356919
Short name T874
Test name
Test status
Simulation time 4419113526 ps
CPU time 4.48 seconds
Started Jul 18 05:58:24 PM PDT 24
Finished Jul 18 05:58:36 PM PDT 24
Peak memory 201768 kb
Host smart-3bc7ea81-4cfc-47ff-aaef-48e13bba159d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966356919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_c
trl_same_csr_outstanding.3966356919
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.2127625334
Short name T895
Test name
Test status
Simulation time 339227266 ps
CPU time 1.96 seconds
Started Jul 18 05:58:13 PM PDT 24
Finished Jul 18 05:58:22 PM PDT 24
Peak memory 201800 kb
Host smart-0ad5a6b4-9a27-4a22-a1f4-9bfb4322b95e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127625334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.2127625334
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.2793543190
Short name T913
Test name
Test status
Simulation time 3806907172 ps
CPU time 10.91 seconds
Started Jul 18 05:58:24 PM PDT 24
Finished Jul 18 05:58:43 PM PDT 24
Peak memory 201776 kb
Host smart-c23b66c0-1543-41b5-87f8-ce26c4df7f9c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793543190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_in
tg_err.2793543190
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.587902889
Short name T808
Test name
Test status
Simulation time 491439480 ps
CPU time 1.44 seconds
Started Jul 18 05:58:34 PM PDT 24
Finished Jul 18 05:58:45 PM PDT 24
Peak memory 201440 kb
Host smart-22239c0c-4609-467c-b52e-68497a7b6609
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587902889 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.587902889
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.1442649408
Short name T865
Test name
Test status
Simulation time 307157396 ps
CPU time 1.32 seconds
Started Jul 18 05:58:29 PM PDT 24
Finished Jul 18 05:58:39 PM PDT 24
Peak memory 201392 kb
Host smart-3aff4637-7957-4ca5-b2ab-6fe2e0031e86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442649408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.1442649408
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.1622599057
Short name T891
Test name
Test status
Simulation time 510252056 ps
CPU time 0.82 seconds
Started Jul 18 05:58:35 PM PDT 24
Finished Jul 18 05:58:44 PM PDT 24
Peak memory 201412 kb
Host smart-8af2ee8b-eec9-4414-86ab-959b46276d27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622599057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.1622599057
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.3649734917
Short name T815
Test name
Test status
Simulation time 431349191 ps
CPU time 0.89 seconds
Started Jul 18 05:59:33 PM PDT 24
Finished Jul 18 05:59:48 PM PDT 24
Peak memory 201472 kb
Host smart-afd01de1-9689-4b2e-9dec-1e9af219cc30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649734917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.3649734917
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.2010764574
Short name T917
Test name
Test status
Simulation time 438395530 ps
CPU time 1.7 seconds
Started Jul 18 05:58:36 PM PDT 24
Finished Jul 18 05:58:46 PM PDT 24
Peak memory 201420 kb
Host smart-c23906c7-defc-488b-a0fb-f2cffe87d60c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010764574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.2010764574
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.4186474608
Short name T907
Test name
Test status
Simulation time 496536232 ps
CPU time 1.75 seconds
Started Jul 18 05:58:26 PM PDT 24
Finished Jul 18 05:58:37 PM PDT 24
Peak memory 201472 kb
Host smart-4bbaed11-aeeb-49ee-b428-a25d26de756f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186474608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.4186474608
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.2297121609
Short name T821
Test name
Test status
Simulation time 443074237 ps
CPU time 0.91 seconds
Started Jul 18 05:58:36 PM PDT 24
Finished Jul 18 05:58:45 PM PDT 24
Peak memory 201388 kb
Host smart-966bdb3c-a846-4474-80e8-81e35be3b5c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297121609 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.2297121609
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.2463849103
Short name T843
Test name
Test status
Simulation time 382891492 ps
CPU time 1.44 seconds
Started Jul 18 05:58:34 PM PDT 24
Finished Jul 18 05:58:45 PM PDT 24
Peak memory 201388 kb
Host smart-56bb8bae-8ef7-43c4-9dc7-5490831c9119
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463849103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.2463849103
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.1539633290
Short name T820
Test name
Test status
Simulation time 302669358 ps
CPU time 1.41 seconds
Started Jul 18 05:58:34 PM PDT 24
Finished Jul 18 05:58:44 PM PDT 24
Peak memory 201408 kb
Host smart-57055cf6-b1b0-456f-9286-9cf60034b508
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539633290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.1539633290
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.2858487945
Short name T916
Test name
Test status
Simulation time 343819797 ps
CPU time 0.87 seconds
Started Jul 18 05:58:34 PM PDT 24
Finished Jul 18 05:58:44 PM PDT 24
Peak memory 201408 kb
Host smart-cfbc3996-7ef4-4511-9e16-a284245f2b12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858487945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.2858487945
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.1023633237
Short name T885
Test name
Test status
Simulation time 1317064776 ps
CPU time 6.04 seconds
Started Jul 18 05:58:23 PM PDT 24
Finished Jul 18 05:58:37 PM PDT 24
Peak memory 201644 kb
Host smart-ee68301a-206a-4b8f-adec-4c608d7d1deb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023633237 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alia
sing.1023633237
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.2468029166
Short name T866
Test name
Test status
Simulation time 25980885999 ps
CPU time 82.03 seconds
Started Jul 18 05:58:23 PM PDT 24
Finished Jul 18 05:59:51 PM PDT 24
Peak memory 201756 kb
Host smart-102cb4b3-c1a1-4893-b1dc-93046e5efdbc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468029166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_
bash.2468029166
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.4264798754
Short name T894
Test name
Test status
Simulation time 1200116648 ps
CPU time 1.56 seconds
Started Jul 18 05:58:17 PM PDT 24
Finished Jul 18 05:58:24 PM PDT 24
Peak memory 201452 kb
Host smart-9f3af57d-29b2-4692-a182-7727ea65df8e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264798754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_r
eset.4264798754
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.2873343682
Short name T870
Test name
Test status
Simulation time 466068331 ps
CPU time 1.09 seconds
Started Jul 18 05:58:22 PM PDT 24
Finished Jul 18 05:58:29 PM PDT 24
Peak memory 201612 kb
Host smart-e23c3cab-18e5-4fed-973c-a913749ad746
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873343682 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.2873343682
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.2964090949
Short name T109
Test name
Test status
Simulation time 410369091 ps
CPU time 1.85 seconds
Started Jul 18 05:58:18 PM PDT 24
Finished Jul 18 05:58:25 PM PDT 24
Peak memory 201424 kb
Host smart-66452838-88a3-492e-88b9-c3d86102571a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964090949 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.2964090949
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.2688104306
Short name T804
Test name
Test status
Simulation time 435269498 ps
CPU time 1.24 seconds
Started Jul 18 05:58:22 PM PDT 24
Finished Jul 18 05:58:30 PM PDT 24
Peak memory 201700 kb
Host smart-25cb78f7-07b7-489d-9033-d96f49949709
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688104306 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.2688104306
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.2902231025
Short name T911
Test name
Test status
Simulation time 4150005696 ps
CPU time 3.4 seconds
Started Jul 18 05:58:26 PM PDT 24
Finished Jul 18 05:58:38 PM PDT 24
Peak memory 201768 kb
Host smart-f95b0844-9f45-418a-a3d1-1cad85d1fd10
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902231025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_c
trl_same_csr_outstanding.2902231025
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.545528775
Short name T890
Test name
Test status
Simulation time 318823245 ps
CPU time 2.9 seconds
Started Jul 18 05:58:18 PM PDT 24
Finished Jul 18 05:58:26 PM PDT 24
Peak memory 201816 kb
Host smart-fbe2a212-14f0-4d51-a6f2-c4d03eeadd07
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545528775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.545528775
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.2515051151
Short name T830
Test name
Test status
Simulation time 4277046318 ps
CPU time 11.56 seconds
Started Jul 18 05:58:17 PM PDT 24
Finished Jul 18 05:58:34 PM PDT 24
Peak memory 201764 kb
Host smart-bedf3e1d-2244-429a-acfb-eff46543e48e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515051151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_in
tg_err.2515051151
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.929625422
Short name T849
Test name
Test status
Simulation time 362718182 ps
CPU time 0.82 seconds
Started Jul 18 05:58:34 PM PDT 24
Finished Jul 18 05:58:44 PM PDT 24
Peak memory 201388 kb
Host smart-33adda8c-20b3-4083-9457-47dff0e69552
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929625422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.929625422
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.1820845138
Short name T807
Test name
Test status
Simulation time 383373363 ps
CPU time 0.84 seconds
Started Jul 18 05:58:30 PM PDT 24
Finished Jul 18 05:58:40 PM PDT 24
Peak memory 201444 kb
Host smart-8f95860e-cc09-4453-9269-22c58db365df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820845138 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.1820845138
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.3924346130
Short name T906
Test name
Test status
Simulation time 495751899 ps
CPU time 0.92 seconds
Started Jul 18 05:58:31 PM PDT 24
Finished Jul 18 05:58:41 PM PDT 24
Peak memory 201444 kb
Host smart-73e2e6b8-d9e1-4b1d-acf0-4a9f7760ef51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924346130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.3924346130
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.2033468620
Short name T841
Test name
Test status
Simulation time 404548731 ps
CPU time 0.88 seconds
Started Jul 18 05:58:32 PM PDT 24
Finished Jul 18 05:58:41 PM PDT 24
Peak memory 201464 kb
Host smart-005b6313-1bfd-4262-b6da-e42732c9c86b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033468620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.2033468620
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.3311194634
Short name T806
Test name
Test status
Simulation time 367686490 ps
CPU time 1.55 seconds
Started Jul 18 05:58:38 PM PDT 24
Finished Jul 18 05:58:47 PM PDT 24
Peak memory 201464 kb
Host smart-6c67afca-2f2b-46b1-be6e-dd6379b50729
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311194634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.3311194634
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.1941870833
Short name T825
Test name
Test status
Simulation time 495647642 ps
CPU time 0.82 seconds
Started Jul 18 05:58:37 PM PDT 24
Finished Jul 18 05:58:45 PM PDT 24
Peak memory 201468 kb
Host smart-1cae4ba6-6849-4930-ae69-79871ba5c7c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941870833 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.1941870833
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.941003704
Short name T812
Test name
Test status
Simulation time 358168548 ps
CPU time 1.18 seconds
Started Jul 18 05:58:34 PM PDT 24
Finished Jul 18 05:58:44 PM PDT 24
Peak memory 201412 kb
Host smart-a208713f-d578-4f4d-ac44-61a6a1b6eb7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941003704 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.941003704
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.3165212948
Short name T912
Test name
Test status
Simulation time 439420931 ps
CPU time 1.6 seconds
Started Jul 18 05:58:31 PM PDT 24
Finished Jul 18 05:58:41 PM PDT 24
Peak memory 201444 kb
Host smart-68dc1850-4a03-4d56-a4ba-a7011e49feaf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165212948 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.3165212948
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.1160402594
Short name T818
Test name
Test status
Simulation time 524131724 ps
CPU time 1.83 seconds
Started Jul 18 05:58:38 PM PDT 24
Finished Jul 18 05:58:47 PM PDT 24
Peak memory 201408 kb
Host smart-5ba31be2-2f71-4e59-b889-70a550c13fa8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160402594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.1160402594
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.4041825266
Short name T886
Test name
Test status
Simulation time 319658005 ps
CPU time 1.32 seconds
Started Jul 18 05:58:31 PM PDT 24
Finished Jul 18 05:58:41 PM PDT 24
Peak memory 201448 kb
Host smart-0f57fef8-33aa-4099-a7f0-96944003c008
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041825266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.4041825266
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.4046037552
Short name T877
Test name
Test status
Simulation time 404340962 ps
CPU time 1.79 seconds
Started Jul 18 05:58:23 PM PDT 24
Finished Jul 18 05:58:33 PM PDT 24
Peak memory 201580 kb
Host smart-a4cff564-fc53-46bd-bcb5-b8943a990f76
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046037552 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.4046037552
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.2615046579
Short name T110
Test name
Test status
Simulation time 498135383 ps
CPU time 2.05 seconds
Started Jul 18 05:58:23 PM PDT 24
Finished Jul 18 05:58:32 PM PDT 24
Peak memory 201436 kb
Host smart-9c671ce7-c231-47d1-a4cc-af2d4bd63885
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615046579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.2615046579
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.3019529950
Short name T861
Test name
Test status
Simulation time 454707883 ps
CPU time 1.11 seconds
Started Jul 18 05:58:23 PM PDT 24
Finished Jul 18 05:58:32 PM PDT 24
Peak memory 201428 kb
Host smart-f388ad90-4463-4bd8-ba7f-2e4daf73a116
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019529950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.3019529950
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.399926346
Short name T53
Test name
Test status
Simulation time 4139553459 ps
CPU time 5.64 seconds
Started Jul 18 05:58:22 PM PDT 24
Finished Jul 18 05:58:34 PM PDT 24
Peak memory 201720 kb
Host smart-de898c5a-e604-42df-8584-6b36c8b48888
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399926346 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ct
rl_same_csr_outstanding.399926346
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.4131806020
Short name T846
Test name
Test status
Simulation time 541317552 ps
CPU time 1.78 seconds
Started Jul 18 05:58:19 PM PDT 24
Finished Jul 18 05:58:26 PM PDT 24
Peak memory 201852 kb
Host smart-0e0466d8-f11b-4174-ae64-bc66bc79dff5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131806020 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.4131806020
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.1060595961
Short name T899
Test name
Test status
Simulation time 5429869446 ps
CPU time 2.21 seconds
Started Jul 18 05:58:18 PM PDT 24
Finished Jul 18 05:58:25 PM PDT 24
Peak memory 201812 kb
Host smart-c46aba09-3537-4e2e-9321-1996d5bb5251
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060595961 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_in
tg_err.1060595961
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.1480134083
Short name T881
Test name
Test status
Simulation time 707415129 ps
CPU time 1.4 seconds
Started Jul 18 05:58:23 PM PDT 24
Finished Jul 18 05:58:32 PM PDT 24
Peak memory 201580 kb
Host smart-f08e8fa6-bccc-471b-9986-ab0d4ea5508b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480134083 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.1480134083
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.484522144
Short name T103
Test name
Test status
Simulation time 443743216 ps
CPU time 0.83 seconds
Started Jul 18 05:58:21 PM PDT 24
Finished Jul 18 05:58:28 PM PDT 24
Peak memory 201404 kb
Host smart-098110d4-45a2-4ba9-adb0-52316217dcf8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484522144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.484522144
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.2215894687
Short name T892
Test name
Test status
Simulation time 529877327 ps
CPU time 1.83 seconds
Started Jul 18 05:58:22 PM PDT 24
Finished Jul 18 05:58:30 PM PDT 24
Peak memory 201468 kb
Host smart-7ecaf8f0-f966-4451-90c6-eac934f670dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215894687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.2215894687
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.3931204891
Short name T850
Test name
Test status
Simulation time 2667817977 ps
CPU time 6.1 seconds
Started Jul 18 05:58:25 PM PDT 24
Finished Jul 18 05:58:39 PM PDT 24
Peak memory 201600 kb
Host smart-67931448-f0fd-47eb-9419-42f616382866
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931204891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_c
trl_same_csr_outstanding.3931204891
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.948950981
Short name T70
Test name
Test status
Simulation time 514579598 ps
CPU time 3.3 seconds
Started Jul 18 05:58:22 PM PDT 24
Finished Jul 18 05:58:31 PM PDT 24
Peak memory 217664 kb
Host smart-31f38c31-4b75-41da-bdce-12a9e206777a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948950981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.948950981
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.1352356992
Short name T869
Test name
Test status
Simulation time 7939807913 ps
CPU time 6.82 seconds
Started Jul 18 05:58:21 PM PDT 24
Finished Jul 18 05:58:34 PM PDT 24
Peak memory 201804 kb
Host smart-11065a4d-59b2-4ab2-b49c-8079c23b20d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352356992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_in
tg_err.1352356992
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.1940561905
Short name T64
Test name
Test status
Simulation time 603428881 ps
CPU time 1.34 seconds
Started Jul 18 05:58:14 PM PDT 24
Finished Jul 18 05:58:22 PM PDT 24
Peak memory 201556 kb
Host smart-fe8e5352-57dc-4d32-953c-1724357b1914
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940561905 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.1940561905
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.2958725408
Short name T884
Test name
Test status
Simulation time 352201910 ps
CPU time 0.99 seconds
Started Jul 18 05:58:22 PM PDT 24
Finished Jul 18 05:58:29 PM PDT 24
Peak memory 201324 kb
Host smart-2b32041c-ee48-4c87-98ee-fa235e255923
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958725408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.2958725408
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.1564135845
Short name T920
Test name
Test status
Simulation time 529551979 ps
CPU time 0.92 seconds
Started Jul 18 05:58:22 PM PDT 24
Finished Jul 18 05:58:29 PM PDT 24
Peak memory 201396 kb
Host smart-584258a3-2183-45b3-93d6-742bec4f3220
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564135845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.1564135845
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.1881874845
Short name T876
Test name
Test status
Simulation time 2332542145 ps
CPU time 2.06 seconds
Started Jul 18 05:58:25 PM PDT 24
Finished Jul 18 05:58:35 PM PDT 24
Peak memory 201524 kb
Host smart-8e10e817-978b-430b-8ce5-9144ce876dbc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881874845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_c
trl_same_csr_outstanding.1881874845
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.3815594613
Short name T905
Test name
Test status
Simulation time 642940808 ps
CPU time 1.36 seconds
Started Jul 18 05:58:24 PM PDT 24
Finished Jul 18 05:58:32 PM PDT 24
Peak memory 201700 kb
Host smart-92d2740e-5a23-420e-b835-a7019e5c73d8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815594613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.3815594613
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.1051549008
Short name T59
Test name
Test status
Simulation time 8004829090 ps
CPU time 18.66 seconds
Started Jul 18 05:58:25 PM PDT 24
Finished Jul 18 05:58:51 PM PDT 24
Peak memory 201716 kb
Host smart-9b7c3819-e700-4c70-bdea-e9a47f3857cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051549008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_in
tg_err.1051549008
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.1374281441
Short name T840
Test name
Test status
Simulation time 494070336 ps
CPU time 1.72 seconds
Started Jul 18 05:58:23 PM PDT 24
Finished Jul 18 05:58:31 PM PDT 24
Peak memory 201556 kb
Host smart-08b804f3-6677-4500-866f-7ff3beb701c6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374281441 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.1374281441
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.4031939615
Short name T112
Test name
Test status
Simulation time 334575783 ps
CPU time 1.48 seconds
Started Jul 18 05:58:28 PM PDT 24
Finished Jul 18 05:58:39 PM PDT 24
Peak memory 201384 kb
Host smart-098290c2-4581-4f85-8fb7-9156c805b5da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031939615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.4031939615
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.3965383001
Short name T867
Test name
Test status
Simulation time 471566433 ps
CPU time 1.61 seconds
Started Jul 18 05:58:22 PM PDT 24
Finished Jul 18 05:58:29 PM PDT 24
Peak memory 201276 kb
Host smart-1c84a3a7-a448-4789-89d2-50451047bd17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965383001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.3965383001
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.2029539402
Short name T898
Test name
Test status
Simulation time 3603195472 ps
CPU time 9.47 seconds
Started Jul 18 05:58:28 PM PDT 24
Finished Jul 18 05:58:47 PM PDT 24
Peak memory 201736 kb
Host smart-9d527aca-4577-440b-9b4e-06af6731c57b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029539402 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_c
trl_same_csr_outstanding.2029539402
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.1873891428
Short name T839
Test name
Test status
Simulation time 1841918060 ps
CPU time 2.02 seconds
Started Jul 18 05:58:21 PM PDT 24
Finished Jul 18 05:58:29 PM PDT 24
Peak memory 201716 kb
Host smart-e12e748a-97be-4019-9378-680b76f61e66
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873891428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.1873891428
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.3753284911
Short name T68
Test name
Test status
Simulation time 4321481024 ps
CPU time 3.81 seconds
Started Jul 18 05:58:27 PM PDT 24
Finished Jul 18 05:58:40 PM PDT 24
Peak memory 201692 kb
Host smart-5609c50a-1b52-463a-b06e-2dbca318c629
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753284911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_in
tg_err.3753284911
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.564531412
Short name T845
Test name
Test status
Simulation time 665767327 ps
CPU time 1.38 seconds
Started Jul 18 05:58:24 PM PDT 24
Finished Jul 18 05:58:33 PM PDT 24
Peak memory 201552 kb
Host smart-d436aa8e-37d5-4fa6-8377-cee7aaf65921
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564531412 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.564531412
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.375606729
Short name T113
Test name
Test status
Simulation time 439540867 ps
CPU time 1.64 seconds
Started Jul 18 05:58:24 PM PDT 24
Finished Jul 18 05:58:34 PM PDT 24
Peak memory 201376 kb
Host smart-6e406a4e-96c3-4976-90d5-6e5ec4186b68
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375606729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.375606729
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.566695916
Short name T828
Test name
Test status
Simulation time 490941604 ps
CPU time 1.19 seconds
Started Jul 18 05:58:26 PM PDT 24
Finished Jul 18 05:58:36 PM PDT 24
Peak memory 201372 kb
Host smart-aca124d8-b26d-4103-97d5-4aee9890efef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566695916 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.566695916
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.2071908236
Short name T114
Test name
Test status
Simulation time 2035855090 ps
CPU time 3.09 seconds
Started Jul 18 05:58:24 PM PDT 24
Finished Jul 18 05:58:34 PM PDT 24
Peak memory 201444 kb
Host smart-684b8a0c-233f-4669-a901-1175c65879ba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071908236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_c
trl_same_csr_outstanding.2071908236
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.997602900
Short name T852
Test name
Test status
Simulation time 448339903 ps
CPU time 1.82 seconds
Started Jul 18 05:58:30 PM PDT 24
Finished Jul 18 05:58:40 PM PDT 24
Peak memory 201776 kb
Host smart-675ba132-a63b-4997-9c99-802e66c5bf99
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997602900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.997602900
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.4122597072
Short name T918
Test name
Test status
Simulation time 8185977593 ps
CPU time 20.85 seconds
Started Jul 18 05:58:27 PM PDT 24
Finished Jul 18 05:58:57 PM PDT 24
Peak memory 201716 kb
Host smart-f02628c4-8634-4e6b-bba5-c0f6617e7dc6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122597072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_in
tg_err.4122597072
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.2264545959
Short name T378
Test name
Test status
Simulation time 427106955 ps
CPU time 1.11 seconds
Started Jul 18 06:31:43 PM PDT 24
Finished Jul 18 06:31:48 PM PDT 24
Peak memory 201536 kb
Host smart-a67c72a9-b013-4fa6-8e52-f992d41f31cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264545959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.2264545959
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.3696796745
Short name T524
Test name
Test status
Simulation time 326727993714 ps
CPU time 141.42 seconds
Started Jul 18 06:31:41 PM PDT 24
Finished Jul 18 06:34:04 PM PDT 24
Peak memory 201808 kb
Host smart-eabd5cab-ff56-465a-aeae-098cd6fd3696
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696796745 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrup
t_fixed.3696796745
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.2921351679
Short name T166
Test name
Test status
Simulation time 323467281954 ps
CPU time 170.4 seconds
Started Jul 18 06:31:39 PM PDT 24
Finished Jul 18 06:34:30 PM PDT 24
Peak memory 201736 kb
Host smart-96febb1d-836f-48df-9799-60dd539eb4dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921351679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.2921351679
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.4163844551
Short name T137
Test name
Test status
Simulation time 487132801635 ps
CPU time 274.84 seconds
Started Jul 18 06:31:48 PM PDT 24
Finished Jul 18 06:36:27 PM PDT 24
Peak memory 201680 kb
Host smart-91d5d691-6348-4692-bd2d-177a183ed779
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163844551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixe
d.4163844551
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.326635504
Short name T42
Test name
Test status
Simulation time 614924632191 ps
CPU time 1381.91 seconds
Started Jul 18 06:31:43 PM PDT 24
Finished Jul 18 06:54:49 PM PDT 24
Peak memory 201724 kb
Host smart-ca22c82c-cb38-4640-b077-154d75506917
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326635504 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.a
dc_ctrl_filters_wakeup_fixed.326635504
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.1525435766
Short name T783
Test name
Test status
Simulation time 80773144281 ps
CPU time 292.49 seconds
Started Jul 18 06:31:45 PM PDT 24
Finished Jul 18 06:36:42 PM PDT 24
Peak memory 202192 kb
Host smart-4b4cc60d-1263-4b9e-8343-5217ba0459cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525435766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.1525435766
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.120968054
Short name T598
Test name
Test status
Simulation time 43048649992 ps
CPU time 25.57 seconds
Started Jul 18 06:31:45 PM PDT 24
Finished Jul 18 06:32:15 PM PDT 24
Peak memory 201580 kb
Host smart-6e8b48d4-3120-4bea-b835-378840a9de84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120968054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.120968054
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.2780593465
Short name T412
Test name
Test status
Simulation time 4441862980 ps
CPU time 5.71 seconds
Started Jul 18 06:31:43 PM PDT 24
Finished Jul 18 06:31:51 PM PDT 24
Peak memory 201688 kb
Host smart-85122278-0767-4172-b4d4-bffe2f3d2022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780593465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.2780593465
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.2533380196
Short name T66
Test name
Test status
Simulation time 7913686152 ps
CPU time 9.45 seconds
Started Jul 18 06:31:42 PM PDT 24
Finished Jul 18 06:31:53 PM PDT 24
Peak memory 217524 kb
Host smart-f397944c-2158-4707-a7b6-c939ef7bc9a9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533380196 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.2533380196
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.1194340431
Short name T613
Test name
Test status
Simulation time 6023162623 ps
CPU time 2.94 seconds
Started Jul 18 06:31:43 PM PDT 24
Finished Jul 18 06:31:49 PM PDT 24
Peak memory 201792 kb
Host smart-08f7c9a4-626d-429e-8169-7d9849581ef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194340431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.1194340431
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.722719162
Short name T196
Test name
Test status
Simulation time 490894796274 ps
CPU time 1012.43 seconds
Started Jul 18 06:31:42 PM PDT 24
Finished Jul 18 06:48:36 PM PDT 24
Peak memory 210312 kb
Host smart-d9336b04-79d7-4237-86f7-ed9c5fbf8c20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722719162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.722719162
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.4222632392
Short name T193
Test name
Test status
Simulation time 312261426525 ps
CPU time 246.07 seconds
Started Jul 18 06:31:43 PM PDT 24
Finished Jul 18 06:35:53 PM PDT 24
Peak memory 210500 kb
Host smart-a72ba133-0470-42be-a47f-6c99558fbcfe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222632392 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.4222632392
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.3836025690
Short name T635
Test name
Test status
Simulation time 530389240 ps
CPU time 1.22 seconds
Started Jul 18 06:31:46 PM PDT 24
Finished Jul 18 06:31:52 PM PDT 24
Peak memory 201512 kb
Host smart-e6f2f570-a6df-4996-a90d-e4e35b613246
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836025690 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.3836025690
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.2158465546
Short name T299
Test name
Test status
Simulation time 175371310656 ps
CPU time 190.45 seconds
Started Jul 18 06:31:40 PM PDT 24
Finished Jul 18 06:34:51 PM PDT 24
Peak memory 201728 kb
Host smart-61f8a362-af10-4342-8e31-42fc57985cb0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158465546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gati
ng.2158465546
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.2712201155
Short name T568
Test name
Test status
Simulation time 162289446845 ps
CPU time 109.12 seconds
Started Jul 18 06:31:43 PM PDT 24
Finished Jul 18 06:33:36 PM PDT 24
Peak memory 201744 kb
Host smart-eea8c91c-1b61-4e32-9caa-4c4fd4cd9630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712201155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.2712201155
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.788288020
Short name T735
Test name
Test status
Simulation time 497935405706 ps
CPU time 626.49 seconds
Started Jul 18 06:31:41 PM PDT 24
Finished Jul 18 06:42:09 PM PDT 24
Peak memory 201720 kb
Host smart-fdf3ddf5-b22e-4c26-a035-c712d4918b56
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=788288020 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt
_fixed.788288020
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.1468221395
Short name T145
Test name
Test status
Simulation time 486457831685 ps
CPU time 292.54 seconds
Started Jul 18 06:31:45 PM PDT 24
Finished Jul 18 06:36:42 PM PDT 24
Peak memory 201796 kb
Host smart-e54e5d05-d29e-478a-87bb-6532e31b9bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468221395 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.1468221395
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.2765347798
Short name T523
Test name
Test status
Simulation time 163937236342 ps
CPU time 194.58 seconds
Started Jul 18 06:31:45 PM PDT 24
Finished Jul 18 06:35:04 PM PDT 24
Peak memory 201684 kb
Host smart-bd1159f5-6476-430f-ad22-0cf00cf847d8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765347798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixe
d.2765347798
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.562919191
Short name T580
Test name
Test status
Simulation time 176435693933 ps
CPU time 393.59 seconds
Started Jul 18 06:31:43 PM PDT 24
Finished Jul 18 06:38:21 PM PDT 24
Peak memory 201812 kb
Host smart-d5267b6e-85d5-4818-b605-343394f733ef
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562919191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_w
akeup.562919191
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.3708929632
Short name T423
Test name
Test status
Simulation time 199025057927 ps
CPU time 159.31 seconds
Started Jul 18 06:31:42 PM PDT 24
Finished Jul 18 06:34:25 PM PDT 24
Peak memory 201684 kb
Host smart-2f52cdd0-d371-4068-b1ec-7fc169274a4d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708929632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
adc_ctrl_filters_wakeup_fixed.3708929632
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.33772630
Short name T28
Test name
Test status
Simulation time 129115148245 ps
CPU time 647.02 seconds
Started Jul 18 06:31:45 PM PDT 24
Finished Jul 18 06:42:37 PM PDT 24
Peak memory 202124 kb
Host smart-55f4e137-9d3b-4c6c-b96b-c9d7cc4470c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33772630 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.33772630
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.2321115228
Short name T467
Test name
Test status
Simulation time 44129956829 ps
CPU time 32.77 seconds
Started Jul 18 06:31:39 PM PDT 24
Finished Jul 18 06:32:13 PM PDT 24
Peak memory 201608 kb
Host smart-1ce69a02-92ba-4f6a-ac80-fb4de17db032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321115228 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.2321115228
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.3751322338
Short name T647
Test name
Test status
Simulation time 3912739881 ps
CPU time 8.77 seconds
Started Jul 18 06:31:43 PM PDT 24
Finished Jul 18 06:31:56 PM PDT 24
Peak memory 201616 kb
Host smart-7b5ea582-d452-4597-aa58-e9e44f15aee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751322338 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.3751322338
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.2023466715
Short name T67
Test name
Test status
Simulation time 7889740351 ps
CPU time 5.84 seconds
Started Jul 18 06:31:44 PM PDT 24
Finished Jul 18 06:31:54 PM PDT 24
Peak memory 217336 kb
Host smart-35464b3c-32d0-4d78-9737-756a9178cbfe
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023466715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.2023466715
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.3749461925
Short name T430
Test name
Test status
Simulation time 5747912083 ps
CPU time 14.17 seconds
Started Jul 18 06:31:43 PM PDT 24
Finished Jul 18 06:32:01 PM PDT 24
Peak memory 201624 kb
Host smart-cdc602b9-cbd5-461d-9419-08acdb1f59e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749461925 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.3749461925
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.3403868628
Short name T640
Test name
Test status
Simulation time 304516882976 ps
CPU time 480.45 seconds
Started Jul 18 06:31:44 PM PDT 24
Finished Jul 18 06:39:49 PM PDT 24
Peak memory 212348 kb
Host smart-3960bb3f-a683-406b-b75d-fd5704313f18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403868628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.
3403868628
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.2582905697
Short name T298
Test name
Test status
Simulation time 30168464868 ps
CPU time 36.43 seconds
Started Jul 18 06:31:48 PM PDT 24
Finished Jul 18 06:32:28 PM PDT 24
Peak memory 210024 kb
Host smart-eeb20bc0-410c-4042-80b4-3e5b3c7ad4ce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582905697 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.2582905697
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.581094203
Short name T569
Test name
Test status
Simulation time 166293306882 ps
CPU time 401.35 seconds
Started Jul 18 06:32:12 PM PDT 24
Finished Jul 18 06:38:58 PM PDT 24
Peak memory 201584 kb
Host smart-752aacc4-4a96-40be-bf6d-45e59876571e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581094203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gati
ng.581094203
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.1788948057
Short name T245
Test name
Test status
Simulation time 166377505004 ps
CPU time 93.3 seconds
Started Jul 18 06:32:12 PM PDT 24
Finished Jul 18 06:33:50 PM PDT 24
Peak memory 201492 kb
Host smart-ae0d4482-0490-4f5a-a31a-56bc91def3c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788948057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.1788948057
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.4177493452
Short name T672
Test name
Test status
Simulation time 331705009556 ps
CPU time 206.88 seconds
Started Jul 18 06:32:12 PM PDT 24
Finished Jul 18 06:35:43 PM PDT 24
Peak memory 201732 kb
Host smart-57b78aad-8ad9-4f57-b7ee-bf71847fad8a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177493452 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interru
pt_fixed.4177493452
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.1705153591
Short name T229
Test name
Test status
Simulation time 319571678120 ps
CPU time 370.5 seconds
Started Jul 18 06:32:12 PM PDT 24
Finished Jul 18 06:38:27 PM PDT 24
Peak memory 201808 kb
Host smart-fa853660-22ae-468e-80e9-8d98065bd3d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705153591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.1705153591
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.1049214901
Short name T532
Test name
Test status
Simulation time 324983663431 ps
CPU time 734.76 seconds
Started Jul 18 06:32:12 PM PDT 24
Finished Jul 18 06:44:32 PM PDT 24
Peak memory 201740 kb
Host smart-0a23ea46-1998-4b02-b036-0be2fee037a2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049214901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fix
ed.1049214901
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.4104591490
Short name T268
Test name
Test status
Simulation time 352682449424 ps
CPU time 437.21 seconds
Started Jul 18 06:32:06 PM PDT 24
Finished Jul 18 06:39:28 PM PDT 24
Peak memory 201832 kb
Host smart-2758fd99-ae59-4d09-9a03-355d39c2efa1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104591490 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters
_wakeup.4104591490
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.3810055323
Short name T399
Test name
Test status
Simulation time 596973812336 ps
CPU time 1360.69 seconds
Started Jul 18 06:32:12 PM PDT 24
Finished Jul 18 06:54:58 PM PDT 24
Peak memory 201740 kb
Host smart-3b9a8baf-65f6-465c-b84a-28d9a2380971
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810055323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.adc_ctrl_filters_wakeup_fixed.3810055323
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.3169561795
Short name T605
Test name
Test status
Simulation time 117578851242 ps
CPU time 568.33 seconds
Started Jul 18 06:32:09 PM PDT 24
Finished Jul 18 06:41:43 PM PDT 24
Peak memory 202168 kb
Host smart-7e86fa48-3a07-4568-a6c9-540acbe8d009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169561795 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.3169561795
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.1816456490
Short name T158
Test name
Test status
Simulation time 29255894820 ps
CPU time 17.31 seconds
Started Jul 18 06:32:05 PM PDT 24
Finished Jul 18 06:32:26 PM PDT 24
Peak memory 201612 kb
Host smart-67c479ac-4b01-41bd-9076-9a790cbbc31c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816456490 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.1816456490
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.3233134486
Short name T36
Test name
Test status
Simulation time 4434302634 ps
CPU time 11.99 seconds
Started Jul 18 06:32:07 PM PDT 24
Finished Jul 18 06:32:24 PM PDT 24
Peak memory 201596 kb
Host smart-6b4689cf-754a-4e4f-a6aa-ed32af738946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233134486 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.3233134486
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.456523309
Short name T521
Test name
Test status
Simulation time 5928340838 ps
CPU time 4.41 seconds
Started Jul 18 06:32:12 PM PDT 24
Finished Jul 18 06:32:21 PM PDT 24
Peak memory 201604 kb
Host smart-972df5b3-dab1-4888-8b07-05089ce0ce4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456523309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.456523309
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.1027619709
Short name T445
Test name
Test status
Simulation time 221388716829 ps
CPU time 38.5 seconds
Started Jul 18 06:32:08 PM PDT 24
Finished Jul 18 06:32:52 PM PDT 24
Peak memory 201812 kb
Host smart-200a1ec8-6b24-48ea-b2ed-a17f521c4153
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027619709 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all
.1027619709
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.3002528529
Short name T768
Test name
Test status
Simulation time 323693876 ps
CPU time 1.34 seconds
Started Jul 18 06:32:06 PM PDT 24
Finished Jul 18 06:32:13 PM PDT 24
Peak memory 201476 kb
Host smart-401d3aa4-8f68-45e1-880f-679cd19118b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002528529 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.3002528529
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.3707498239
Short name T617
Test name
Test status
Simulation time 341374644465 ps
CPU time 420.47 seconds
Started Jul 18 06:32:07 PM PDT 24
Finished Jul 18 06:39:13 PM PDT 24
Peak memory 201756 kb
Host smart-93c410cb-4653-4346-9248-dd82d22dc930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707498239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.3707498239
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.1683363745
Short name T737
Test name
Test status
Simulation time 494751194458 ps
CPU time 196.93 seconds
Started Jul 18 06:32:10 PM PDT 24
Finished Jul 18 06:35:32 PM PDT 24
Peak memory 201740 kb
Host smart-89986a25-48c4-4921-a052-2cb5493517f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683363745 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.1683363745
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.248287696
Short name T542
Test name
Test status
Simulation time 318779385844 ps
CPU time 181.17 seconds
Started Jul 18 06:32:06 PM PDT 24
Finished Jul 18 06:35:13 PM PDT 24
Peak memory 201720 kb
Host smart-590161fa-5a19-4737-9b88-8a277ff1a70a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=248287696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrup
t_fixed.248287696
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.2388166081
Short name T11
Test name
Test status
Simulation time 337649551879 ps
CPU time 744.59 seconds
Started Jul 18 06:32:09 PM PDT 24
Finished Jul 18 06:44:39 PM PDT 24
Peak memory 201748 kb
Host smart-6d32df59-24e9-4f4b-9991-5f150077036c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388166081 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fix
ed.2388166081
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.1634472779
Short name T656
Test name
Test status
Simulation time 389367136444 ps
CPU time 851.09 seconds
Started Jul 18 06:32:09 PM PDT 24
Finished Jul 18 06:46:26 PM PDT 24
Peak memory 201744 kb
Host smart-1eb45b0b-7a26-4b16-af62-4dfa2ad4d9a7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634472779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters
_wakeup.1634472779
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.3267878090
Short name T408
Test name
Test status
Simulation time 205392499174 ps
CPU time 50.6 seconds
Started Jul 18 06:32:05 PM PDT 24
Finished Jul 18 06:32:59 PM PDT 24
Peak memory 201776 kb
Host smart-3cba45b5-2b48-4c74-a161-cad0f06d42e1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267878090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.adc_ctrl_filters_wakeup_fixed.3267878090
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.4013138360
Short name T393
Test name
Test status
Simulation time 30331409381 ps
CPU time 34.79 seconds
Started Jul 18 06:32:05 PM PDT 24
Finished Jul 18 06:32:45 PM PDT 24
Peak memory 201644 kb
Host smart-83000b3c-95d8-4c8e-85ba-ae05702518cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013138360 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.4013138360
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.2213354685
Short name T396
Test name
Test status
Simulation time 4003271494 ps
CPU time 2.82 seconds
Started Jul 18 06:32:06 PM PDT 24
Finished Jul 18 06:32:14 PM PDT 24
Peak memory 201256 kb
Host smart-ce24329c-441e-452f-9eb9-e7eada23b373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213354685 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.2213354685
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.3183553187
Short name T782
Test name
Test status
Simulation time 6118041751 ps
CPU time 3.37 seconds
Started Jul 18 06:32:08 PM PDT 24
Finished Jul 18 06:32:17 PM PDT 24
Peak memory 201632 kb
Host smart-e9a9a1ec-e6cf-4975-b3f0-15ac80297f17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183553187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.3183553187
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.451579551
Short name T323
Test name
Test status
Simulation time 499132082153 ps
CPU time 500.1 seconds
Started Jul 18 06:32:06 PM PDT 24
Finished Jul 18 06:40:32 PM PDT 24
Peak memory 201728 kb
Host smart-781fb72b-63bb-49f6-9f88-1f428ba484da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451579551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all.
451579551
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.705319516
Short name T190
Test name
Test status
Simulation time 77984339124 ps
CPU time 124.52 seconds
Started Jul 18 06:32:05 PM PDT 24
Finished Jul 18 06:34:14 PM PDT 24
Peak memory 210156 kb
Host smart-72bde5b8-2d49-44d9-a1e5-6a2428caf0a6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705319516 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.705319516
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.3814891857
Short name T512
Test name
Test status
Simulation time 431360720 ps
CPU time 0.87 seconds
Started Jul 18 06:32:25 PM PDT 24
Finished Jul 18 06:32:28 PM PDT 24
Peak memory 201544 kb
Host smart-4b3d1991-7923-4463-abfe-96889b5098e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814891857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.3814891857
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.2645663955
Short name T508
Test name
Test status
Simulation time 165461378645 ps
CPU time 49.89 seconds
Started Jul 18 06:32:06 PM PDT 24
Finished Jul 18 06:33:01 PM PDT 24
Peak memory 201820 kb
Host smart-e86611ad-f6ee-48bd-96d2-63ecd57471fc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645663955 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gat
ing.2645663955
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.3154291103
Short name T206
Test name
Test status
Simulation time 490474195238 ps
CPU time 1084.46 seconds
Started Jul 18 06:32:04 PM PDT 24
Finished Jul 18 06:50:12 PM PDT 24
Peak memory 201748 kb
Host smart-b8a8dd08-0870-4579-a4be-2718fe5411cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154291103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.3154291103
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.2162987787
Short name T411
Test name
Test status
Simulation time 321541984542 ps
CPU time 375.17 seconds
Started Jul 18 06:32:08 PM PDT 24
Finished Jul 18 06:38:29 PM PDT 24
Peak memory 201684 kb
Host smart-5a35d435-050a-4c56-8170-285e49a4dd18
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162987787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interru
pt_fixed.2162987787
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.1626330037
Short name T185
Test name
Test status
Simulation time 493616958844 ps
CPU time 321.7 seconds
Started Jul 18 06:32:08 PM PDT 24
Finished Jul 18 06:37:35 PM PDT 24
Peak memory 201704 kb
Host smart-ea10ff52-33f1-4790-ac04-1e718435c13b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626330037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.1626330037
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.2086773703
Short name T173
Test name
Test status
Simulation time 161115311934 ps
CPU time 358.78 seconds
Started Jul 18 06:32:08 PM PDT 24
Finished Jul 18 06:38:12 PM PDT 24
Peak memory 201700 kb
Host smart-4a92e453-78ab-482b-9621-7240b5e398d7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086773703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fix
ed.2086773703
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.73995659
Short name T305
Test name
Test status
Simulation time 182624827852 ps
CPU time 90.3 seconds
Started Jul 18 06:32:06 PM PDT 24
Finished Jul 18 06:33:42 PM PDT 24
Peak memory 201756 kb
Host smart-6eca87b6-f647-4869-8b4e-fd08ee7dab81
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73995659 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_w
akeup.73995659
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.3655308882
Short name T698
Test name
Test status
Simulation time 390692203587 ps
CPU time 76.95 seconds
Started Jul 18 06:32:12 PM PDT 24
Finished Jul 18 06:33:33 PM PDT 24
Peak memory 201740 kb
Host smart-b2a7b178-1151-4a1f-8f82-59d89763c775
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655308882 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.adc_ctrl_filters_wakeup_fixed.3655308882
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.1510899161
Short name T355
Test name
Test status
Simulation time 91394797453 ps
CPU time 410.09 seconds
Started Jul 18 06:32:08 PM PDT 24
Finished Jul 18 06:39:03 PM PDT 24
Peak memory 202084 kb
Host smart-4bc972c1-0398-4247-af39-99f8ec0d690d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510899161 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.1510899161
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.592408029
Short name T125
Test name
Test status
Simulation time 25002598083 ps
CPU time 30.23 seconds
Started Jul 18 06:32:12 PM PDT 24
Finished Jul 18 06:32:47 PM PDT 24
Peak memory 201572 kb
Host smart-de8c64f9-c4f2-48a8-897b-ae93e58b9343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592408029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.592408029
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.517351726
Short name T175
Test name
Test status
Simulation time 5131391591 ps
CPU time 12.54 seconds
Started Jul 18 06:32:07 PM PDT 24
Finished Jul 18 06:32:25 PM PDT 24
Peak memory 201516 kb
Host smart-c0f6faad-b028-4938-a452-1977a2b56e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517351726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.517351726
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.2301003937
Short name T622
Test name
Test status
Simulation time 5953165815 ps
CPU time 13.67 seconds
Started Jul 18 06:32:07 PM PDT 24
Finished Jul 18 06:32:26 PM PDT 24
Peak memory 201584 kb
Host smart-b9a69cc6-5cfb-42ea-b357-af068b0a7a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301003937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.2301003937
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.560228450
Short name T304
Test name
Test status
Simulation time 334062562422 ps
CPU time 115.57 seconds
Started Jul 18 06:32:07 PM PDT 24
Finished Jul 18 06:34:08 PM PDT 24
Peak memory 201736 kb
Host smart-593c088e-951a-4dd0-8728-685e6c023191
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560228450 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all.
560228450
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.1877423036
Short name T704
Test name
Test status
Simulation time 344744850112 ps
CPU time 165.94 seconds
Started Jul 18 06:32:12 PM PDT 24
Finished Jul 18 06:35:03 PM PDT 24
Peak memory 210128 kb
Host smart-16d3c3f3-49be-498e-a7e3-ecfa22ed63dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877423036 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.1877423036
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.1514766878
Short name T763
Test name
Test status
Simulation time 369451321 ps
CPU time 0.93 seconds
Started Jul 18 06:32:20 PM PDT 24
Finished Jul 18 06:32:23 PM PDT 24
Peak memory 201556 kb
Host smart-aded8d93-a343-46f7-bcf0-b340139339b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514766878 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.1514766878
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.4262440047
Short name T340
Test name
Test status
Simulation time 520744427561 ps
CPU time 451.43 seconds
Started Jul 18 06:32:27 PM PDT 24
Finished Jul 18 06:40:01 PM PDT 24
Peak memory 201740 kb
Host smart-8a49ed15-e40a-4031-a071-89c1df7eca0d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262440047 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gat
ing.4262440047
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.3808994033
Short name T394
Test name
Test status
Simulation time 496462233865 ps
CPU time 326.16 seconds
Started Jul 18 06:32:25 PM PDT 24
Finished Jul 18 06:37:53 PM PDT 24
Peak memory 201744 kb
Host smart-b13df2f8-0456-42b8-a2eb-caf5df11b72e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808994033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interru
pt_fixed.3808994033
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.1512953256
Short name T328
Test name
Test status
Simulation time 332165338757 ps
CPU time 538.27 seconds
Started Jul 18 06:32:22 PM PDT 24
Finished Jul 18 06:41:22 PM PDT 24
Peak memory 201744 kb
Host smart-65b38e56-89cf-4644-abee-5f23ae0246f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512953256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.1512953256
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.3429738423
Short name T390
Test name
Test status
Simulation time 326733319132 ps
CPU time 770.89 seconds
Started Jul 18 06:32:27 PM PDT 24
Finished Jul 18 06:45:20 PM PDT 24
Peak memory 201716 kb
Host smart-b2738d14-d61e-4ce3-813c-72b324b24c4a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429738423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fix
ed.3429738423
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.3954602289
Short name T233
Test name
Test status
Simulation time 191485113656 ps
CPU time 88.84 seconds
Started Jul 18 06:32:25 PM PDT 24
Finished Jul 18 06:33:55 PM PDT 24
Peak memory 201756 kb
Host smart-67183c12-c98b-4358-9384-1c6147a6050c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954602289 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters
_wakeup.3954602289
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.4169715007
Short name T454
Test name
Test status
Simulation time 392702713963 ps
CPU time 868 seconds
Started Jul 18 06:32:33 PM PDT 24
Finished Jul 18 06:47:04 PM PDT 24
Peak memory 201768 kb
Host smart-c42ab967-767d-4c93-b993-0828d1329fcd
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169715007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.adc_ctrl_filters_wakeup_fixed.4169715007
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.3364717412
Short name T525
Test name
Test status
Simulation time 22791665401 ps
CPU time 4.51 seconds
Started Jul 18 06:32:28 PM PDT 24
Finished Jul 18 06:32:36 PM PDT 24
Peak memory 201548 kb
Host smart-e0b80789-7163-46f0-88cf-1f42be4f6307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364717412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.3364717412
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.1665998347
Short name T557
Test name
Test status
Simulation time 3691223971 ps
CPU time 8.47 seconds
Started Jul 18 06:32:28 PM PDT 24
Finished Jul 18 06:32:39 PM PDT 24
Peak memory 201560 kb
Host smart-941a07f7-ffd0-415a-967c-61550a575e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665998347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.1665998347
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.1886968814
Short name T626
Test name
Test status
Simulation time 6198830154 ps
CPU time 3.97 seconds
Started Jul 18 06:32:32 PM PDT 24
Finished Jul 18 06:32:39 PM PDT 24
Peak memory 201576 kb
Host smart-057ec9ee-fe6e-41a4-946b-3bc435ac70dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886968814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.1886968814
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.3839255887
Short name T497
Test name
Test status
Simulation time 6727205390 ps
CPU time 16.39 seconds
Started Jul 18 06:32:29 PM PDT 24
Finished Jul 18 06:32:48 PM PDT 24
Peak memory 201604 kb
Host smart-a49a8b9e-4478-4e9f-b8fd-39812afe2b51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839255887 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all
.3839255887
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.1961724212
Short name T38
Test name
Test status
Simulation time 129213042191 ps
CPU time 39.71 seconds
Started Jul 18 06:32:28 PM PDT 24
Finished Jul 18 06:33:11 PM PDT 24
Peak memory 210032 kb
Host smart-e8e95269-036a-4514-98ed-2a5620f104d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961724212 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.1961724212
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.3313751003
Short name T597
Test name
Test status
Simulation time 369673573 ps
CPU time 0.86 seconds
Started Jul 18 06:32:28 PM PDT 24
Finished Jul 18 06:32:31 PM PDT 24
Peak memory 201548 kb
Host smart-bda4fd8a-ce40-47fc-b308-2c2fd9eac8d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313751003 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.3313751003
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.3698729868
Short name T311
Test name
Test status
Simulation time 505841639055 ps
CPU time 990.69 seconds
Started Jul 18 06:32:28 PM PDT 24
Finished Jul 18 06:49:01 PM PDT 24
Peak memory 201748 kb
Host smart-72935ffa-d485-4b13-b3a4-e2bd53e9073c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698729868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gat
ing.3698729868
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.728528797
Short name T538
Test name
Test status
Simulation time 164076667758 ps
CPU time 384.81 seconds
Started Jul 18 06:32:32 PM PDT 24
Finished Jul 18 06:39:00 PM PDT 24
Peak memory 201716 kb
Host smart-8e8bc9c7-fcc5-44eb-9a69-dce7cfd833b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728528797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.728528797
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.2882755818
Short name T641
Test name
Test status
Simulation time 168903708144 ps
CPU time 226.34 seconds
Started Jul 18 06:32:24 PM PDT 24
Finished Jul 18 06:36:12 PM PDT 24
Peak memory 201812 kb
Host smart-4cb78363-a6df-49f0-813a-cacba6268beb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882755818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interru
pt_fixed.2882755818
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.3498186975
Short name T767
Test name
Test status
Simulation time 322550861510 ps
CPU time 394.6 seconds
Started Jul 18 06:32:22 PM PDT 24
Finished Jul 18 06:38:58 PM PDT 24
Peak memory 201924 kb
Host smart-80b2afa7-216e-4f35-9327-6d2c8d96ff81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498186975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.3498186975
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.3068213594
Short name T692
Test name
Test status
Simulation time 172173681511 ps
CPU time 103.27 seconds
Started Jul 18 06:32:28 PM PDT 24
Finished Jul 18 06:34:14 PM PDT 24
Peak memory 201740 kb
Host smart-b5ffadbe-0da0-43a5-b1a7-d4777088c6d1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068213594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fix
ed.3068213594
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.2117413136
Short name T706
Test name
Test status
Simulation time 528542527526 ps
CPU time 1214.68 seconds
Started Jul 18 06:32:30 PM PDT 24
Finished Jul 18 06:52:47 PM PDT 24
Peak memory 201760 kb
Host smart-75bc25e3-b158-4892-8b49-dec29b663922
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117413136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters
_wakeup.2117413136
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.1036153046
Short name T428
Test name
Test status
Simulation time 406074948023 ps
CPU time 118.27 seconds
Started Jul 18 06:32:20 PM PDT 24
Finished Jul 18 06:34:20 PM PDT 24
Peak memory 201724 kb
Host smart-d3d5249a-0138-4b10-b13d-f84d6aa79a2a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036153046 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.adc_ctrl_filters_wakeup_fixed.1036153046
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.1537315231
Short name T742
Test name
Test status
Simulation time 70388927511 ps
CPU time 270.67 seconds
Started Jul 18 06:32:31 PM PDT 24
Finished Jul 18 06:37:04 PM PDT 24
Peak memory 202108 kb
Host smart-9bf085f3-f357-47f0-8bfa-00ace2a08098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537315231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.1537315231
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.882736190
Short name T609
Test name
Test status
Simulation time 38669279343 ps
CPU time 47.33 seconds
Started Jul 18 06:32:21 PM PDT 24
Finished Jul 18 06:33:10 PM PDT 24
Peak memory 201580 kb
Host smart-ad2d4983-d9b2-469a-a53e-ae1efc3636d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882736190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.882736190
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.3540435481
Short name T669
Test name
Test status
Simulation time 3900079175 ps
CPU time 9.22 seconds
Started Jul 18 06:32:28 PM PDT 24
Finished Jul 18 06:32:41 PM PDT 24
Peak memory 201580 kb
Host smart-4d798f46-ab6c-4d2d-843a-6a473ac2ff6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540435481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.3540435481
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.2761940942
Short name T701
Test name
Test status
Simulation time 5903542513 ps
CPU time 14.46 seconds
Started Jul 18 06:32:24 PM PDT 24
Finished Jul 18 06:32:39 PM PDT 24
Peak memory 201592 kb
Host smart-ab9f8bb3-5bb2-432f-a7d4-b66acec92f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761940942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.2761940942
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.393931804
Short name T705
Test name
Test status
Simulation time 29862782985 ps
CPU time 63.32 seconds
Started Jul 18 06:32:27 PM PDT 24
Finished Jul 18 06:33:33 PM PDT 24
Peak memory 201596 kb
Host smart-e09c3b58-9565-445b-add3-f0db42cca4b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393931804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all.
393931804
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.2634578713
Short name T385
Test name
Test status
Simulation time 1499624014 ps
CPU time 4.09 seconds
Started Jul 18 06:32:26 PM PDT 24
Finished Jul 18 06:32:33 PM PDT 24
Peak memory 201672 kb
Host smart-0a6609ac-e689-4f9b-af67-0ed45ce60957
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634578713 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.2634578713
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.909566851
Short name T703
Test name
Test status
Simulation time 307476556 ps
CPU time 0.98 seconds
Started Jul 18 06:32:25 PM PDT 24
Finished Jul 18 06:32:28 PM PDT 24
Peak memory 201548 kb
Host smart-a340469c-d030-424e-b801-21c845bbbe06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909566851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.909566851
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.2086962739
Short name T281
Test name
Test status
Simulation time 486373297286 ps
CPU time 1116.27 seconds
Started Jul 18 06:32:27 PM PDT 24
Finished Jul 18 06:51:06 PM PDT 24
Peak memory 201728 kb
Host smart-7987276e-ae54-4f1d-b473-cdd641eccf0a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086962739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gat
ing.2086962739
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.2849459891
Short name T601
Test name
Test status
Simulation time 496866988836 ps
CPU time 1158.31 seconds
Started Jul 18 06:32:32 PM PDT 24
Finished Jul 18 06:51:53 PM PDT 24
Peak memory 201696 kb
Host smart-f3320070-1e62-4ba5-8aee-3f86b28cca43
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849459891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interru
pt_fixed.2849459891
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.2081831616
Short name T132
Test name
Test status
Simulation time 490466947260 ps
CPU time 1101.19 seconds
Started Jul 18 06:32:28 PM PDT 24
Finished Jul 18 06:50:52 PM PDT 24
Peak memory 201708 kb
Host smart-324b5bd3-2d60-414b-97a5-785f5a314f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081831616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.2081831616
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.646421
Short name T760
Test name
Test status
Simulation time 486312363191 ps
CPU time 1125.18 seconds
Started Jul 18 06:32:29 PM PDT 24
Finished Jul 18 06:51:17 PM PDT 24
Peak memory 201728 kb
Host smart-51eec1c5-2011-4caa-afc6-03f9e4154dc4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=646421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fixed.646421
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.2532252191
Short name T461
Test name
Test status
Simulation time 400661709903 ps
CPU time 247.55 seconds
Started Jul 18 06:32:28 PM PDT 24
Finished Jul 18 06:36:39 PM PDT 24
Peak memory 201728 kb
Host smart-4bcb224b-bee1-46b7-a259-98509c92a9b5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532252191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.adc_ctrl_filters_wakeup_fixed.2532252191
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.844191634
Short name T708
Test name
Test status
Simulation time 71474711369 ps
CPU time 287.1 seconds
Started Jul 18 06:32:33 PM PDT 24
Finished Jul 18 06:37:23 PM PDT 24
Peak memory 201952 kb
Host smart-a3992b8c-b56e-48ba-8f4f-f0499f310949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844191634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.844191634
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.285836966
Short name T496
Test name
Test status
Simulation time 29670099451 ps
CPU time 18.85 seconds
Started Jul 18 06:32:28 PM PDT 24
Finished Jul 18 06:32:50 PM PDT 24
Peak memory 201600 kb
Host smart-6b0f437c-05e7-43e3-907a-33db83838bbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285836966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.285836966
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.4243968103
Short name T373
Test name
Test status
Simulation time 3507956494 ps
CPU time 8.33 seconds
Started Jul 18 06:32:26 PM PDT 24
Finished Jul 18 06:32:37 PM PDT 24
Peak memory 201588 kb
Host smart-d7c64f85-8e49-47fd-b0b8-848ec59a9c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243968103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.4243968103
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.876518218
Short name T771
Test name
Test status
Simulation time 6011380336 ps
CPU time 7.94 seconds
Started Jul 18 06:32:21 PM PDT 24
Finished Jul 18 06:32:31 PM PDT 24
Peak memory 201656 kb
Host smart-57628273-2d46-4f86-8f5f-4c5c558aaf93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876518218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.876518218
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.1355181224
Short name T12
Test name
Test status
Simulation time 30136032928 ps
CPU time 86.12 seconds
Started Jul 18 06:32:26 PM PDT 24
Finished Jul 18 06:33:55 PM PDT 24
Peak memory 202404 kb
Host smart-de88deea-25a8-4d82-834e-0f30c28b4800
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355181224 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.1355181224
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.3015858829
Short name T475
Test name
Test status
Simulation time 526370865 ps
CPU time 1.87 seconds
Started Jul 18 06:32:32 PM PDT 24
Finished Jul 18 06:32:36 PM PDT 24
Peak memory 201520 kb
Host smart-9a22c0dd-9cf8-460f-a7de-650d059e7e07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015858829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.3015858829
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.3274539481
Short name T123
Test name
Test status
Simulation time 516005971584 ps
CPU time 110.79 seconds
Started Jul 18 06:32:31 PM PDT 24
Finished Jul 18 06:34:24 PM PDT 24
Peak memory 201760 kb
Host smart-8b451e76-62e4-4cba-86c0-6f7c269b1554
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274539481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gat
ing.3274539481
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.287336064
Short name T333
Test name
Test status
Simulation time 181159676781 ps
CPU time 422.05 seconds
Started Jul 18 06:32:27 PM PDT 24
Finished Jul 18 06:39:32 PM PDT 24
Peak memory 201752 kb
Host smart-5a3dd2f9-6daa-4379-9343-c8d0ad08af66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287336064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.287336064
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.4273181114
Short name T668
Test name
Test status
Simulation time 162138112036 ps
CPU time 358.8 seconds
Started Jul 18 06:32:28 PM PDT 24
Finished Jul 18 06:38:29 PM PDT 24
Peak memory 201812 kb
Host smart-787f34fe-29bc-473e-a583-804eabd678df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273181114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.4273181114
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.3540893838
Short name T680
Test name
Test status
Simulation time 319554195836 ps
CPU time 676.8 seconds
Started Jul 18 06:32:26 PM PDT 24
Finished Jul 18 06:43:45 PM PDT 24
Peak memory 201716 kb
Host smart-b2cc4c1a-44d1-4630-976b-8de7e9306007
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540893838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fix
ed.3540893838
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.2599376541
Short name T482
Test name
Test status
Simulation time 192042439644 ps
CPU time 81.56 seconds
Started Jul 18 06:32:28 PM PDT 24
Finished Jul 18 06:33:52 PM PDT 24
Peak memory 201720 kb
Host smart-2b169ae2-7950-44b2-bb47-80514a14c17d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599376541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16
.adc_ctrl_filters_wakeup_fixed.2599376541
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.2485370827
Short name T773
Test name
Test status
Simulation time 144525561877 ps
CPU time 442.01 seconds
Started Jul 18 06:32:27 PM PDT 24
Finished Jul 18 06:39:52 PM PDT 24
Peak memory 202112 kb
Host smart-39fb489c-41d8-4396-b7bc-9f57d3b91aeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485370827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.2485370827
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.3074106266
Short name T471
Test name
Test status
Simulation time 30322039342 ps
CPU time 7.44 seconds
Started Jul 18 06:32:28 PM PDT 24
Finished Jul 18 06:32:38 PM PDT 24
Peak memory 201604 kb
Host smart-e0159615-8ba9-4d78-91fe-c8d396be1221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074106266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.3074106266
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.2098205059
Short name T362
Test name
Test status
Simulation time 5309669172 ps
CPU time 3.61 seconds
Started Jul 18 06:32:29 PM PDT 24
Finished Jul 18 06:32:35 PM PDT 24
Peak memory 201604 kb
Host smart-57d19336-5b57-4a4c-8059-29987fdf6b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098205059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.2098205059
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.3112722861
Short name T791
Test name
Test status
Simulation time 6008301931 ps
CPU time 7.52 seconds
Started Jul 18 06:32:26 PM PDT 24
Finished Jul 18 06:32:36 PM PDT 24
Peak memory 201596 kb
Host smart-cec6a4f6-d6b2-4cbd-8009-6e4eb4d765db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112722861 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.3112722861
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.2924327643
Short name T573
Test name
Test status
Simulation time 48999164259 ps
CPU time 92.13 seconds
Started Jul 18 06:32:29 PM PDT 24
Finished Jul 18 06:34:04 PM PDT 24
Peak memory 201924 kb
Host smart-a72091d6-b4cc-4d73-ae50-d439c2b07abc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924327643 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.2924327643
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.2031691946
Short name T398
Test name
Test status
Simulation time 429408508 ps
CPU time 1.55 seconds
Started Jul 18 06:32:31 PM PDT 24
Finished Jul 18 06:32:35 PM PDT 24
Peak memory 201560 kb
Host smart-ea890ff7-c5cc-4303-9431-f83d63908316
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031691946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.2031691946
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.3208781009
Short name T287
Test name
Test status
Simulation time 163194133774 ps
CPU time 146.58 seconds
Started Jul 18 06:32:34 PM PDT 24
Finished Jul 18 06:35:04 PM PDT 24
Peak memory 201752 kb
Host smart-9d19cad7-de4d-4653-8423-ca219e938c66
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208781009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gat
ing.3208781009
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.2624710814
Short name T282
Test name
Test status
Simulation time 179796731613 ps
CPU time 108.01 seconds
Started Jul 18 06:32:34 PM PDT 24
Finished Jul 18 06:34:25 PM PDT 24
Peak memory 201772 kb
Host smart-f1354639-b1e3-407c-a0bd-229f79b5a425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624710814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.2624710814
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.3597675430
Short name T239
Test name
Test status
Simulation time 158248620593 ps
CPU time 379.43 seconds
Started Jul 18 06:32:31 PM PDT 24
Finished Jul 18 06:38:53 PM PDT 24
Peak memory 201756 kb
Host smart-02df05b9-2499-45ab-94cc-3b98560dc8e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597675430 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.3597675430
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.285656852
Short name T492
Test name
Test status
Simulation time 326788663179 ps
CPU time 362.56 seconds
Started Jul 18 06:32:33 PM PDT 24
Finished Jul 18 06:38:38 PM PDT 24
Peak memory 201732 kb
Host smart-57b7af88-684b-40fb-904c-e8efaa3ce868
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=285656852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrup
t_fixed.285656852
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.1774939862
Short name T148
Test name
Test status
Simulation time 492096964819 ps
CPU time 263.86 seconds
Started Jul 18 06:32:34 PM PDT 24
Finished Jul 18 06:37:01 PM PDT 24
Peak memory 201820 kb
Host smart-8071c42d-1ec1-410e-b86b-034e4e2fb9a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774939862 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.1774939862
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.1342896977
Short name T402
Test name
Test status
Simulation time 160129602543 ps
CPU time 183.91 seconds
Started Jul 18 06:32:33 PM PDT 24
Finished Jul 18 06:35:40 PM PDT 24
Peak memory 201736 kb
Host smart-b2e2ed94-0514-43e4-afb2-88f77ff2ec9b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342896977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fix
ed.1342896977
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.1137361733
Short name T249
Test name
Test status
Simulation time 177538413824 ps
CPU time 388.74 seconds
Started Jul 18 06:32:32 PM PDT 24
Finished Jul 18 06:39:03 PM PDT 24
Peak memory 201800 kb
Host smart-228a7412-a682-4f66-baa4-ffa73a342079
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137361733 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters
_wakeup.1137361733
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.4240392033
Short name T792
Test name
Test status
Simulation time 194635344738 ps
CPU time 43.77 seconds
Started Jul 18 06:32:33 PM PDT 24
Finished Jul 18 06:33:20 PM PDT 24
Peak memory 201744 kb
Host smart-a4f732e2-6dc5-4164-ab08-640d296883b0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240392033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.adc_ctrl_filters_wakeup_fixed.4240392033
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.3955007208
Short name T92
Test name
Test status
Simulation time 121024931066 ps
CPU time 340.12 seconds
Started Jul 18 06:32:31 PM PDT 24
Finished Jul 18 06:38:13 PM PDT 24
Peak memory 202152 kb
Host smart-6c15e4df-bf93-4651-bfce-ef9fdd280579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955007208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.3955007208
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.3658915397
Short name T510
Test name
Test status
Simulation time 23576319754 ps
CPU time 57.72 seconds
Started Jul 18 06:32:30 PM PDT 24
Finished Jul 18 06:33:30 PM PDT 24
Peak memory 201612 kb
Host smart-af69f4b1-7b02-45ae-b920-b9c5d1c67740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658915397 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.3658915397
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.2151987116
Short name T547
Test name
Test status
Simulation time 2832795019 ps
CPU time 2.25 seconds
Started Jul 18 06:32:31 PM PDT 24
Finished Jul 18 06:32:36 PM PDT 24
Peak memory 201612 kb
Host smart-22463a06-11cb-481e-af91-636fb3da4fc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151987116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.2151987116
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.3403565162
Short name T753
Test name
Test status
Simulation time 5614468542 ps
CPU time 14.4 seconds
Started Jul 18 06:32:33 PM PDT 24
Finished Jul 18 06:32:50 PM PDT 24
Peak memory 201472 kb
Host smart-6c0b0de6-71ea-4c8d-8176-1b2e7bfdee53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403565162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.3403565162
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.938156425
Short name T574
Test name
Test status
Simulation time 193582694936 ps
CPU time 411.04 seconds
Started Jul 18 06:32:34 PM PDT 24
Finished Jul 18 06:39:28 PM PDT 24
Peak memory 201728 kb
Host smart-40fbf43b-2436-4c73-a880-92fcdb345b80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938156425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all.
938156425
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.3877721202
Short name T685
Test name
Test status
Simulation time 186404601811 ps
CPU time 184.89 seconds
Started Jul 18 06:32:22 PM PDT 24
Finished Jul 18 06:35:28 PM PDT 24
Peak memory 210444 kb
Host smart-5731ade0-817e-446c-b554-9d264b8c0229
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877721202 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.3877721202
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.4234612792
Short name T738
Test name
Test status
Simulation time 469261280 ps
CPU time 1.2 seconds
Started Jul 18 06:32:21 PM PDT 24
Finished Jul 18 06:32:24 PM PDT 24
Peak memory 201644 kb
Host smart-109395b2-cf37-4701-8cde-dc0fe8e0784d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234612792 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.4234612792
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.3683897232
Short name T237
Test name
Test status
Simulation time 164163701010 ps
CPU time 188.87 seconds
Started Jul 18 06:32:34 PM PDT 24
Finished Jul 18 06:35:46 PM PDT 24
Peak memory 201728 kb
Host smart-57a4ea4b-fefb-432a-91a8-dcaa4977baa0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683897232 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gat
ing.3683897232
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.540387110
Short name T339
Test name
Test status
Simulation time 165127235373 ps
CPU time 297.78 seconds
Started Jul 18 06:32:32 PM PDT 24
Finished Jul 18 06:37:32 PM PDT 24
Peak memory 201748 kb
Host smart-3225e183-19be-4d82-b0d2-a639da41f590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540387110 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.540387110
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.1132944855
Short name T470
Test name
Test status
Simulation time 162173230232 ps
CPU time 65.09 seconds
Started Jul 18 06:32:31 PM PDT 24
Finished Jul 18 06:33:38 PM PDT 24
Peak memory 201784 kb
Host smart-da0c4ea2-b20f-47e3-ba82-afce88d4cbbe
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132944855 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interru
pt_fixed.1132944855
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.2149279502
Short name T313
Test name
Test status
Simulation time 329595693383 ps
CPU time 207.95 seconds
Started Jul 18 06:32:33 PM PDT 24
Finished Jul 18 06:36:04 PM PDT 24
Peak memory 201816 kb
Host smart-fed320ac-bb53-4efe-92e8-93cb72472742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149279502 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.2149279502
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.586215017
Short name T726
Test name
Test status
Simulation time 498206128926 ps
CPU time 1077.72 seconds
Started Jul 18 06:32:31 PM PDT 24
Finished Jul 18 06:50:31 PM PDT 24
Peak memory 201744 kb
Host smart-3cc3fcf7-7d5f-4e57-af25-fb4a74465bb3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=586215017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fixe
d.586215017
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.2072531679
Short name T422
Test name
Test status
Simulation time 620753183358 ps
CPU time 310.26 seconds
Started Jul 18 06:32:35 PM PDT 24
Finished Jul 18 06:37:48 PM PDT 24
Peak memory 201728 kb
Host smart-5616df9c-7cec-48e7-a3b8-b23af10e71bd
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072531679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.adc_ctrl_filters_wakeup_fixed.2072531679
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.3852737739
Short name T351
Test name
Test status
Simulation time 128380983152 ps
CPU time 673.5 seconds
Started Jul 18 06:32:31 PM PDT 24
Finished Jul 18 06:43:47 PM PDT 24
Peak memory 202104 kb
Host smart-b27a3ec0-fa22-4b0e-98a3-64f4bb0b2dd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852737739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.3852737739
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.1352048392
Short name T642
Test name
Test status
Simulation time 26233469313 ps
CPU time 27.13 seconds
Started Jul 18 06:32:34 PM PDT 24
Finished Jul 18 06:33:05 PM PDT 24
Peak memory 201604 kb
Host smart-2cb51f96-e52a-425f-a626-bcbb883cdc50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352048392 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.1352048392
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.2078687397
Short name T157
Test name
Test status
Simulation time 2907336256 ps
CPU time 7.85 seconds
Started Jul 18 06:32:34 PM PDT 24
Finished Jul 18 06:32:45 PM PDT 24
Peak memory 201604 kb
Host smart-bd1a60c2-e5dc-429a-8ab5-a016c5ff927c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078687397 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.2078687397
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.1026477573
Short name T555
Test name
Test status
Simulation time 6047483412 ps
CPU time 2.45 seconds
Started Jul 18 06:32:34 PM PDT 24
Finished Jul 18 06:32:40 PM PDT 24
Peak memory 201616 kb
Host smart-698aaca6-c586-461e-b7a7-c47d599259b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026477573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.1026477573
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.787603186
Short name T700
Test name
Test status
Simulation time 456797888 ps
CPU time 0.86 seconds
Started Jul 18 06:32:37 PM PDT 24
Finished Jul 18 06:32:41 PM PDT 24
Peak memory 201696 kb
Host smart-0fb21d39-bf98-43d1-9115-9828f3a4b041
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787603186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.787603186
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.245249956
Short name T283
Test name
Test status
Simulation time 532914122861 ps
CPU time 1145.35 seconds
Started Jul 18 06:32:36 PM PDT 24
Finished Jul 18 06:51:45 PM PDT 24
Peak memory 201068 kb
Host smart-7f9b5ba3-748e-40d9-b0e3-30dc9c25ab5d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245249956 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gati
ng.245249956
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.3226659722
Short name T167
Test name
Test status
Simulation time 496345700733 ps
CPU time 103.04 seconds
Started Jul 18 06:32:34 PM PDT 24
Finished Jul 18 06:34:21 PM PDT 24
Peak memory 201760 kb
Host smart-d892d61b-c880-4514-93a6-474a35bae945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226659722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.3226659722
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.2073849256
Short name T391
Test name
Test status
Simulation time 487254407561 ps
CPU time 556.95 seconds
Started Jul 18 06:32:34 PM PDT 24
Finished Jul 18 06:41:55 PM PDT 24
Peak memory 201860 kb
Host smart-0fb631ad-3217-4ced-9459-4a44cf8576db
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073849256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interru
pt_fixed.2073849256
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.580527215
Short name T714
Test name
Test status
Simulation time 491177953204 ps
CPU time 713.48 seconds
Started Jul 18 06:32:35 PM PDT 24
Finished Jul 18 06:44:32 PM PDT 24
Peak memory 201764 kb
Host smart-240840e6-1812-47f2-8531-bdd9f6314d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580527215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.580527215
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.1264745376
Short name T406
Test name
Test status
Simulation time 483617599789 ps
CPU time 299.75 seconds
Started Jul 18 06:32:36 PM PDT 24
Finished Jul 18 06:37:39 PM PDT 24
Peak memory 201708 kb
Host smart-707309d6-144c-4fd5-8658-47e74e97e0e9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264745376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fix
ed.1264745376
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.3180510400
Short name T277
Test name
Test status
Simulation time 375763893103 ps
CPU time 216.79 seconds
Started Jul 18 06:32:36 PM PDT 24
Finished Jul 18 06:36:16 PM PDT 24
Peak memory 201652 kb
Host smart-efb0b032-1071-4f0b-9e4b-bb3cb0faa5ff
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180510400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters
_wakeup.3180510400
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.3049470458
Short name T431
Test name
Test status
Simulation time 613588319302 ps
CPU time 623.21 seconds
Started Jul 18 06:32:34 PM PDT 24
Finished Jul 18 06:43:01 PM PDT 24
Peak memory 201696 kb
Host smart-69d9e481-5b74-4839-9f00-50fd8fcc85bc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049470458 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.adc_ctrl_filters_wakeup_fixed.3049470458
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.3993579779
Short name T686
Test name
Test status
Simulation time 29603701141 ps
CPU time 6.1 seconds
Started Jul 18 06:32:36 PM PDT 24
Finished Jul 18 06:32:45 PM PDT 24
Peak memory 201604 kb
Host smart-437099bb-3ed3-4e4c-b17d-c63fcfd28954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993579779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.3993579779
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.227301904
Short name T779
Test name
Test status
Simulation time 5305252879 ps
CPU time 3.41 seconds
Started Jul 18 06:32:35 PM PDT 24
Finished Jul 18 06:32:42 PM PDT 24
Peak memory 201608 kb
Host smart-5f15de59-b2ff-4275-8e8d-cac4f240de6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227301904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.227301904
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.1333814155
Short name T420
Test name
Test status
Simulation time 5997118194 ps
CPU time 1.57 seconds
Started Jul 18 06:32:34 PM PDT 24
Finished Jul 18 06:32:38 PM PDT 24
Peak memory 201604 kb
Host smart-b4348835-7fd0-457b-a17f-f4c49b2b7c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333814155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.1333814155
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.893831810
Short name T150
Test name
Test status
Simulation time 178751211025 ps
CPU time 400.25 seconds
Started Jul 18 06:32:36 PM PDT 24
Finished Jul 18 06:39:19 PM PDT 24
Peak memory 201048 kb
Host smart-acd73d64-7ef5-412b-ac98-ddcb62e74455
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893831810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all.
893831810
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.1249078133
Short name T21
Test name
Test status
Simulation time 87384296533 ps
CPU time 60.38 seconds
Started Jul 18 06:32:34 PM PDT 24
Finished Jul 18 06:33:38 PM PDT 24
Peak memory 210068 kb
Host smart-0c92a118-b7fd-492f-ba88-fd9174583749
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249078133 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.1249078133
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.4235302233
Short name T460
Test name
Test status
Simulation time 447271328 ps
CPU time 0.81 seconds
Started Jul 18 06:31:43 PM PDT 24
Finished Jul 18 06:31:48 PM PDT 24
Peak memory 201552 kb
Host smart-036744f0-6521-4974-979a-8a06889e6276
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235302233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.4235302233
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.1670782215
Short name T674
Test name
Test status
Simulation time 159561047406 ps
CPU time 197.74 seconds
Started Jul 18 06:31:44 PM PDT 24
Finished Jul 18 06:35:06 PM PDT 24
Peak memory 201808 kb
Host smart-419af08a-f64f-4b52-87e3-9d4ae0500493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670782215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.1670782215
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.3478675380
Short name T717
Test name
Test status
Simulation time 161816882924 ps
CPU time 83.6 seconds
Started Jul 18 06:31:43 PM PDT 24
Finished Jul 18 06:33:10 PM PDT 24
Peak memory 201792 kb
Host smart-8d86e92d-d1e5-4528-869d-8df81cc97e01
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478675380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrup
t_fixed.3478675380
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.4049165813
Short name T745
Test name
Test status
Simulation time 492527669750 ps
CPU time 373.58 seconds
Started Jul 18 06:31:44 PM PDT 24
Finished Jul 18 06:38:02 PM PDT 24
Peak memory 201728 kb
Host smart-dbb5d40b-9a83-4b13-a58d-91b4f534cdd0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049165813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixe
d.4049165813
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.2588498263
Short name T790
Test name
Test status
Simulation time 383833971472 ps
CPU time 795.55 seconds
Started Jul 18 06:31:44 PM PDT 24
Finished Jul 18 06:45:04 PM PDT 24
Peak memory 201720 kb
Host smart-7e01b00d-7dbe-48ad-be19-c63cb2208511
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588498263 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
adc_ctrl_filters_wakeup_fixed.2588498263
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.1800892323
Short name T748
Test name
Test status
Simulation time 122696562606 ps
CPU time 605.17 seconds
Started Jul 18 06:31:41 PM PDT 24
Finished Jul 18 06:41:48 PM PDT 24
Peak memory 202160 kb
Host smart-8fd91935-1fcd-4c66-9ab3-87ca8143cb26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800892323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.1800892323
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.3891537699
Short name T414
Test name
Test status
Simulation time 26280242239 ps
CPU time 63.27 seconds
Started Jul 18 06:31:46 PM PDT 24
Finished Jul 18 06:32:54 PM PDT 24
Peak memory 201796 kb
Host smart-d772b1d2-09df-4bfc-8264-74c707f58e0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891537699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.3891537699
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.3927304010
Short name T444
Test name
Test status
Simulation time 3309865159 ps
CPU time 7.95 seconds
Started Jul 18 06:31:42 PM PDT 24
Finished Jul 18 06:31:53 PM PDT 24
Peak memory 201552 kb
Host smart-8cde028c-63ad-4ca6-98eb-459348531e81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927304010 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.3927304010
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.1514149069
Short name T87
Test name
Test status
Simulation time 8470343928 ps
CPU time 18.12 seconds
Started Jul 18 06:31:50 PM PDT 24
Finished Jul 18 06:32:11 PM PDT 24
Peak memory 218340 kb
Host smart-6fc296fc-2824-4e8a-b7ac-2188c6484a01
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514149069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.1514149069
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.524486547
Short name T33
Test name
Test status
Simulation time 6182231597 ps
CPU time 2.11 seconds
Started Jul 18 06:31:40 PM PDT 24
Finished Jul 18 06:31:43 PM PDT 24
Peak memory 201620 kb
Host smart-c7624feb-a7c2-43d5-b903-f5cbbfd62e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524486547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.524486547
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.3280610659
Short name T31
Test name
Test status
Simulation time 351028876759 ps
CPU time 754.75 seconds
Started Jul 18 06:31:45 PM PDT 24
Finished Jul 18 06:44:24 PM PDT 24
Peak memory 201792 kb
Host smart-b632c350-d976-46be-a08d-947d440bdd03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280610659 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.
3280610659
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.1261094636
Short name T483
Test name
Test status
Simulation time 401590578 ps
CPU time 1.56 seconds
Started Jul 18 06:32:50 PM PDT 24
Finished Jul 18 06:32:53 PM PDT 24
Peak memory 201548 kb
Host smart-282b48d2-1ce9-4674-9883-385e61a60d8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261094636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.1261094636
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.606299133
Short name T139
Test name
Test status
Simulation time 328345658035 ps
CPU time 110.31 seconds
Started Jul 18 06:32:36 PM PDT 24
Finished Jul 18 06:34:30 PM PDT 24
Peak memory 201760 kb
Host smart-c8a3c828-075c-4879-97d0-6aaeef7aa09c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606299133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.606299133
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.2643823578
Short name T501
Test name
Test status
Simulation time 490020864124 ps
CPU time 307.07 seconds
Started Jul 18 06:32:37 PM PDT 24
Finished Jul 18 06:37:47 PM PDT 24
Peak memory 201904 kb
Host smart-a098e24d-6408-4872-9b9c-a18b85c0f97d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643823578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interru
pt_fixed.2643823578
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.1859048717
Short name T786
Test name
Test status
Simulation time 164798700704 ps
CPU time 75.33 seconds
Started Jul 18 06:32:36 PM PDT 24
Finished Jul 18 06:33:55 PM PDT 24
Peak memory 201712 kb
Host smart-e8360454-0c0b-462f-90db-5c2116242c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859048717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.1859048717
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.2305901575
Short name T435
Test name
Test status
Simulation time 497810083033 ps
CPU time 715.77 seconds
Started Jul 18 06:32:34 PM PDT 24
Finished Jul 18 06:44:34 PM PDT 24
Peak memory 201904 kb
Host smart-ba6acf94-455e-4771-aa64-1a3f3a9f87b3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305901575 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fix
ed.2305901575
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.645502529
Short name T293
Test name
Test status
Simulation time 343639567477 ps
CPU time 846.71 seconds
Started Jul 18 06:32:34 PM PDT 24
Finished Jul 18 06:46:45 PM PDT 24
Peak memory 201832 kb
Host smart-82f97420-30bc-4311-97b7-9a7b7814979a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645502529 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_
wakeup.645502529
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.3628013253
Short name T527
Test name
Test status
Simulation time 606029568519 ps
CPU time 1278.29 seconds
Started Jul 18 06:32:36 PM PDT 24
Finished Jul 18 06:53:58 PM PDT 24
Peak memory 201740 kb
Host smart-7192e4cf-1401-4aa5-88c1-79fc309cf974
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628013253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.adc_ctrl_filters_wakeup_fixed.3628013253
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.3965707317
Short name T558
Test name
Test status
Simulation time 102207806716 ps
CPU time 309.11 seconds
Started Jul 18 06:32:50 PM PDT 24
Finished Jul 18 06:38:01 PM PDT 24
Peak memory 202148 kb
Host smart-17eb18b9-e93a-4a43-b80a-92e640e8c03d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965707317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.3965707317
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.3301739109
Short name T3
Test name
Test status
Simulation time 28770849991 ps
CPU time 31.17 seconds
Started Jul 18 06:32:53 PM PDT 24
Finished Jul 18 06:33:26 PM PDT 24
Peak memory 201584 kb
Host smart-657a569f-64d5-400c-94f9-971224f5a801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301739109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.3301739109
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.868942252
Short name T646
Test name
Test status
Simulation time 3661087375 ps
CPU time 4.74 seconds
Started Jul 18 06:32:51 PM PDT 24
Finished Jul 18 06:32:57 PM PDT 24
Peak memory 201600 kb
Host smart-27fa6443-58c9-48de-9a13-05870999c85a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868942252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.868942252
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.3531990118
Short name T116
Test name
Test status
Simulation time 5942772338 ps
CPU time 7.5 seconds
Started Jul 18 06:32:35 PM PDT 24
Finished Jul 18 06:32:46 PM PDT 24
Peak memory 201612 kb
Host smart-a28f0374-b95a-44a6-ac92-05bb7dc288d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531990118 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.3531990118
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.13195384
Short name T479
Test name
Test status
Simulation time 17638463442 ps
CPU time 21.92 seconds
Started Jul 18 06:32:52 PM PDT 24
Finished Jul 18 06:33:15 PM PDT 24
Peak memory 201936 kb
Host smart-6efacd67-fa1b-47c4-ae82-8d92164e3535
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13195384 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all.13195384
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.3303289034
Short name T400
Test name
Test status
Simulation time 396581521 ps
CPU time 0.8 seconds
Started Jul 18 06:33:10 PM PDT 24
Finished Jul 18 06:33:14 PM PDT 24
Peak memory 201620 kb
Host smart-539f701c-2651-46dd-ba5e-b8237083f900
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303289034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.3303289034
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.2009313166
Short name T242
Test name
Test status
Simulation time 511126583073 ps
CPU time 215.34 seconds
Started Jul 18 06:32:50 PM PDT 24
Finished Jul 18 06:36:28 PM PDT 24
Peak memory 201824 kb
Host smart-10a83b79-8add-42bb-86d6-523a8a2853aa
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009313166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gat
ing.2009313166
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.1785205546
Short name T177
Test name
Test status
Simulation time 320000743670 ps
CPU time 67.57 seconds
Started Jul 18 06:32:53 PM PDT 24
Finished Jul 18 06:34:02 PM PDT 24
Peak memory 201760 kb
Host smart-feb139f0-35c8-426a-88e0-920a77e460c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785205546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.1785205546
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.357350721
Short name T127
Test name
Test status
Simulation time 332805978123 ps
CPU time 720.83 seconds
Started Jul 18 06:32:54 PM PDT 24
Finished Jul 18 06:44:56 PM PDT 24
Peak memory 201792 kb
Host smart-0371f0b4-3d9a-4be5-822b-9f57d483d5b5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=357350721 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrup
t_fixed.357350721
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.3498832554
Short name T709
Test name
Test status
Simulation time 335116799384 ps
CPU time 689.27 seconds
Started Jul 18 06:32:50 PM PDT 24
Finished Jul 18 06:44:21 PM PDT 24
Peak memory 201808 kb
Host smart-c88c3e2f-7c13-40ae-a691-66c8f87e79d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498832554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.3498832554
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.3283280364
Short name T673
Test name
Test status
Simulation time 489302733058 ps
CPU time 1173.49 seconds
Started Jul 18 06:32:50 PM PDT 24
Finished Jul 18 06:52:26 PM PDT 24
Peak memory 201800 kb
Host smart-0622a797-b8b9-49fe-9bca-8ad17ee8d76c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283280364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fix
ed.3283280364
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.674958903
Short name T183
Test name
Test status
Simulation time 377073942581 ps
CPU time 150.3 seconds
Started Jul 18 06:32:53 PM PDT 24
Finished Jul 18 06:35:24 PM PDT 24
Peak memory 201728 kb
Host smart-f8c321aa-0a4d-4222-8e97-4a2fccc57cb3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674958903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_
wakeup.674958903
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.4278417206
Short name T368
Test name
Test status
Simulation time 590070910509 ps
CPU time 630.42 seconds
Started Jul 18 06:32:50 PM PDT 24
Finished Jul 18 06:43:22 PM PDT 24
Peak memory 201720 kb
Host smart-fcc0661d-2133-4ca4-bbd2-6769b4381afd
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278417206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.adc_ctrl_filters_wakeup_fixed.4278417206
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.986256241
Short name T375
Test name
Test status
Simulation time 74109413299 ps
CPU time 416.98 seconds
Started Jul 18 06:33:07 PM PDT 24
Finished Jul 18 06:40:05 PM PDT 24
Peak memory 202144 kb
Host smart-4b8fa22a-b301-4e5b-beab-565a04281158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986256241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.986256241
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.910407520
Short name T570
Test name
Test status
Simulation time 41630301804 ps
CPU time 46.75 seconds
Started Jul 18 06:33:10 PM PDT 24
Finished Jul 18 06:34:00 PM PDT 24
Peak memory 201480 kb
Host smart-fc688169-d2d3-4341-9454-459aa39e08d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910407520 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.910407520
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.2940387502
Short name T476
Test name
Test status
Simulation time 3141029135 ps
CPU time 1.27 seconds
Started Jul 18 06:32:50 PM PDT 24
Finished Jul 18 06:32:53 PM PDT 24
Peak memory 201588 kb
Host smart-3a3f39d2-445d-455d-ad9a-d8b70f9c1007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940387502 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.2940387502
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.1439608557
Short name T386
Test name
Test status
Simulation time 5677868803 ps
CPU time 5.47 seconds
Started Jul 18 06:32:53 PM PDT 24
Finished Jul 18 06:32:59 PM PDT 24
Peak memory 201604 kb
Host smart-4d519e21-8c2b-414c-a8b9-e98321b17565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439608557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.1439608557
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.2824653067
Short name T329
Test name
Test status
Simulation time 175083823323 ps
CPU time 98.24 seconds
Started Jul 18 06:33:08 PM PDT 24
Finished Jul 18 06:34:49 PM PDT 24
Peak memory 201728 kb
Host smart-9e7b4d2b-0e73-4873-be6d-4b249eb8568e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824653067 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all
.2824653067
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.4279133079
Short name T191
Test name
Test status
Simulation time 86402817017 ps
CPU time 282.04 seconds
Started Jul 18 06:33:09 PM PDT 24
Finished Jul 18 06:37:54 PM PDT 24
Peak memory 210440 kb
Host smart-cdfae8e2-a79e-4077-bd88-c31d1107e044
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279133079 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.4279133079
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.4128880439
Short name T575
Test name
Test status
Simulation time 445650965 ps
CPU time 0.83 seconds
Started Jul 18 06:33:10 PM PDT 24
Finished Jul 18 06:33:14 PM PDT 24
Peak memory 201404 kb
Host smart-570bd755-0983-4323-8efb-96cfb3ed8f9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128880439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.4128880439
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.3993652145
Short name T310
Test name
Test status
Simulation time 201431282292 ps
CPU time 451.85 seconds
Started Jul 18 06:33:08 PM PDT 24
Finished Jul 18 06:40:42 PM PDT 24
Peak memory 201804 kb
Host smart-75052b1a-cb26-4a8e-8b0c-b14f0e73bc92
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993652145 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gat
ing.3993652145
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.2111658866
Short name T43
Test name
Test status
Simulation time 331600401994 ps
CPU time 810.43 seconds
Started Jul 18 06:33:09 PM PDT 24
Finished Jul 18 06:46:41 PM PDT 24
Peak memory 201740 kb
Host smart-c3a3ff2f-ce59-4d49-b1f4-bf865204e3e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111658866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.2111658866
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.2305052448
Short name T165
Test name
Test status
Simulation time 321693165809 ps
CPU time 87.26 seconds
Started Jul 18 06:33:10 PM PDT 24
Finished Jul 18 06:34:40 PM PDT 24
Peak memory 201748 kb
Host smart-a4c7debd-b2cd-4337-a25b-4060a814fd9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305052448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.2305052448
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.1781980213
Short name T739
Test name
Test status
Simulation time 483824931598 ps
CPU time 533.9 seconds
Started Jul 18 06:33:08 PM PDT 24
Finished Jul 18 06:42:03 PM PDT 24
Peak memory 201708 kb
Host smart-99e848af-b8aa-458d-a96a-cc5d815dfe70
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781980213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interru
pt_fixed.1781980213
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.1529209744
Short name T325
Test name
Test status
Simulation time 496688022782 ps
CPU time 1119.6 seconds
Started Jul 18 06:33:09 PM PDT 24
Finished Jul 18 06:51:52 PM PDT 24
Peak memory 201796 kb
Host smart-43df7607-ef68-42f7-ba00-ba16c16280bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529209744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.1529209744
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.3204728259
Short name T670
Test name
Test status
Simulation time 495046635377 ps
CPU time 1112.82 seconds
Started Jul 18 06:33:10 PM PDT 24
Finished Jul 18 06:51:46 PM PDT 24
Peak memory 201716 kb
Host smart-fd05ca8a-ed07-4a8e-bd0f-43c2ea39585e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204728259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fix
ed.3204728259
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.1127272202
Short name T621
Test name
Test status
Simulation time 605105743947 ps
CPU time 326.76 seconds
Started Jul 18 06:33:12 PM PDT 24
Finished Jul 18 06:38:41 PM PDT 24
Peak memory 201784 kb
Host smart-f482dc79-435c-4204-8fc3-6e34feb7f611
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127272202 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.adc_ctrl_filters_wakeup_fixed.1127272202
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.1259659591
Short name T796
Test name
Test status
Simulation time 125257486889 ps
CPU time 697.19 seconds
Started Jul 18 06:33:08 PM PDT 24
Finished Jul 18 06:44:46 PM PDT 24
Peak memory 202156 kb
Host smart-b3fd4383-cccc-4c57-b6f3-5ae6559bf9c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259659591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.1259659591
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.342008540
Short name T533
Test name
Test status
Simulation time 26818993291 ps
CPU time 57.39 seconds
Started Jul 18 06:33:11 PM PDT 24
Finished Jul 18 06:34:11 PM PDT 24
Peak memory 201680 kb
Host smart-257b787b-a1ea-4b01-a671-e5fd232c0ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342008540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.342008540
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.3816092052
Short name T410
Test name
Test status
Simulation time 3731289303 ps
CPU time 4.95 seconds
Started Jul 18 06:33:10 PM PDT 24
Finished Jul 18 06:33:17 PM PDT 24
Peak memory 201604 kb
Host smart-264dff51-53e8-4ece-9044-7c8c50884850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816092052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.3816092052
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.4053630892
Short name T728
Test name
Test status
Simulation time 5884664936 ps
CPU time 7.41 seconds
Started Jul 18 06:33:08 PM PDT 24
Finished Jul 18 06:33:16 PM PDT 24
Peak memory 201612 kb
Host smart-3e8613c7-78cf-408a-be9d-003f27b6f239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053630892 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.4053630892
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.274991673
Short name T347
Test name
Test status
Simulation time 119353744576 ps
CPU time 543.33 seconds
Started Jul 18 06:33:09 PM PDT 24
Finished Jul 18 06:42:14 PM PDT 24
Peak memory 202104 kb
Host smart-49f248cd-619b-4b7c-bbad-a23ee6c72e73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274991673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all.
274991673
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.3738846387
Short name T194
Test name
Test status
Simulation time 263516985903 ps
CPU time 266.51 seconds
Started Jul 18 06:33:11 PM PDT 24
Finished Jul 18 06:37:40 PM PDT 24
Peak memory 218656 kb
Host smart-fdb480e3-6c39-4fe4-b226-a9a5773cd882
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738846387 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.3738846387
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.132076308
Short name T616
Test name
Test status
Simulation time 360967634 ps
CPU time 0.83 seconds
Started Jul 18 06:33:24 PM PDT 24
Finished Jul 18 06:33:28 PM PDT 24
Peak memory 201488 kb
Host smart-ac526ad8-ac3f-47a6-a0a1-90ebb657a2ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132076308 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.132076308
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.3018410872
Short name T515
Test name
Test status
Simulation time 163423421944 ps
CPU time 390.77 seconds
Started Jul 18 06:33:10 PM PDT 24
Finished Jul 18 06:39:43 PM PDT 24
Peak memory 201760 kb
Host smart-cc39c95b-10d4-42c3-a09e-8ce9215c0ae5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018410872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gat
ing.3018410872
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.1155787043
Short name T89
Test name
Test status
Simulation time 338403744547 ps
CPU time 220.78 seconds
Started Jul 18 06:33:10 PM PDT 24
Finished Jul 18 06:36:54 PM PDT 24
Peak memory 201816 kb
Host smart-44c10159-de62-4590-888e-5f45a7f2f509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155787043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.1155787043
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.550727999
Short name T747
Test name
Test status
Simulation time 328845632556 ps
CPU time 207.96 seconds
Started Jul 18 06:33:09 PM PDT 24
Finished Jul 18 06:36:39 PM PDT 24
Peak memory 201728 kb
Host smart-649fab08-16ec-4c95-9e9b-9dee074ffa3a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=550727999 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrup
t_fixed.550727999
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.2429727289
Short name T588
Test name
Test status
Simulation time 497329081076 ps
CPU time 131.47 seconds
Started Jul 18 06:33:08 PM PDT 24
Finished Jul 18 06:35:20 PM PDT 24
Peak memory 201716 kb
Host smart-8d0a775d-3a0c-4f95-83eb-f4d55cc4c3db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429727289 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.2429727289
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.3783135960
Short name T468
Test name
Test status
Simulation time 484888814207 ps
CPU time 326.03 seconds
Started Jul 18 06:33:09 PM PDT 24
Finished Jul 18 06:38:37 PM PDT 24
Peak memory 201744 kb
Host smart-7b960cbe-7e65-4eea-94b2-5fb6d281056e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783135960 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fix
ed.3783135960
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.169837076
Short name T780
Test name
Test status
Simulation time 390148178800 ps
CPU time 922.22 seconds
Started Jul 18 06:33:09 PM PDT 24
Finished Jul 18 06:48:34 PM PDT 24
Peak memory 201732 kb
Host smart-90352028-d7ca-4187-ab66-ae6a31e4cce2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169837076 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
adc_ctrl_filters_wakeup_fixed.169837076
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.3340068369
Short name T195
Test name
Test status
Simulation time 95279070444 ps
CPU time 379.55 seconds
Started Jul 18 06:33:24 PM PDT 24
Finished Jul 18 06:39:47 PM PDT 24
Peak memory 202132 kb
Host smart-c95d9739-9092-4971-8cc0-d71e55ab4257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340068369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.3340068369
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.709847355
Short name T797
Test name
Test status
Simulation time 23921214143 ps
CPU time 15.97 seconds
Started Jul 18 06:33:26 PM PDT 24
Finished Jul 18 06:33:44 PM PDT 24
Peak memory 201608 kb
Host smart-52495560-e71e-40d2-8e2f-b22871255ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709847355 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.709847355
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.491129639
Short name T505
Test name
Test status
Simulation time 4025967036 ps
CPU time 9.52 seconds
Started Jul 18 06:33:24 PM PDT 24
Finished Jul 18 06:33:36 PM PDT 24
Peak memory 201604 kb
Host smart-d54aed66-f16d-4927-94cb-d3e34db8e8c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491129639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.491129639
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.562572283
Short name T478
Test name
Test status
Simulation time 5896567349 ps
CPU time 8.18 seconds
Started Jul 18 06:33:08 PM PDT 24
Finished Jul 18 06:33:17 PM PDT 24
Peak memory 201520 kb
Host smart-13661848-c8cf-4efd-97a9-efd977996ffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562572283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.562572283
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.1868108585
Short name T526
Test name
Test status
Simulation time 553148407 ps
CPU time 0.92 seconds
Started Jul 18 06:33:26 PM PDT 24
Finished Jul 18 06:33:29 PM PDT 24
Peak memory 201620 kb
Host smart-da6fff05-25ca-42bf-9d16-1b1e81d7a29a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868108585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.1868108585
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.4174006157
Short name T279
Test name
Test status
Simulation time 164307220921 ps
CPU time 346.99 seconds
Started Jul 18 06:33:22 PM PDT 24
Finished Jul 18 06:39:11 PM PDT 24
Peak memory 201740 kb
Host smart-3f8f2969-e665-4202-ac46-0fe3454ee513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174006157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.4174006157
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.378423992
Short name T681
Test name
Test status
Simulation time 331171024051 ps
CPU time 533.47 seconds
Started Jul 18 06:33:22 PM PDT 24
Finished Jul 18 06:42:18 PM PDT 24
Peak memory 201784 kb
Host smart-a9067e93-0c43-4fc3-80ef-16de17e42dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378423992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.378423992
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.2193551090
Short name T627
Test name
Test status
Simulation time 486548821383 ps
CPU time 288.36 seconds
Started Jul 18 06:33:23 PM PDT 24
Finished Jul 18 06:38:13 PM PDT 24
Peak memory 201736 kb
Host smart-9b7c0d4f-b85b-4ca4-bc9d-8788da185711
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193551090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interru
pt_fixed.2193551090
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.783185291
Short name T550
Test name
Test status
Simulation time 492332385193 ps
CPU time 182.11 seconds
Started Jul 18 06:33:24 PM PDT 24
Finished Jul 18 06:36:29 PM PDT 24
Peak memory 201792 kb
Host smart-75f53fc1-dd57-4152-ba28-831f045be467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783185291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.783185291
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.731225233
Short name T556
Test name
Test status
Simulation time 166427260256 ps
CPU time 349.29 seconds
Started Jul 18 06:33:23 PM PDT 24
Finished Jul 18 06:39:14 PM PDT 24
Peak memory 201732 kb
Host smart-e91f46f5-cf50-4c7f-b928-5c76b0dc715b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=731225233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fixe
d.731225233
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.366702475
Short name T572
Test name
Test status
Simulation time 200078190729 ps
CPU time 423.89 seconds
Started Jul 18 06:33:22 PM PDT 24
Finished Jul 18 06:40:27 PM PDT 24
Peak memory 201972 kb
Host smart-5b85e6bc-f003-4d13-85c7-3bb6966a078f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366702475 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_
wakeup.366702475
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.3061263033
Short name T772
Test name
Test status
Simulation time 205912828297 ps
CPU time 118.95 seconds
Started Jul 18 06:33:25 PM PDT 24
Finished Jul 18 06:35:26 PM PDT 24
Peak memory 201744 kb
Host smart-c7dd6a7d-d0bd-46c1-8a66-5ece050bd431
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061263033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.adc_ctrl_filters_wakeup_fixed.3061263033
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.3929031742
Short name T366
Test name
Test status
Simulation time 39220815062 ps
CPU time 23.8 seconds
Started Jul 18 06:33:23 PM PDT 24
Finished Jul 18 06:33:49 PM PDT 24
Peak memory 201604 kb
Host smart-de2bea9a-3122-4f72-b84c-acfde7346a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929031742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.3929031742
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.2299231040
Short name T540
Test name
Test status
Simulation time 4303302985 ps
CPU time 11.58 seconds
Started Jul 18 06:33:23 PM PDT 24
Finished Jul 18 06:33:37 PM PDT 24
Peak memory 201604 kb
Host smart-db1ecb55-910f-4f7a-ba69-03a73a00364c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299231040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.2299231040
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.2323240171
Short name T665
Test name
Test status
Simulation time 5663898101 ps
CPU time 2.77 seconds
Started Jul 18 06:33:23 PM PDT 24
Finished Jul 18 06:33:27 PM PDT 24
Peak memory 201620 kb
Host smart-f52bf21a-bc66-41cd-ad78-cc332ab1f9b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323240171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.2323240171
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.173620929
Short name T633
Test name
Test status
Simulation time 224221987270 ps
CPU time 490.94 seconds
Started Jul 18 06:33:26 PM PDT 24
Finished Jul 18 06:41:39 PM PDT 24
Peak memory 201744 kb
Host smart-12648ee6-da1f-46cf-9190-753c5fd4ee49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173620929 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all.
173620929
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.3360236607
Short name T15
Test name
Test status
Simulation time 20481669084 ps
CPU time 90.14 seconds
Started Jul 18 06:33:24 PM PDT 24
Finished Jul 18 06:34:57 PM PDT 24
Peak memory 210464 kb
Host smart-19b02822-955a-42a8-8b59-8c7547b484fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360236607 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.3360236607
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.2127434745
Short name T759
Test name
Test status
Simulation time 501290420 ps
CPU time 0.85 seconds
Started Jul 18 06:33:38 PM PDT 24
Finished Jul 18 06:33:40 PM PDT 24
Peak memory 201560 kb
Host smart-45250898-7cde-4a92-b76c-5b85f38c1ba1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127434745 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.2127434745
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.2393090327
Short name T798
Test name
Test status
Simulation time 166650817260 ps
CPU time 110.67 seconds
Started Jul 18 06:33:36 PM PDT 24
Finished Jul 18 06:35:28 PM PDT 24
Peak memory 201740 kb
Host smart-bcf460c5-9c4d-48b6-b4f2-b4ac88b83ac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393090327 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.2393090327
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.1746847527
Short name T215
Test name
Test status
Simulation time 165795771123 ps
CPU time 410.46 seconds
Started Jul 18 06:33:24 PM PDT 24
Finished Jul 18 06:40:18 PM PDT 24
Peak memory 201828 kb
Host smart-761e733e-477d-4430-a69d-aaa24a202ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746847527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.1746847527
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.85129615
Short name T795
Test name
Test status
Simulation time 164803883088 ps
CPU time 331.07 seconds
Started Jul 18 06:33:23 PM PDT 24
Finished Jul 18 06:38:56 PM PDT 24
Peak memory 201724 kb
Host smart-3da35b5f-e7e2-4ec9-8eb2-97907f6e5188
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=85129615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt
_fixed.85129615
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.1859442896
Short name T625
Test name
Test status
Simulation time 331126546561 ps
CPU time 101.42 seconds
Started Jul 18 06:33:26 PM PDT 24
Finished Jul 18 06:35:10 PM PDT 24
Peak memory 201808 kb
Host smart-25a6f218-68b3-499d-87e0-12c9ed7f5f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859442896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.1859442896
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.1521507990
Short name T778
Test name
Test status
Simulation time 326106667868 ps
CPU time 176.19 seconds
Started Jul 18 06:33:21 PM PDT 24
Finished Jul 18 06:36:19 PM PDT 24
Peak memory 201808 kb
Host smart-fda17e45-0f1e-405e-a30f-6ff67076e50b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521507990 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fix
ed.1521507990
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.655276713
Short name T124
Test name
Test status
Simulation time 442572428283 ps
CPU time 378.66 seconds
Started Jul 18 06:33:23 PM PDT 24
Finished Jul 18 06:39:44 PM PDT 24
Peak memory 201764 kb
Host smart-bb7c32d0-cea2-4e5a-b529-d0542857451f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655276713 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_
wakeup.655276713
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.1539718601
Short name T426
Test name
Test status
Simulation time 607932721688 ps
CPU time 1352.38 seconds
Started Jul 18 06:33:25 PM PDT 24
Finished Jul 18 06:56:00 PM PDT 24
Peak memory 201744 kb
Host smart-07cba653-5be1-444a-827f-9944f0a35b94
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539718601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25
.adc_ctrl_filters_wakeup_fixed.1539718601
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.1589015838
Short name T750
Test name
Test status
Simulation time 128503424484 ps
CPU time 412.74 seconds
Started Jul 18 06:33:38 PM PDT 24
Finished Jul 18 06:40:32 PM PDT 24
Peak memory 202108 kb
Host smart-cbed4b0f-bd2d-4828-a93e-54101150da1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589015838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.1589015838
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.3999424009
Short name T429
Test name
Test status
Simulation time 45477918793 ps
CPU time 31.71 seconds
Started Jul 18 06:33:37 PM PDT 24
Finished Jul 18 06:34:10 PM PDT 24
Peak memory 201596 kb
Host smart-22a56033-e24e-4170-a0d7-e69fc185e42a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999424009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.3999424009
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.2483023422
Short name T117
Test name
Test status
Simulation time 3257142290 ps
CPU time 7.9 seconds
Started Jul 18 06:33:38 PM PDT 24
Finished Jul 18 06:33:47 PM PDT 24
Peak memory 201720 kb
Host smart-2e83e9cb-11a6-4d61-a352-eef08adf6a1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483023422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.2483023422
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.2068485620
Short name T384
Test name
Test status
Simulation time 5899670017 ps
CPU time 14.59 seconds
Started Jul 18 06:33:22 PM PDT 24
Finished Jul 18 06:33:38 PM PDT 24
Peak memory 201612 kb
Host smart-23fd1435-0b07-4d96-bc0f-95e2fc600bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068485620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.2068485620
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.3620984749
Short name T40
Test name
Test status
Simulation time 127388522527 ps
CPU time 232.78 seconds
Started Jul 18 06:33:37 PM PDT 24
Finished Jul 18 06:37:31 PM PDT 24
Peak memory 218564 kb
Host smart-515a389d-f06e-4dc5-96ba-6451b005d2b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620984749 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.3620984749
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.934501182
Short name T469
Test name
Test status
Simulation time 366420226 ps
CPU time 1.37 seconds
Started Jul 18 06:33:51 PM PDT 24
Finished Jul 18 06:33:54 PM PDT 24
Peak memory 201544 kb
Host smart-acc59959-6cb9-44f3-83f0-9de9e7513fc9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934501182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.934501182
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.2093644357
Short name T307
Test name
Test status
Simulation time 485574183080 ps
CPU time 244.9 seconds
Started Jul 18 06:33:41 PM PDT 24
Finished Jul 18 06:37:47 PM PDT 24
Peak memory 201708 kb
Host smart-637eb3c4-c0a3-4b5d-a6f6-60e76db770e9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093644357 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gat
ing.2093644357
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.1781523114
Short name T624
Test name
Test status
Simulation time 323725038627 ps
CPU time 389.36 seconds
Started Jul 18 06:33:37 PM PDT 24
Finished Jul 18 06:40:08 PM PDT 24
Peak memory 201736 kb
Host smart-22f1e7a7-5fe6-49e6-847a-efd77bab7900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781523114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.1781523114
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.2598197018
Short name T122
Test name
Test status
Simulation time 164491893795 ps
CPU time 96.34 seconds
Started Jul 18 06:33:40 PM PDT 24
Finished Jul 18 06:35:17 PM PDT 24
Peak memory 201724 kb
Host smart-0cea975d-82d5-465c-aba0-5d0a67808dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598197018 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.2598197018
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.1772795540
Short name T413
Test name
Test status
Simulation time 161540101953 ps
CPU time 43.9 seconds
Started Jul 18 06:33:39 PM PDT 24
Finished Jul 18 06:34:24 PM PDT 24
Peak memory 201636 kb
Host smart-b80b4825-73bf-4a73-ae3f-3a352e77bd97
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772795540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interru
pt_fixed.1772795540
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.3888203105
Short name T671
Test name
Test status
Simulation time 324417506866 ps
CPU time 197.94 seconds
Started Jul 18 06:33:37 PM PDT 24
Finished Jul 18 06:36:56 PM PDT 24
Peak memory 201812 kb
Host smart-e81a4d16-c77a-4f43-bf63-affab7e17be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888203105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.3888203105
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.423824459
Short name T657
Test name
Test status
Simulation time 498288660236 ps
CPU time 1083.56 seconds
Started Jul 18 06:33:38 PM PDT 24
Finished Jul 18 06:51:43 PM PDT 24
Peak memory 201844 kb
Host smart-7bd86c9f-b213-4780-a2c5-75cf3523d234
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=423824459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fixe
d.423824459
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.33475572
Short name T644
Test name
Test status
Simulation time 574582480600 ps
CPU time 1290.09 seconds
Started Jul 18 06:33:38 PM PDT 24
Finished Jul 18 06:55:09 PM PDT 24
Peak memory 201788 kb
Host smart-88ca420f-001c-4e98-b4ad-ddeb4f226290
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33475572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_w
akeup.33475572
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.2575066620
Short name T690
Test name
Test status
Simulation time 596435144793 ps
CPU time 1450.5 seconds
Started Jul 18 06:33:38 PM PDT 24
Finished Jul 18 06:57:50 PM PDT 24
Peak memory 201784 kb
Host smart-cf67fe00-e7ad-4168-8f60-c06284008b9d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575066620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.adc_ctrl_filters_wakeup_fixed.2575066620
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.420158433
Short name T595
Test name
Test status
Simulation time 91597400228 ps
CPU time 434.74 seconds
Started Jul 18 06:33:53 PM PDT 24
Finished Jul 18 06:41:10 PM PDT 24
Peak memory 202172 kb
Host smart-525e9e91-c466-4d15-b2e2-288f87151123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420158433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.420158433
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.3454026996
Short name T713
Test name
Test status
Simulation time 42986788439 ps
CPU time 98.25 seconds
Started Jul 18 06:33:39 PM PDT 24
Finished Jul 18 06:35:19 PM PDT 24
Peak memory 201556 kb
Host smart-03c791e0-0ffb-46ba-a8d6-021625f24872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454026996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.3454026996
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.3917844733
Short name T736
Test name
Test status
Simulation time 4225825479 ps
CPU time 5.85 seconds
Started Jul 18 06:33:39 PM PDT 24
Finished Jul 18 06:33:46 PM PDT 24
Peak memory 201676 kb
Host smart-541e2130-da97-45af-bb4f-50ad9c860348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917844733 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.3917844733
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.434249833
Short name T403
Test name
Test status
Simulation time 6118879132 ps
CPU time 2.32 seconds
Started Jul 18 06:33:38 PM PDT 24
Finished Jul 18 06:33:42 PM PDT 24
Peak memory 201604 kb
Host smart-b0ad2698-ffa3-4d4b-8575-ad4b35ec1640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434249833 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.434249833
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.3623715912
Short name T32
Test name
Test status
Simulation time 34503071433 ps
CPU time 21.8 seconds
Started Jul 18 06:33:53 PM PDT 24
Finished Jul 18 06:34:17 PM PDT 24
Peak memory 201508 kb
Host smart-1b993d2a-2254-4902-86a0-d53a84afae1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623715912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all
.3623715912
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.1638524605
Short name T746
Test name
Test status
Simulation time 49782340126 ps
CPU time 113.12 seconds
Started Jul 18 06:33:52 PM PDT 24
Finished Jul 18 06:35:48 PM PDT 24
Peak memory 210416 kb
Host smart-10bf200f-c244-43fd-9749-fddbc9ed027e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638524605 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.1638524605
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.2054065225
Short name T531
Test name
Test status
Simulation time 384234432 ps
CPU time 0.68 seconds
Started Jul 18 06:34:05 PM PDT 24
Finished Jul 18 06:34:07 PM PDT 24
Peak memory 201560 kb
Host smart-11c0ca43-f095-4229-af7f-b7bf3b5454a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054065225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.2054065225
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.1979134408
Short name T186
Test name
Test status
Simulation time 525112048758 ps
CPU time 408.42 seconds
Started Jul 18 06:33:52 PM PDT 24
Finished Jul 18 06:40:43 PM PDT 24
Peak memory 201748 kb
Host smart-6df7b779-9cd1-4231-8819-c2e4121c0708
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979134408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gat
ing.1979134408
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.2952163190
Short name T777
Test name
Test status
Simulation time 503330344299 ps
CPU time 632.16 seconds
Started Jul 18 06:33:52 PM PDT 24
Finished Jul 18 06:44:27 PM PDT 24
Peak memory 201812 kb
Host smart-d0e93540-509a-4241-85a5-dc50452a0138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952163190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.2952163190
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.867963990
Short name T606
Test name
Test status
Simulation time 337278235166 ps
CPU time 847.5 seconds
Started Jul 18 06:33:51 PM PDT 24
Finished Jul 18 06:48:01 PM PDT 24
Peak memory 201668 kb
Host smart-0c80da59-dbb3-4d20-ad79-e80ec603741f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=867963990 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrup
t_fixed.867963990
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.995889984
Short name T155
Test name
Test status
Simulation time 490528813292 ps
CPU time 248.35 seconds
Started Jul 18 06:33:53 PM PDT 24
Finished Jul 18 06:38:04 PM PDT 24
Peak memory 201720 kb
Host smart-b3fef1e8-4328-4731-85a2-6dce3e3c4f74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995889984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.995889984
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.2403333508
Short name T752
Test name
Test status
Simulation time 163441224237 ps
CPU time 370.11 seconds
Started Jul 18 06:33:51 PM PDT 24
Finished Jul 18 06:40:04 PM PDT 24
Peak memory 201736 kb
Host smart-90192594-3805-4777-b3dc-9e96d1993ceb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403333508 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fix
ed.2403333508
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.3385968216
Short name T297
Test name
Test status
Simulation time 186250325673 ps
CPU time 52.22 seconds
Started Jul 18 06:33:52 PM PDT 24
Finished Jul 18 06:34:47 PM PDT 24
Peak memory 201832 kb
Host smart-d017098b-48ca-4d5c-9d76-ff47a4c5602b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385968216 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters
_wakeup.3385968216
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.4231014084
Short name T581
Test name
Test status
Simulation time 197769564029 ps
CPU time 453.95 seconds
Started Jul 18 06:33:59 PM PDT 24
Finished Jul 18 06:41:34 PM PDT 24
Peak memory 201936 kb
Host smart-de063d13-9802-45dd-b086-d5377eaf25bd
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231014084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.adc_ctrl_filters_wakeup_fixed.4231014084
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.1433396110
Short name T349
Test name
Test status
Simulation time 131705385061 ps
CPU time 549.65 seconds
Started Jul 18 06:33:51 PM PDT 24
Finished Jul 18 06:43:04 PM PDT 24
Peak memory 202116 kb
Host smart-e8630368-3e04-44fc-a5e9-7ba24f29c64c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433396110 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.1433396110
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.3014262875
Short name T490
Test name
Test status
Simulation time 34419176156 ps
CPU time 14.13 seconds
Started Jul 18 06:33:50 PM PDT 24
Finished Jul 18 06:34:06 PM PDT 24
Peak memory 201600 kb
Host smart-704c3b23-f187-4fc9-802c-56f8dbf57f64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014262875 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.3014262875
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.3236244786
Short name T689
Test name
Test status
Simulation time 4589042392 ps
CPU time 1.83 seconds
Started Jul 18 06:33:52 PM PDT 24
Finished Jul 18 06:33:56 PM PDT 24
Peak memory 201676 kb
Host smart-c8ec17f4-b19f-4aa0-8525-cb04773ba278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236244786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.3236244786
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.751993428
Short name T432
Test name
Test status
Simulation time 5893411709 ps
CPU time 8.47 seconds
Started Jul 18 06:33:52 PM PDT 24
Finished Jul 18 06:34:03 PM PDT 24
Peak memory 201608 kb
Host smart-27863601-6a5e-4876-b81d-0bad25d2998b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751993428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.751993428
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.3833555089
Short name T716
Test name
Test status
Simulation time 332637485891 ps
CPU time 377.45 seconds
Started Jul 18 06:34:04 PM PDT 24
Finished Jul 18 06:40:22 PM PDT 24
Peak memory 201812 kb
Host smart-148caf63-1419-4aca-a2e1-25ef106b0730
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833555089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all
.3833555089
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.2622542389
Short name T551
Test name
Test status
Simulation time 105512341579 ps
CPU time 48.54 seconds
Started Jul 18 06:33:53 PM PDT 24
Finished Jul 18 06:34:44 PM PDT 24
Peak memory 211056 kb
Host smart-b6ce8b24-1f44-4f9e-9b35-6bbd88c5b1fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622542389 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.2622542389
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.71793192
Short name T458
Test name
Test status
Simulation time 365710208 ps
CPU time 1.11 seconds
Started Jul 18 06:34:23 PM PDT 24
Finished Jul 18 06:34:25 PM PDT 24
Peak memory 201568 kb
Host smart-7082f6da-a487-497e-a66e-e86fce4e87fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71793192 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.71793192
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.3483877531
Short name T754
Test name
Test status
Simulation time 331747731455 ps
CPU time 52.44 seconds
Started Jul 18 06:34:05 PM PDT 24
Finished Jul 18 06:34:58 PM PDT 24
Peak memory 201772 kb
Host smart-7194a7f4-36c8-4153-a0d1-3b98d1c44607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483877531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.3483877531
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.3621489401
Short name T446
Test name
Test status
Simulation time 161261493713 ps
CPU time 334.31 seconds
Started Jul 18 06:34:05 PM PDT 24
Finished Jul 18 06:39:41 PM PDT 24
Peak memory 201728 kb
Host smart-1b6e39d1-f51f-4e7a-a2e6-e8c78207d15d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621489401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.3621489401
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.1260053495
Short name T389
Test name
Test status
Simulation time 323497562878 ps
CPU time 383.99 seconds
Started Jul 18 06:34:03 PM PDT 24
Finished Jul 18 06:40:28 PM PDT 24
Peak memory 201716 kb
Host smart-35311543-f77c-46ed-8a3c-6d6bae219c66
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260053495 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interru
pt_fixed.1260053495
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.4082250766
Short name T207
Test name
Test status
Simulation time 327144487402 ps
CPU time 578.41 seconds
Started Jul 18 06:34:06 PM PDT 24
Finished Jul 18 06:43:46 PM PDT 24
Peak memory 201716 kb
Host smart-8c5099d8-9606-42a8-8a2f-a209efbebe14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082250766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.4082250766
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.2928709033
Short name T603
Test name
Test status
Simulation time 171460295205 ps
CPU time 380.88 seconds
Started Jul 18 06:34:03 PM PDT 24
Finished Jul 18 06:40:25 PM PDT 24
Peak memory 201748 kb
Host smart-876ce503-94b9-4122-97c6-34536c3afe93
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928709033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fix
ed.2928709033
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.157338447
Short name T181
Test name
Test status
Simulation time 555564961158 ps
CPU time 320.02 seconds
Started Jul 18 06:34:20 PM PDT 24
Finished Jul 18 06:39:40 PM PDT 24
Peak memory 201812 kb
Host smart-40f98653-4ae0-4b40-8cfb-3d2d99c4622b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157338447 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_
wakeup.157338447
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.3897714765
Short name T417
Test name
Test status
Simulation time 400960866267 ps
CPU time 945.19 seconds
Started Jul 18 06:34:06 PM PDT 24
Finished Jul 18 06:49:52 PM PDT 24
Peak memory 201708 kb
Host smart-61d2c38c-f526-4251-bfa0-79b943ef7b5c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897714765 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.adc_ctrl_filters_wakeup_fixed.3897714765
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.3219691339
Short name T614
Test name
Test status
Simulation time 127729644708 ps
CPU time 431.74 seconds
Started Jul 18 06:34:05 PM PDT 24
Finished Jul 18 06:41:18 PM PDT 24
Peak memory 202156 kb
Host smart-ed898644-c93d-4679-9479-af77f91daf8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219691339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.3219691339
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.1089284745
Short name T520
Test name
Test status
Simulation time 33228776216 ps
CPU time 75.36 seconds
Started Jul 18 06:34:04 PM PDT 24
Finished Jul 18 06:35:20 PM PDT 24
Peak memory 201608 kb
Host smart-660c5288-5b26-4bbb-97b5-8c4ffe491639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089284745 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.1089284745
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.1506765389
Short name T563
Test name
Test status
Simulation time 4869634375 ps
CPU time 3.31 seconds
Started Jul 18 06:34:04 PM PDT 24
Finished Jul 18 06:34:09 PM PDT 24
Peak memory 201600 kb
Host smart-bf225aa5-861b-48ce-919e-91bac89a8dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506765389 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.1506765389
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.2532867410
Short name T466
Test name
Test status
Simulation time 5815025462 ps
CPU time 14.19 seconds
Started Jul 18 06:34:05 PM PDT 24
Finished Jul 18 06:34:21 PM PDT 24
Peak memory 201604 kb
Host smart-5b6a035f-4ccf-4ed2-9e4b-10e2e48909aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532867410 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.2532867410
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.374045522
Short name T18
Test name
Test status
Simulation time 94606134256 ps
CPU time 175.71 seconds
Started Jul 18 06:34:05 PM PDT 24
Finished Jul 18 06:37:02 PM PDT 24
Peak memory 211532 kb
Host smart-528706fd-b832-4cb9-b7ef-821363bfcbe5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374045522 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.374045522
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.1268378509
Short name T76
Test name
Test status
Simulation time 364350241 ps
CPU time 1.41 seconds
Started Jul 18 06:34:23 PM PDT 24
Finished Jul 18 06:34:25 PM PDT 24
Peak memory 201544 kb
Host smart-c4c877a9-b574-4cd3-868e-2dfe218c7dce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268378509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.1268378509
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.1711030203
Short name T146
Test name
Test status
Simulation time 401164447271 ps
CPU time 196.89 seconds
Started Jul 18 06:34:24 PM PDT 24
Finished Jul 18 06:37:43 PM PDT 24
Peak memory 201792 kb
Host smart-4b40f3c4-48bb-4738-80fc-13a6759409b9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711030203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gat
ing.1711030203
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.3241470496
Short name T179
Test name
Test status
Simulation time 536027877274 ps
CPU time 108.66 seconds
Started Jul 18 06:34:23 PM PDT 24
Finished Jul 18 06:36:12 PM PDT 24
Peak memory 201824 kb
Host smart-0d976c52-2994-4819-9db7-e29c239caace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241470496 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.3241470496
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.3128175155
Short name T744
Test name
Test status
Simulation time 323889873732 ps
CPU time 186.3 seconds
Started Jul 18 06:34:23 PM PDT 24
Finished Jul 18 06:37:31 PM PDT 24
Peak memory 201788 kb
Host smart-66b23d8f-45d1-44e4-a2db-7799169e3303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128175155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.3128175155
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.3248598730
Short name T718
Test name
Test status
Simulation time 494863519770 ps
CPU time 297.09 seconds
Started Jul 18 06:34:24 PM PDT 24
Finished Jul 18 06:39:22 PM PDT 24
Peak memory 201640 kb
Host smart-fdeb37e5-21d9-4eee-8a21-1a39c977de08
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248598730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interru
pt_fixed.3248598730
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.822068234
Short name T252
Test name
Test status
Simulation time 501519358394 ps
CPU time 286.28 seconds
Started Jul 18 06:34:21 PM PDT 24
Finished Jul 18 06:39:08 PM PDT 24
Peak memory 201832 kb
Host smart-aeff72b1-f4ee-4d6a-8d02-4742aee4ae76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822068234 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.822068234
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.827681755
Short name T369
Test name
Test status
Simulation time 163439112341 ps
CPU time 205.79 seconds
Started Jul 18 06:34:23 PM PDT 24
Finished Jul 18 06:37:50 PM PDT 24
Peak memory 201796 kb
Host smart-aa980086-16f1-4d17-8350-5dba71352a42
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=827681755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fixe
d.827681755
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.560581865
Short name T266
Test name
Test status
Simulation time 615156455742 ps
CPU time 1439.58 seconds
Started Jul 18 06:34:23 PM PDT 24
Finished Jul 18 06:58:23 PM PDT 24
Peak memory 201820 kb
Host smart-dcf6a398-c853-435d-b0e4-3c239d653268
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560581865 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_
wakeup.560581865
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.2497805926
Short name T518
Test name
Test status
Simulation time 606475852582 ps
CPU time 149.14 seconds
Started Jul 18 06:34:21 PM PDT 24
Finished Jul 18 06:36:51 PM PDT 24
Peak memory 201740 kb
Host smart-c55bdcc3-a989-4c04-8e98-254a4f4e8cfb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497805926 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.adc_ctrl_filters_wakeup_fixed.2497805926
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.4103514768
Short name T504
Test name
Test status
Simulation time 70442648223 ps
CPU time 312.41 seconds
Started Jul 18 06:34:22 PM PDT 24
Finished Jul 18 06:39:35 PM PDT 24
Peak memory 202124 kb
Host smart-5950b557-0127-4202-937f-59a9e0314221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103514768 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.4103514768
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.960224616
Short name T424
Test name
Test status
Simulation time 38172492060 ps
CPU time 10.21 seconds
Started Jul 18 06:34:22 PM PDT 24
Finished Jul 18 06:34:33 PM PDT 24
Peak memory 201608 kb
Host smart-7ac9477e-ba3b-42b8-a465-ea0ae4b5101e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960224616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.960224616
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.3138823159
Short name T743
Test name
Test status
Simulation time 3051253333 ps
CPU time 3.64 seconds
Started Jul 18 06:34:23 PM PDT 24
Finished Jul 18 06:34:28 PM PDT 24
Peak memory 201608 kb
Host smart-360c196b-6f1e-4d15-aa15-191cd9e9427b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138823159 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.3138823159
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.429550234
Short name T564
Test name
Test status
Simulation time 5762578594 ps
CPU time 2 seconds
Started Jul 18 06:34:22 PM PDT 24
Finished Jul 18 06:34:25 PM PDT 24
Peak memory 201612 kb
Host smart-f02222ab-7fdb-452a-8612-d4e0290afca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429550234 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.429550234
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.313711748
Short name T7
Test name
Test status
Simulation time 169398474426 ps
CPU time 107.25 seconds
Started Jul 18 06:34:23 PM PDT 24
Finished Jul 18 06:36:12 PM PDT 24
Peak memory 201800 kb
Host smart-22e5fec9-4d8e-469e-b01b-a968553f547b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313711748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all.
313711748
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.826430984
Short name T354
Test name
Test status
Simulation time 89161661459 ps
CPU time 315.95 seconds
Started Jul 18 06:34:23 PM PDT 24
Finished Jul 18 06:39:41 PM PDT 24
Peak memory 210416 kb
Host smart-9e4bb4a9-a334-418f-a10b-9a8c826a3a5f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826430984 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.826430984
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.2145434543
Short name T658
Test name
Test status
Simulation time 392530405 ps
CPU time 0.88 seconds
Started Jul 18 06:31:48 PM PDT 24
Finished Jul 18 06:31:53 PM PDT 24
Peak memory 201492 kb
Host smart-91bbb405-9e1d-4c43-8c1a-1fa4c0dbc190
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145434543 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.2145434543
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.1798055020
Short name T566
Test name
Test status
Simulation time 159085323740 ps
CPU time 352.94 seconds
Started Jul 18 06:31:45 PM PDT 24
Finished Jul 18 06:37:43 PM PDT 24
Peak memory 201940 kb
Host smart-dec3586d-2067-4fc6-8866-7339f3af306f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798055020 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gati
ng.1798055020
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.123985493
Short name T552
Test name
Test status
Simulation time 522059729976 ps
CPU time 288.61 seconds
Started Jul 18 06:31:46 PM PDT 24
Finished Jul 18 06:36:39 PM PDT 24
Peak memory 201752 kb
Host smart-51e98f93-7bb1-4e29-b245-5f02c70b2309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123985493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.123985493
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.2091937453
Short name T238
Test name
Test status
Simulation time 163147406160 ps
CPU time 368.93 seconds
Started Jul 18 06:31:42 PM PDT 24
Finished Jul 18 06:37:54 PM PDT 24
Peak memory 201820 kb
Host smart-e1b48269-73af-42c3-b5d7-63f9cda091b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091937453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.2091937453
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.3084489013
Short name T643
Test name
Test status
Simulation time 167853253278 ps
CPU time 102.08 seconds
Started Jul 18 06:31:44 PM PDT 24
Finished Jul 18 06:33:29 PM PDT 24
Peak memory 201716 kb
Host smart-9f210c3f-c756-4030-8e0b-06d0d53ddc6f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084489013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrup
t_fixed.3084489013
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.3430097833
Short name T184
Test name
Test status
Simulation time 487710905573 ps
CPU time 290.4 seconds
Started Jul 18 06:31:44 PM PDT 24
Finished Jul 18 06:36:39 PM PDT 24
Peak memory 201668 kb
Host smart-286c19a4-ee40-40dc-afcb-74553e85dfb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430097833 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.3430097833
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.3926130183
Short name T757
Test name
Test status
Simulation time 490968608276 ps
CPU time 1166.71 seconds
Started Jul 18 06:31:44 PM PDT 24
Finished Jul 18 06:51:15 PM PDT 24
Peak memory 201808 kb
Host smart-a0cd847f-4848-40c5-a7c2-fd935c1ea7e8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926130183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixe
d.3926130183
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.449853058
Short name T161
Test name
Test status
Simulation time 181841070834 ps
CPU time 437.41 seconds
Started Jul 18 06:31:43 PM PDT 24
Finished Jul 18 06:39:04 PM PDT 24
Peak memory 201744 kb
Host smart-50d38c94-1327-4643-b40b-6dbd5c90c6fa
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449853058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_w
akeup.449853058
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.1009474243
Short name T436
Test name
Test status
Simulation time 196337570343 ps
CPU time 439.6 seconds
Started Jul 18 06:31:47 PM PDT 24
Finished Jul 18 06:39:11 PM PDT 24
Peak memory 201752 kb
Host smart-c5b9277a-93c3-4dd9-b85b-fa104507b816
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009474243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
adc_ctrl_filters_wakeup_fixed.1009474243
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.1589800469
Short name T755
Test name
Test status
Simulation time 113618364325 ps
CPU time 367.3 seconds
Started Jul 18 06:31:44 PM PDT 24
Finished Jul 18 06:37:56 PM PDT 24
Peak memory 202108 kb
Host smart-b0739b43-81e1-4b4a-ad1e-b3000f66d41b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589800469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.1589800469
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.2059069863
Short name T474
Test name
Test status
Simulation time 27568794506 ps
CPU time 59.7 seconds
Started Jul 18 06:31:48 PM PDT 24
Finished Jul 18 06:32:52 PM PDT 24
Peak memory 201600 kb
Host smart-0f118091-d9e4-4fe3-ae47-61667ea8ae46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059069863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.2059069863
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.1271086282
Short name T707
Test name
Test status
Simulation time 5333906823 ps
CPU time 13.13 seconds
Started Jul 18 06:31:51 PM PDT 24
Finished Jul 18 06:32:06 PM PDT 24
Peak memory 201568 kb
Host smart-41366069-526c-4fa0-9bc7-13ce3343165e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271086282 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.1271086282
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.2864245478
Short name T159
Test name
Test status
Simulation time 5922026275 ps
CPU time 4 seconds
Started Jul 18 06:31:44 PM PDT 24
Finished Jul 18 06:31:51 PM PDT 24
Peak memory 201612 kb
Host smart-7af50891-e082-4674-a263-04d6a62a3598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864245478 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.2864245478
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.300097362
Short name T94
Test name
Test status
Simulation time 331476577400 ps
CPU time 778.99 seconds
Started Jul 18 06:31:43 PM PDT 24
Finished Jul 18 06:44:46 PM PDT 24
Peak memory 201736 kb
Host smart-f0a7dc2c-58a8-4e19-b513-c6de0b899830
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300097362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.300097362
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.394778887
Short name T502
Test name
Test status
Simulation time 421086387 ps
CPU time 0.7 seconds
Started Jul 18 06:34:41 PM PDT 24
Finished Jul 18 06:34:43 PM PDT 24
Peak memory 201436 kb
Host smart-bd4bd57e-6be8-4612-8727-de8ee47c7a6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394778887 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.394778887
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.4217909754
Short name T147
Test name
Test status
Simulation time 169038141862 ps
CPU time 198.67 seconds
Started Jul 18 06:34:42 PM PDT 24
Finished Jul 18 06:38:01 PM PDT 24
Peak memory 201752 kb
Host smart-e2d56c40-35ee-44bf-8004-c2cec372fbf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217909754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.4217909754
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.910004265
Short name T300
Test name
Test status
Simulation time 170330936714 ps
CPU time 100.03 seconds
Started Jul 18 06:34:42 PM PDT 24
Finished Jul 18 06:36:24 PM PDT 24
Peak memory 201748 kb
Host smart-218c1be1-b248-48df-af4f-f200211d575e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910004265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.910004265
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.3171804583
Short name T500
Test name
Test status
Simulation time 493499663561 ps
CPU time 215.29 seconds
Started Jul 18 06:34:41 PM PDT 24
Finished Jul 18 06:38:18 PM PDT 24
Peak memory 201720 kb
Host smart-980630d6-be01-4dd7-88ea-01e8773b1d54
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171804583 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interru
pt_fixed.3171804583
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.4168167478
Short name T553
Test name
Test status
Simulation time 326252801212 ps
CPU time 759.62 seconds
Started Jul 18 06:34:41 PM PDT 24
Finished Jul 18 06:47:21 PM PDT 24
Peak memory 201736 kb
Host smart-d0782af3-e69b-402e-a4b1-12a9e3e40187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168167478 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.4168167478
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.1537455347
Short name T589
Test name
Test status
Simulation time 331542281647 ps
CPU time 738.35 seconds
Started Jul 18 06:34:42 PM PDT 24
Finished Jul 18 06:47:01 PM PDT 24
Peak memory 201796 kb
Host smart-0d2edbea-fe66-41cc-99f8-5270a324ed71
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537455347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fix
ed.1537455347
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.2306050238
Short name T246
Test name
Test status
Simulation time 356144960186 ps
CPU time 182.48 seconds
Started Jul 18 06:34:40 PM PDT 24
Finished Jul 18 06:37:44 PM PDT 24
Peak memory 201820 kb
Host smart-76948d29-69b4-419f-80fb-c3bf50274d32
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306050238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters
_wakeup.2306050238
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.3175867365
Short name T637
Test name
Test status
Simulation time 394053964386 ps
CPU time 93.02 seconds
Started Jul 18 06:34:40 PM PDT 24
Finished Jul 18 06:36:15 PM PDT 24
Peak memory 201716 kb
Host smart-5f637e17-e276-45f2-b66a-c0288c91c924
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175867365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.adc_ctrl_filters_wakeup_fixed.3175867365
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.2435865252
Short name T356
Test name
Test status
Simulation time 108382196217 ps
CPU time 593.23 seconds
Started Jul 18 06:34:43 PM PDT 24
Finished Jul 18 06:44:37 PM PDT 24
Peak memory 202128 kb
Host smart-9fe4839b-8bc0-4c20-a046-ef6bd22146bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435865252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.2435865252
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.2501984319
Short name T427
Test name
Test status
Simulation time 31022121246 ps
CPU time 77.44 seconds
Started Jul 18 06:34:44 PM PDT 24
Finished Jul 18 06:36:02 PM PDT 24
Peak memory 201604 kb
Host smart-1c162bb9-3490-4379-bd1c-2f766ef90f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501984319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.2501984319
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.3412226141
Short name T719
Test name
Test status
Simulation time 2778566336 ps
CPU time 1.34 seconds
Started Jul 18 06:34:42 PM PDT 24
Finished Jul 18 06:34:45 PM PDT 24
Peak memory 201600 kb
Host smart-715b7390-f9bc-40cc-a7d9-28e2a6e4f163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412226141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.3412226141
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.3752392457
Short name T675
Test name
Test status
Simulation time 5889255066 ps
CPU time 14.41 seconds
Started Jul 18 06:34:25 PM PDT 24
Finished Jul 18 06:34:40 PM PDT 24
Peak memory 201592 kb
Host smart-0aa1f7ef-fe70-440b-aeb8-f7a0395c4cf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752392457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.3752392457
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.1011802666
Short name T775
Test name
Test status
Simulation time 11332782283 ps
CPU time 8.23 seconds
Started Jul 18 06:34:41 PM PDT 24
Finished Jul 18 06:34:50 PM PDT 24
Peak memory 201604 kb
Host smart-1df9bd54-31b4-40b7-899f-9cc4d100a97e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011802666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all
.1011802666
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.2545206379
Short name T318
Test name
Test status
Simulation time 226115460241 ps
CPU time 238.35 seconds
Started Jul 18 06:34:41 PM PDT 24
Finished Jul 18 06:38:41 PM PDT 24
Peak memory 210992 kb
Host smart-4ea00453-9ec0-406a-8a0a-77a2c9193795
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545206379 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.2545206379
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.3382140006
Short name T419
Test name
Test status
Simulation time 380026251 ps
CPU time 0.79 seconds
Started Jul 18 06:34:59 PM PDT 24
Finished Jul 18 06:35:02 PM PDT 24
Peak memory 201552 kb
Host smart-a7eb3ef8-ec64-4a01-8fb4-8d75defb32a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382140006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.3382140006
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.1846193042
Short name T623
Test name
Test status
Simulation time 187813559985 ps
CPU time 329.3 seconds
Started Jul 18 06:34:44 PM PDT 24
Finished Jul 18 06:40:14 PM PDT 24
Peak memory 201744 kb
Host smart-532cd9d2-aeb3-43e9-a8a1-10e736364c96
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846193042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gat
ing.1846193042
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.3722424249
Short name T208
Test name
Test status
Simulation time 412077460514 ps
CPU time 800.55 seconds
Started Jul 18 06:35:02 PM PDT 24
Finished Jul 18 06:48:24 PM PDT 24
Peak memory 201740 kb
Host smart-bc177181-6967-4d3d-a90f-0582fbe46795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722424249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.3722424249
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.2284122491
Short name T539
Test name
Test status
Simulation time 497372224064 ps
CPU time 1135.1 seconds
Started Jul 18 06:34:41 PM PDT 24
Finished Jul 18 06:53:37 PM PDT 24
Peak memory 201724 kb
Host smart-a126f854-65b2-424d-9621-67aea90409b0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284122491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interru
pt_fixed.2284122491
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.518164483
Short name T676
Test name
Test status
Simulation time 168576892596 ps
CPU time 393 seconds
Started Jul 18 06:34:42 PM PDT 24
Finished Jul 18 06:41:16 PM PDT 24
Peak memory 201748 kb
Host smart-db778bdf-8921-4495-9ebd-d287c7a828ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518164483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.518164483
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.4099409254
Short name T447
Test name
Test status
Simulation time 329890714529 ps
CPU time 746.42 seconds
Started Jul 18 06:34:41 PM PDT 24
Finished Jul 18 06:47:09 PM PDT 24
Peak memory 201808 kb
Host smart-01cdfa01-9f55-492b-914a-c9d0cedd2794
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099409254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fix
ed.4099409254
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.2554690582
Short name T288
Test name
Test status
Simulation time 206930761069 ps
CPU time 94.44 seconds
Started Jul 18 06:34:42 PM PDT 24
Finished Jul 18 06:36:18 PM PDT 24
Peak memory 201824 kb
Host smart-cc0fcbd7-7a8e-4e8f-9613-fdac4eaa3784
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554690582 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters
_wakeup.2554690582
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.657356522
Short name T473
Test name
Test status
Simulation time 206299958054 ps
CPU time 128.83 seconds
Started Jul 18 06:34:42 PM PDT 24
Finished Jul 18 06:36:52 PM PDT 24
Peak memory 201808 kb
Host smart-85b9f079-f2fe-43f3-8f3f-4eb035e4b9d4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657356522 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
adc_ctrl_filters_wakeup_fixed.657356522
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.4281848569
Short name T608
Test name
Test status
Simulation time 131382412156 ps
CPU time 414.59 seconds
Started Jul 18 06:34:59 PM PDT 24
Finished Jul 18 06:41:55 PM PDT 24
Peak memory 202120 kb
Host smart-98da9779-c8f4-4357-9d76-384be813e507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281848569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.4281848569
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.4043740121
Short name T682
Test name
Test status
Simulation time 35688839312 ps
CPU time 42.91 seconds
Started Jul 18 06:34:59 PM PDT 24
Finished Jul 18 06:35:44 PM PDT 24
Peak memory 201604 kb
Host smart-3d5362e5-f126-4892-a429-b53bf5f69296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043740121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.4043740121
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.2773376624
Short name T452
Test name
Test status
Simulation time 3029182966 ps
CPU time 2.02 seconds
Started Jul 18 06:34:57 PM PDT 24
Finished Jul 18 06:35:01 PM PDT 24
Peak memory 201616 kb
Host smart-3ff80c53-8c3f-4db8-bf19-0c536ebf5212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773376624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.2773376624
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.2809867022
Short name T729
Test name
Test status
Simulation time 5855277477 ps
CPU time 14.12 seconds
Started Jul 18 06:34:44 PM PDT 24
Finished Jul 18 06:34:59 PM PDT 24
Peak memory 201620 kb
Host smart-a6345a3a-ebb6-434a-87b0-5f45d23e5330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809867022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.2809867022
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.1561550498
Short name T667
Test name
Test status
Simulation time 97701489194 ps
CPU time 513.05 seconds
Started Jul 18 06:35:01 PM PDT 24
Finished Jul 18 06:43:36 PM PDT 24
Peak memory 210300 kb
Host smart-8a5b16ad-3239-4586-873c-ef15e53f85d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561550498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all
.1561550498
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.3739593234
Short name T189
Test name
Test status
Simulation time 281799868070 ps
CPU time 55.69 seconds
Started Jul 18 06:34:57 PM PDT 24
Finished Jul 18 06:35:55 PM PDT 24
Peak memory 210076 kb
Host smart-eb6607da-2d89-4c29-98b7-6bad9785acab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739593234 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.3739593234
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.4029603485
Short name T77
Test name
Test status
Simulation time 447182237 ps
CPU time 0.9 seconds
Started Jul 18 06:34:59 PM PDT 24
Finished Jul 18 06:35:01 PM PDT 24
Peak memory 201544 kb
Host smart-c61f08fa-a5b6-4179-8e1c-4b9bac42312d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029603485 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.4029603485
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.2726907640
Short name T758
Test name
Test status
Simulation time 168910875560 ps
CPU time 99.61 seconds
Started Jul 18 06:34:58 PM PDT 24
Finished Jul 18 06:36:38 PM PDT 24
Peak memory 201816 kb
Host smart-f7c2caa7-6442-4ae2-b176-a06914366f74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726907640 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.2726907640
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.2644909446
Short name T546
Test name
Test status
Simulation time 485812795177 ps
CPU time 532.31 seconds
Started Jul 18 06:35:02 PM PDT 24
Finished Jul 18 06:43:56 PM PDT 24
Peak memory 201652 kb
Host smart-36e50e7a-956e-4247-a009-fc26fb167551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644909446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.2644909446
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.3938251548
Short name T171
Test name
Test status
Simulation time 322971700265 ps
CPU time 773.65 seconds
Started Jul 18 06:34:58 PM PDT 24
Finished Jul 18 06:47:53 PM PDT 24
Peak memory 201732 kb
Host smart-572c2078-b39f-4b31-8f2a-857cff2b5118
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938251548 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interru
pt_fixed.3938251548
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.275686194
Short name T401
Test name
Test status
Simulation time 323087611977 ps
CPU time 185.7 seconds
Started Jul 18 06:34:57 PM PDT 24
Finished Jul 18 06:38:04 PM PDT 24
Peak memory 201680 kb
Host smart-b0011a58-c0a0-4e40-852d-ef1c93ba7b55
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=275686194 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fixe
d.275686194
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.3638641326
Short name T494
Test name
Test status
Simulation time 430013217223 ps
CPU time 1014.53 seconds
Started Jul 18 06:34:58 PM PDT 24
Finished Jul 18 06:51:54 PM PDT 24
Peak memory 201828 kb
Host smart-f7f66dbe-7a18-4066-ba4c-3be574160dbf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638641326 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters
_wakeup.3638641326
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.1227949585
Short name T379
Test name
Test status
Simulation time 204423739099 ps
CPU time 123.12 seconds
Started Jul 18 06:35:02 PM PDT 24
Finished Jul 18 06:37:07 PM PDT 24
Peak memory 201828 kb
Host smart-ee13470c-c29d-4754-95a7-e22aaf43eb4f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227949585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.adc_ctrl_filters_wakeup_fixed.1227949585
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.703541438
Short name T691
Test name
Test status
Simulation time 88724929889 ps
CPU time 434.63 seconds
Started Jul 18 06:35:02 PM PDT 24
Finished Jul 18 06:42:18 PM PDT 24
Peak memory 202204 kb
Host smart-6d4ae6aa-dd86-4c32-970d-cd7f8beb2681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703541438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.703541438
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.2352766952
Short name T695
Test name
Test status
Simulation time 39018982406 ps
CPU time 86.76 seconds
Started Jul 18 06:35:00 PM PDT 24
Finished Jul 18 06:36:28 PM PDT 24
Peak memory 201608 kb
Host smart-f5bea17d-1cd6-4565-b1fb-6697f749e1e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352766952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.2352766952
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.4203125784
Short name T766
Test name
Test status
Simulation time 4110065042 ps
CPU time 10.55 seconds
Started Jul 18 06:34:58 PM PDT 24
Finished Jul 18 06:35:11 PM PDT 24
Peak memory 201604 kb
Host smart-891d0369-3044-4fa2-84d8-672f5ad2d22b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203125784 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.4203125784
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.3957176655
Short name T450
Test name
Test status
Simulation time 6116208994 ps
CPU time 10.43 seconds
Started Jul 18 06:35:01 PM PDT 24
Finished Jul 18 06:35:13 PM PDT 24
Peak memory 201676 kb
Host smart-3b298fde-bb3f-456b-9c4d-d0f55f61bd05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957176655 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.3957176655
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.285372084
Short name T442
Test name
Test status
Simulation time 278466860609 ps
CPU time 893.25 seconds
Started Jul 18 06:35:02 PM PDT 24
Finished Jul 18 06:49:57 PM PDT 24
Peak memory 218332 kb
Host smart-a7fbaae7-c81a-456c-a246-b425d161f6ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285372084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all.
285372084
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.199954821
Short name T787
Test name
Test status
Simulation time 81499824635 ps
CPU time 97.39 seconds
Started Jul 18 06:34:59 PM PDT 24
Finished Jul 18 06:36:38 PM PDT 24
Peak memory 210064 kb
Host smart-5479598a-bda7-44d8-bbb2-946e6af68ecc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199954821 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.199954821
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.2000330424
Short name T382
Test name
Test status
Simulation time 297964465 ps
CPU time 0.95 seconds
Started Jul 18 06:35:13 PM PDT 24
Finished Jul 18 06:35:15 PM PDT 24
Peak memory 201560 kb
Host smart-3ea109c7-d494-4aff-8c32-3ffd726ecc87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000330424 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.2000330424
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.1289645074
Short name T309
Test name
Test status
Simulation time 550190946579 ps
CPU time 887.54 seconds
Started Jul 18 06:35:22 PM PDT 24
Finished Jul 18 06:50:10 PM PDT 24
Peak memory 201812 kb
Host smart-39f1b767-bf40-49a3-a31e-8ad870485e8b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289645074 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gat
ing.1289645074
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.2876782130
Short name T178
Test name
Test status
Simulation time 326724812860 ps
CPU time 85.37 seconds
Started Jul 18 06:35:13 PM PDT 24
Finished Jul 18 06:36:39 PM PDT 24
Peak memory 201748 kb
Host smart-40eb9ce0-1994-4b5d-83b8-e5f8657df923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876782130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.2876782130
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.1706702345
Short name T212
Test name
Test status
Simulation time 166674639579 ps
CPU time 404.29 seconds
Started Jul 18 06:34:59 PM PDT 24
Finished Jul 18 06:41:45 PM PDT 24
Peak memory 201820 kb
Host smart-d853c5eb-cf0d-44d8-bbaa-e3270c9e04d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706702345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.1706702345
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.1089741891
Short name T722
Test name
Test status
Simulation time 158005017629 ps
CPU time 45.97 seconds
Started Jul 18 06:34:59 PM PDT 24
Finished Jul 18 06:35:46 PM PDT 24
Peak memory 201736 kb
Host smart-b011dfcd-944d-4294-aa3a-4aa68db08e4e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089741891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interru
pt_fixed.1089741891
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.3638229176
Short name T338
Test name
Test status
Simulation time 493278481913 ps
CPU time 184.66 seconds
Started Jul 18 06:34:59 PM PDT 24
Finished Jul 18 06:38:05 PM PDT 24
Peak memory 201736 kb
Host smart-271b9326-bea4-445b-9339-a08e7fd6be0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638229176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.3638229176
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.2217913057
Short name T620
Test name
Test status
Simulation time 325715646332 ps
CPU time 173.25 seconds
Started Jul 18 06:34:59 PM PDT 24
Finished Jul 18 06:37:54 PM PDT 24
Peak memory 201772 kb
Host smart-68bb92c3-bc71-48dc-b8ee-455260074341
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217913057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fix
ed.2217913057
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.1466828115
Short name T344
Test name
Test status
Simulation time 354103706806 ps
CPU time 813.47 seconds
Started Jul 18 06:35:02 PM PDT 24
Finished Jul 18 06:48:37 PM PDT 24
Peak memory 201748 kb
Host smart-787ba8e6-dc71-461c-a995-c7066216a6d5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466828115 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters
_wakeup.1466828115
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.541963215
Short name T579
Test name
Test status
Simulation time 611793090383 ps
CPU time 660.73 seconds
Started Jul 18 06:35:16 PM PDT 24
Finished Jul 18 06:46:17 PM PDT 24
Peak memory 201652 kb
Host smart-0ef7ae44-f832-4222-9e39-408869ce5eff
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541963215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
adc_ctrl_filters_wakeup_fixed.541963215
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.2949072147
Short name T712
Test name
Test status
Simulation time 78528974838 ps
CPU time 300.77 seconds
Started Jul 18 06:35:23 PM PDT 24
Finished Jul 18 06:40:25 PM PDT 24
Peak memory 202180 kb
Host smart-5f07cb21-093b-4317-9605-a0887a6d99e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949072147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.2949072147
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.2875719152
Short name T397
Test name
Test status
Simulation time 41212893401 ps
CPU time 48.55 seconds
Started Jul 18 06:35:15 PM PDT 24
Finished Jul 18 06:36:04 PM PDT 24
Peak memory 201600 kb
Host smart-393074e6-e17b-430f-8428-83fe83470d89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875719152 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.2875719152
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.3993535739
Short name T457
Test name
Test status
Simulation time 4544403497 ps
CPU time 10.34 seconds
Started Jul 18 06:35:14 PM PDT 24
Finished Jul 18 06:35:25 PM PDT 24
Peak memory 201604 kb
Host smart-f41eb4c2-0a6d-4c18-a90d-4ffa9cfd15c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993535739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.3993535739
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.203740154
Short name T438
Test name
Test status
Simulation time 5593196625 ps
CPU time 4.03 seconds
Started Jul 18 06:35:00 PM PDT 24
Finished Jul 18 06:35:06 PM PDT 24
Peak memory 201604 kb
Host smart-b14827e3-35b0-4f08-a30a-60200d8a0bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203740154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.203740154
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.2065293043
Short name T271
Test name
Test status
Simulation time 456459017184 ps
CPU time 529.69 seconds
Started Jul 18 06:35:15 PM PDT 24
Finished Jul 18 06:44:06 PM PDT 24
Peak memory 210360 kb
Host smart-e3ec90e3-28de-4c36-9424-5d6279aba4b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065293043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all
.2065293043
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.2264266794
Short name T263
Test name
Test status
Simulation time 114965129638 ps
CPU time 181.79 seconds
Started Jul 18 06:35:14 PM PDT 24
Finished Jul 18 06:38:17 PM PDT 24
Peak memory 201916 kb
Host smart-b7911c4b-cf87-4fe6-8fcd-5353c1029dae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264266794 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.2264266794
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.1031131116
Short name T360
Test name
Test status
Simulation time 308490955 ps
CPU time 1.35 seconds
Started Jul 18 06:35:30 PM PDT 24
Finished Jul 18 06:35:32 PM PDT 24
Peak memory 201544 kb
Host smart-93aa0dd8-9e7d-438c-9e52-6928a18e8d73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031131116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.1031131116
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.2611249630
Short name T571
Test name
Test status
Simulation time 166361812863 ps
CPU time 98.69 seconds
Started Jul 18 06:35:15 PM PDT 24
Finished Jul 18 06:36:55 PM PDT 24
Peak memory 201736 kb
Host smart-dbab183d-c920-400c-b434-c0244c76e238
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611249630 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gat
ing.2611249630
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.3956820109
Short name T224
Test name
Test status
Simulation time 165584498460 ps
CPU time 106.85 seconds
Started Jul 18 06:35:22 PM PDT 24
Finished Jul 18 06:37:09 PM PDT 24
Peak memory 201756 kb
Host smart-9874854b-51bc-4043-9f81-ed7eab5e3564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956820109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.3956820109
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.2663545806
Short name T302
Test name
Test status
Simulation time 164612764686 ps
CPU time 185.18 seconds
Started Jul 18 06:35:14 PM PDT 24
Finished Jul 18 06:38:20 PM PDT 24
Peak memory 201904 kb
Host smart-fc13dd72-f36e-4d6a-b750-90d002a0b95a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663545806 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.2663545806
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.1090785678
Short name T639
Test name
Test status
Simulation time 330954374238 ps
CPU time 775.59 seconds
Started Jul 18 06:35:15 PM PDT 24
Finished Jul 18 06:48:11 PM PDT 24
Peak memory 201720 kb
Host smart-9abf0b4c-fc58-4072-9a2a-0fbf21a098f0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090785678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interru
pt_fixed.1090785678
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.2595934499
Short name T324
Test name
Test status
Simulation time 328055284220 ps
CPU time 99.01 seconds
Started Jul 18 06:35:13 PM PDT 24
Finished Jul 18 06:36:53 PM PDT 24
Peak memory 201760 kb
Host smart-c2432ef3-ed0a-47b1-aec4-7e30722901fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595934499 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.2595934499
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.4177493556
Short name T734
Test name
Test status
Simulation time 331533637281 ps
CPU time 709.29 seconds
Started Jul 18 06:35:13 PM PDT 24
Finished Jul 18 06:47:03 PM PDT 24
Peak memory 201740 kb
Host smart-e81c48e0-70bf-4615-be91-ce30c13e2fe6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177493556 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fix
ed.4177493556
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.702952262
Short name T218
Test name
Test status
Simulation time 516121240865 ps
CPU time 1159.23 seconds
Started Jul 18 06:35:14 PM PDT 24
Finished Jul 18 06:54:34 PM PDT 24
Peak memory 201896 kb
Host smart-888455e0-dd0d-4eef-964f-2cfbccc80d23
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702952262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_
wakeup.702952262
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.541895254
Short name T548
Test name
Test status
Simulation time 391379176289 ps
CPU time 166.38 seconds
Started Jul 18 06:35:22 PM PDT 24
Finished Jul 18 06:38:10 PM PDT 24
Peak memory 201744 kb
Host smart-a0428a40-b8d5-4c5f-a2c4-cfa008a70872
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541895254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
adc_ctrl_filters_wakeup_fixed.541895254
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.1962675541
Short name T697
Test name
Test status
Simulation time 119538484504 ps
CPU time 454.06 seconds
Started Jul 18 06:35:32 PM PDT 24
Finished Jul 18 06:43:07 PM PDT 24
Peak memory 202020 kb
Host smart-1ed0ed85-9acd-49d3-b63d-49d9a9bd7dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962675541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.1962675541
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.3449622559
Short name T25
Test name
Test status
Simulation time 24432352688 ps
CPU time 14.77 seconds
Started Jul 18 06:35:23 PM PDT 24
Finished Jul 18 06:35:39 PM PDT 24
Peak memory 201608 kb
Host smart-118a348a-6c2c-4781-af84-9f77d5404c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449622559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.3449622559
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.989551185
Short name T491
Test name
Test status
Simulation time 3514804050 ps
CPU time 6.22 seconds
Started Jul 18 06:35:22 PM PDT 24
Finished Jul 18 06:35:29 PM PDT 24
Peak memory 201612 kb
Host smart-841b45de-e16e-4b5a-97ab-22581aba0caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989551185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.989551185
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.3823214452
Short name T733
Test name
Test status
Simulation time 5776532857 ps
CPU time 3.47 seconds
Started Jul 18 06:35:23 PM PDT 24
Finished Jul 18 06:35:27 PM PDT 24
Peak memory 201620 kb
Host smart-bd7de9a2-0a15-4ba1-ba8d-a018fe6863c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823214452 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.3823214452
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.1733521163
Short name T684
Test name
Test status
Simulation time 351713369434 ps
CPU time 737.87 seconds
Started Jul 18 06:35:30 PM PDT 24
Finished Jul 18 06:47:48 PM PDT 24
Peak memory 201816 kb
Host smart-7afc0cea-1402-4ba4-b9ce-ec00f1196042
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733521163 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all
.1733521163
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.2746320201
Short name T506
Test name
Test status
Simulation time 312042064 ps
CPU time 1.34 seconds
Started Jul 18 06:35:49 PM PDT 24
Finished Jul 18 06:35:52 PM PDT 24
Peak memory 201548 kb
Host smart-6691e514-3298-4114-89f3-98d2d2d86f20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746320201 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.2746320201
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.1641635840
Short name T330
Test name
Test status
Simulation time 515402850061 ps
CPU time 587.93 seconds
Started Jul 18 06:35:45 PM PDT 24
Finished Jul 18 06:45:37 PM PDT 24
Peak memory 202004 kb
Host smart-a16f7b8c-fbc4-4e11-8b64-336953421fbf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641635840 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gat
ing.1641635840
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.2878334929
Short name T274
Test name
Test status
Simulation time 524333404686 ps
CPU time 181.54 seconds
Started Jul 18 06:35:50 PM PDT 24
Finished Jul 18 06:38:53 PM PDT 24
Peak memory 201748 kb
Host smart-08b41c7f-6359-4139-be3d-47403235948c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878334929 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.2878334929
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.2800781981
Short name T291
Test name
Test status
Simulation time 485985195016 ps
CPU time 299 seconds
Started Jul 18 06:35:30 PM PDT 24
Finished Jul 18 06:40:29 PM PDT 24
Peak memory 201744 kb
Host smart-a9e50527-6047-4756-9274-1fdc32db04eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800781981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.2800781981
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.3962471673
Short name T679
Test name
Test status
Simulation time 482786200160 ps
CPU time 707.32 seconds
Started Jul 18 06:35:31 PM PDT 24
Finished Jul 18 06:47:20 PM PDT 24
Peak memory 201700 kb
Host smart-579c4600-39fc-4ccf-8df3-744d71647de0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962471673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interru
pt_fixed.3962471673
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.1671514209
Short name T462
Test name
Test status
Simulation time 163487314147 ps
CPU time 351.73 seconds
Started Jul 18 06:35:31 PM PDT 24
Finished Jul 18 06:41:24 PM PDT 24
Peak memory 201740 kb
Host smart-035a0ad4-f49e-404a-aa60-a6cb600e4e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671514209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.1671514209
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.2429838463
Short name T587
Test name
Test status
Simulation time 327328181817 ps
CPU time 707.06 seconds
Started Jul 18 06:35:31 PM PDT 24
Finished Jul 18 06:47:19 PM PDT 24
Peak memory 201728 kb
Host smart-76e7a109-35b1-47e7-9ddf-fbb7f461670e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429838463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fix
ed.2429838463
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.2719320538
Short name T710
Test name
Test status
Simulation time 543884884787 ps
CPU time 167.34 seconds
Started Jul 18 06:35:31 PM PDT 24
Finished Jul 18 06:38:20 PM PDT 24
Peak memory 201748 kb
Host smart-0411f26d-6d49-4390-8784-a959a3b7c379
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719320538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters
_wakeup.2719320538
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.1576454602
Short name T511
Test name
Test status
Simulation time 151859139638 ps
CPU time 680.18 seconds
Started Jul 18 06:35:46 PM PDT 24
Finished Jul 18 06:47:10 PM PDT 24
Peak memory 202080 kb
Host smart-51f91e2c-d8a6-4d66-b2c6-05919f48c1f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576454602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.1576454602
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.2939823384
Short name T536
Test name
Test status
Simulation time 40961559484 ps
CPU time 88.45 seconds
Started Jul 18 06:35:46 PM PDT 24
Finished Jul 18 06:37:18 PM PDT 24
Peak memory 201596 kb
Host smart-606f044b-3676-40ae-8236-5f3b162ce54c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939823384 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.2939823384
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.627099154
Short name T463
Test name
Test status
Simulation time 3491159881 ps
CPU time 8.58 seconds
Started Jul 18 06:35:47 PM PDT 24
Finished Jul 18 06:35:59 PM PDT 24
Peak memory 201592 kb
Host smart-a81bfb15-ca04-48e8-9591-d26412e5a2cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627099154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.627099154
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.1062096997
Short name T693
Test name
Test status
Simulation time 5603532571 ps
CPU time 14.76 seconds
Started Jul 18 06:35:30 PM PDT 24
Finished Jul 18 06:35:46 PM PDT 24
Peak memory 201592 kb
Host smart-4ed695ae-01a6-4d20-9d53-c071bc429f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062096997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.1062096997
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.1051327380
Short name T280
Test name
Test status
Simulation time 496436797563 ps
CPU time 308.03 seconds
Started Jul 18 06:35:46 PM PDT 24
Finished Jul 18 06:40:58 PM PDT 24
Peak memory 201796 kb
Host smart-85bcec13-2d4e-4192-87a2-701e5fb7f824
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051327380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all
.1051327380
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.2034892183
Short name T14
Test name
Test status
Simulation time 26655420312 ps
CPU time 59.86 seconds
Started Jul 18 06:35:47 PM PDT 24
Finished Jul 18 06:36:50 PM PDT 24
Peak memory 210128 kb
Host smart-7327a776-cfdb-4303-9c78-7883818a7373
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034892183 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.2034892183
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.1763189803
Short name T453
Test name
Test status
Simulation time 396456127 ps
CPU time 0.83 seconds
Started Jul 18 06:36:01 PM PDT 24
Finished Jul 18 06:36:04 PM PDT 24
Peak memory 201516 kb
Host smart-bf6bd50f-b93d-4b10-9ab3-8eadea7c570d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763189803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.1763189803
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.3466514968
Short name T554
Test name
Test status
Simulation time 329543179013 ps
CPU time 340.97 seconds
Started Jul 18 06:35:47 PM PDT 24
Finished Jul 18 06:41:31 PM PDT 24
Peak memory 201636 kb
Host smart-a9d9ffd3-ad0b-40e3-b7f1-f80e6f5c66ac
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466514968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gat
ing.3466514968
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.3944207583
Short name T151
Test name
Test status
Simulation time 337529962111 ps
CPU time 375.7 seconds
Started Jul 18 06:35:46 PM PDT 24
Finished Jul 18 06:42:05 PM PDT 24
Peak memory 201784 kb
Host smart-60a12727-5016-4fa7-a2ec-3081795faec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944207583 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.3944207583
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.3335670313
Short name T441
Test name
Test status
Simulation time 166687592066 ps
CPU time 112.96 seconds
Started Jul 18 06:35:46 PM PDT 24
Finished Jul 18 06:37:42 PM PDT 24
Peak memory 201732 kb
Host smart-081e6872-dba6-42ec-98aa-4343ae75977b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335670313 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interru
pt_fixed.3335670313
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.4135351374
Short name T514
Test name
Test status
Simulation time 502287881754 ps
CPU time 1085.09 seconds
Started Jul 18 06:35:44 PM PDT 24
Finished Jul 18 06:53:52 PM PDT 24
Peak memory 201800 kb
Host smart-e2f2d267-c6a1-43c9-bc0c-831052f4baff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135351374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.4135351374
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.2916266568
Short name T794
Test name
Test status
Simulation time 483369052622 ps
CPU time 203.04 seconds
Started Jul 18 06:35:45 PM PDT 24
Finished Jul 18 06:39:11 PM PDT 24
Peak memory 201720 kb
Host smart-e6618480-1307-4731-a522-74f869702460
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916266568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fix
ed.2916266568
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.2971394383
Short name T484
Test name
Test status
Simulation time 594835279138 ps
CPU time 717 seconds
Started Jul 18 06:35:44 PM PDT 24
Finished Jul 18 06:47:44 PM PDT 24
Peak memory 201736 kb
Host smart-dd5e3bde-a5f4-4498-9434-e242f4b86f1e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971394383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.adc_ctrl_filters_wakeup_fixed.2971394383
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.2910977102
Short name T26
Test name
Test status
Simulation time 117227335028 ps
CPU time 633.41 seconds
Started Jul 18 06:36:02 PM PDT 24
Finished Jul 18 06:46:37 PM PDT 24
Peak memory 202108 kb
Host smart-991626f8-0e3a-45d1-93d0-0ce6f41b1f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910977102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.2910977102
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.3835996111
Short name T659
Test name
Test status
Simulation time 44565097842 ps
CPU time 14.29 seconds
Started Jul 18 06:36:00 PM PDT 24
Finished Jul 18 06:36:15 PM PDT 24
Peak memory 201600 kb
Host smart-d0a4ebf6-05c1-4b6c-9084-e174749d1ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835996111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.3835996111
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.2356377163
Short name T615
Test name
Test status
Simulation time 2917131344 ps
CPU time 2.47 seconds
Started Jul 18 06:36:00 PM PDT 24
Finished Jul 18 06:36:04 PM PDT 24
Peak memory 201608 kb
Host smart-ad297e03-3baf-4162-92a7-4ea7ddc285a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356377163 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.2356377163
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.2094597518
Short name T599
Test name
Test status
Simulation time 5682842151 ps
CPU time 8.67 seconds
Started Jul 18 06:35:45 PM PDT 24
Finished Jul 18 06:35:56 PM PDT 24
Peak memory 201624 kb
Host smart-c5181aca-b72b-4347-9590-8c9b84940e34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094597518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.2094597518
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.3374372477
Short name T559
Test name
Test status
Simulation time 678306964748 ps
CPU time 1686.49 seconds
Started Jul 18 06:36:00 PM PDT 24
Finished Jul 18 07:04:08 PM PDT 24
Peak memory 201868 kb
Host smart-45f7617a-a1b3-4964-a691-4658afa1691f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374372477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all
.3374372477
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.61804744
Short name T39
Test name
Test status
Simulation time 6225628455 ps
CPU time 7.91 seconds
Started Jul 18 06:36:00 PM PDT 24
Finished Jul 18 06:36:09 PM PDT 24
Peak memory 201860 kb
Host smart-2ad3872f-2dfa-47bd-b729-c0f4809b8e77
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61804744 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.61804744
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.3276786712
Short name T600
Test name
Test status
Simulation time 386653178 ps
CPU time 1.49 seconds
Started Jul 18 06:36:15 PM PDT 24
Finished Jul 18 06:36:18 PM PDT 24
Peak memory 201556 kb
Host smart-d5f4e222-b1d7-4f1b-8ee7-4a1a5c66aed3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276786712 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.3276786712
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.3232982015
Short name T133
Test name
Test status
Simulation time 518413465561 ps
CPU time 1183.58 seconds
Started Jul 18 06:36:01 PM PDT 24
Finished Jul 18 06:55:45 PM PDT 24
Peak memory 201752 kb
Host smart-7323606d-dd4d-4ea0-b6a7-f9ccfd10daf9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232982015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gat
ing.3232982015
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.208621310
Short name T296
Test name
Test status
Simulation time 484916159040 ps
CPU time 1072.39 seconds
Started Jul 18 06:36:14 PM PDT 24
Finished Jul 18 06:54:08 PM PDT 24
Peak memory 201756 kb
Host smart-25c7e074-6c0d-46fc-afd1-c50b429eecf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208621310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.208621310
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.861814040
Short name T128
Test name
Test status
Simulation time 170816739063 ps
CPU time 377.76 seconds
Started Jul 18 06:35:59 PM PDT 24
Finished Jul 18 06:42:17 PM PDT 24
Peak memory 201808 kb
Host smart-31c94b8a-5e28-4ec0-a089-5e55db9fa88b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861814040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.861814040
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.2130966879
Short name T545
Test name
Test status
Simulation time 168198477178 ps
CPU time 378.81 seconds
Started Jul 18 06:36:00 PM PDT 24
Finished Jul 18 06:42:20 PM PDT 24
Peak memory 201672 kb
Host smart-f082371e-ba79-45ef-b439-c94c01256518
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130966879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interru
pt_fixed.2130966879
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.3829780951
Short name T586
Test name
Test status
Simulation time 500696062624 ps
CPU time 303.41 seconds
Started Jul 18 06:36:00 PM PDT 24
Finished Jul 18 06:41:04 PM PDT 24
Peak memory 201784 kb
Host smart-6b87137b-3f4f-4e55-8e2c-fe63cc5c7cc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829780951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.3829780951
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.1070828843
Short name T751
Test name
Test status
Simulation time 330944746689 ps
CPU time 695.49 seconds
Started Jul 18 06:36:01 PM PDT 24
Finished Jul 18 06:47:38 PM PDT 24
Peak memory 201768 kb
Host smart-73c5a728-278f-4756-a364-dca37e16f718
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070828843 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fix
ed.1070828843
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.1990548862
Short name T95
Test name
Test status
Simulation time 340809071253 ps
CPU time 171.64 seconds
Started Jul 18 06:36:00 PM PDT 24
Finished Jul 18 06:38:52 PM PDT 24
Peak memory 201656 kb
Host smart-79bd2e84-1ead-402c-b40b-82c60b02ec09
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990548862 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters
_wakeup.1990548862
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.3000765295
Short name T650
Test name
Test status
Simulation time 607991742353 ps
CPU time 692.59 seconds
Started Jul 18 06:36:01 PM PDT 24
Finished Jul 18 06:47:35 PM PDT 24
Peak memory 201744 kb
Host smart-356200f8-09bd-47bc-a4c0-fd2ea2917ea2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000765295 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.adc_ctrl_filters_wakeup_fixed.3000765295
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.1614656780
Short name T464
Test name
Test status
Simulation time 123345006032 ps
CPU time 468.02 seconds
Started Jul 18 06:36:16 PM PDT 24
Finished Jul 18 06:44:06 PM PDT 24
Peak memory 202048 kb
Host smart-c7e20d39-6d34-4784-9d1d-f3cf9b9b9a36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614656780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.1614656780
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.1810963144
Short name T585
Test name
Test status
Simulation time 28559483591 ps
CPU time 49.01 seconds
Started Jul 18 06:36:16 PM PDT 24
Finished Jul 18 06:37:06 PM PDT 24
Peak memory 201600 kb
Host smart-2b95a415-39f0-4f48-b06f-53007eb5a90b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810963144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.1810963144
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.1355437815
Short name T584
Test name
Test status
Simulation time 2504328746 ps
CPU time 7.11 seconds
Started Jul 18 06:36:14 PM PDT 24
Finished Jul 18 06:36:23 PM PDT 24
Peak memory 201676 kb
Host smart-dfd912bc-284c-4b4c-ad06-417b39f1f455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355437815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.1355437815
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.3717942050
Short name T749
Test name
Test status
Simulation time 6135992159 ps
CPU time 4.34 seconds
Started Jul 18 06:36:01 PM PDT 24
Finished Jul 18 06:36:08 PM PDT 24
Peak memory 201620 kb
Host smart-f8c3686f-7954-48f2-a32d-83f362027124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717942050 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.3717942050
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.4081973647
Short name T130
Test name
Test status
Simulation time 497249800145 ps
CPU time 727.21 seconds
Started Jul 18 06:36:15 PM PDT 24
Finished Jul 18 06:48:24 PM PDT 24
Peak memory 201636 kb
Host smart-af280a7b-184b-4812-97fc-44fe43bf160e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081973647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all
.4081973647
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.756189584
Short name T220
Test name
Test status
Simulation time 147215150736 ps
CPU time 227.63 seconds
Started Jul 18 06:36:14 PM PDT 24
Finished Jul 18 06:40:04 PM PDT 24
Peak memory 218572 kb
Host smart-dc9eb1cd-9c63-4e07-84af-02cb7e2b0fe7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756189584 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.756189584
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.1043400999
Short name T372
Test name
Test status
Simulation time 491304082 ps
CPU time 0.73 seconds
Started Jul 18 06:36:34 PM PDT 24
Finished Jul 18 06:36:35 PM PDT 24
Peak memory 201548 kb
Host smart-38211bcb-2298-4ee5-986f-0e10f9037131
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043400999 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.1043400999
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.2945773321
Short name T205
Test name
Test status
Simulation time 197584709470 ps
CPU time 230.24 seconds
Started Jul 18 06:36:14 PM PDT 24
Finished Jul 18 06:40:06 PM PDT 24
Peak memory 201812 kb
Host smart-886d9cca-a849-413d-8d23-1c73b7aab27d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945773321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gat
ing.2945773321
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.1570565654
Short name T317
Test name
Test status
Simulation time 598315817031 ps
CPU time 1371.08 seconds
Started Jul 18 06:36:13 PM PDT 24
Finished Jul 18 06:59:06 PM PDT 24
Peak memory 201824 kb
Host smart-08ac3746-22ad-4902-a896-1dc62d5f3998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570565654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.1570565654
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.2407930074
Short name T764
Test name
Test status
Simulation time 158581497458 ps
CPU time 59.04 seconds
Started Jul 18 06:36:15 PM PDT 24
Finished Jul 18 06:37:16 PM PDT 24
Peak memory 201760 kb
Host smart-39f4247c-9a55-4da4-abdb-8eae59d6cb60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407930074 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.2407930074
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.946102049
Short name T489
Test name
Test status
Simulation time 328481939101 ps
CPU time 374.99 seconds
Started Jul 18 06:36:14 PM PDT 24
Finished Jul 18 06:42:31 PM PDT 24
Peak memory 201728 kb
Host smart-54b503fc-fbd4-449a-87d3-69363fa63b84
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=946102049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrup
t_fixed.946102049
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.609147470
Short name T662
Test name
Test status
Simulation time 166412964556 ps
CPU time 105.75 seconds
Started Jul 18 06:36:17 PM PDT 24
Finished Jul 18 06:38:03 PM PDT 24
Peak memory 201820 kb
Host smart-93da2866-d76a-4570-b739-9e3f080c8938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609147470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.609147470
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.3229475869
Short name T789
Test name
Test status
Simulation time 164084829502 ps
CPU time 34.78 seconds
Started Jul 18 06:36:15 PM PDT 24
Finished Jul 18 06:36:51 PM PDT 24
Peak memory 201740 kb
Host smart-95cc119e-450d-4c92-a2d3-32a4096cd1b2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229475869 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fix
ed.3229475869
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.271609360
Short name T164
Test name
Test status
Simulation time 344054159092 ps
CPU time 204.95 seconds
Started Jul 18 06:36:14 PM PDT 24
Finished Jul 18 06:39:41 PM PDT 24
Peak memory 201816 kb
Host smart-f5cab799-811a-4990-98b0-f888f49faf9a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271609360 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_
wakeup.271609360
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.3477261629
Short name T485
Test name
Test status
Simulation time 598384843534 ps
CPU time 354.51 seconds
Started Jul 18 06:36:14 PM PDT 24
Finished Jul 18 06:42:11 PM PDT 24
Peak memory 201720 kb
Host smart-f6d73821-e721-463a-bd5a-375586817594
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477261629 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.adc_ctrl_filters_wakeup_fixed.3477261629
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.1642374221
Short name T741
Test name
Test status
Simulation time 131341489623 ps
CPU time 517.9 seconds
Started Jul 18 06:36:14 PM PDT 24
Finished Jul 18 06:44:54 PM PDT 24
Peak memory 202076 kb
Host smart-d340991f-4670-4986-93b1-9d119e68fa26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642374221 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.1642374221
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.813736523
Short name T472
Test name
Test status
Simulation time 25091580651 ps
CPU time 58.5 seconds
Started Jul 18 06:36:13 PM PDT 24
Finished Jul 18 06:37:13 PM PDT 24
Peak memory 201596 kb
Host smart-9de595ec-dbc6-46f2-afc4-3e9a1795dbb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813736523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.813736523
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.3081841668
Short name T93
Test name
Test status
Simulation time 3880716009 ps
CPU time 2.9 seconds
Started Jul 18 06:36:14 PM PDT 24
Finished Jul 18 06:36:19 PM PDT 24
Peak memory 201604 kb
Host smart-45618746-0c32-40f3-800a-f27157336a9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081841668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.3081841668
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.750229917
Short name T756
Test name
Test status
Simulation time 5838278358 ps
CPU time 4.31 seconds
Started Jul 18 06:36:14 PM PDT 24
Finished Jul 18 06:36:20 PM PDT 24
Peak memory 201604 kb
Host smart-e8d8e54d-ab90-4fed-90ad-b833df9b6fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750229917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.750229917
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.1958391713
Short name T488
Test name
Test status
Simulation time 61890564428 ps
CPU time 9.26 seconds
Started Jul 18 06:36:35 PM PDT 24
Finished Jul 18 06:36:45 PM PDT 24
Peak memory 201596 kb
Host smart-340b953e-a3e4-49fc-9bd9-547b197e14bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958391713 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all
.1958391713
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.2793274906
Short name T800
Test name
Test status
Simulation time 415059347 ps
CPU time 1.35 seconds
Started Jul 18 06:36:50 PM PDT 24
Finished Jul 18 06:36:53 PM PDT 24
Peak memory 201716 kb
Host smart-7ad76c09-048c-4f18-abaf-a7862e31ce62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793274906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.2793274906
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.3597866600
Short name T286
Test name
Test status
Simulation time 514903708288 ps
CPU time 553.15 seconds
Started Jul 18 06:36:33 PM PDT 24
Finished Jul 18 06:45:47 PM PDT 24
Peak memory 201812 kb
Host smart-1ac6e554-0d7a-4780-bf0f-98d0e951c5dc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597866600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gat
ing.3597866600
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.1694222734
Short name T255
Test name
Test status
Simulation time 335903881404 ps
CPU time 730.68 seconds
Started Jul 18 06:36:34 PM PDT 24
Finished Jul 18 06:48:46 PM PDT 24
Peak memory 201788 kb
Host smart-e77b8376-2f98-4c47-94d7-ad5234602fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694222734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.1694222734
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.3976660697
Short name T732
Test name
Test status
Simulation time 329589825525 ps
CPU time 187.64 seconds
Started Jul 18 06:36:32 PM PDT 24
Finished Jul 18 06:39:41 PM PDT 24
Peak memory 201724 kb
Host smart-873e3a10-ba0b-4565-896b-54a4242ee78b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976660697 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interru
pt_fixed.3976660697
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.1044847834
Short name T141
Test name
Test status
Simulation time 337979809864 ps
CPU time 392.73 seconds
Started Jul 18 06:36:35 PM PDT 24
Finished Jul 18 06:43:09 PM PDT 24
Peak memory 201812 kb
Host smart-22c2bfa7-76d9-42de-b283-8a855955fb38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044847834 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.1044847834
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.2434070754
Short name T416
Test name
Test status
Simulation time 167290702973 ps
CPU time 385.56 seconds
Started Jul 18 06:36:34 PM PDT 24
Finished Jul 18 06:43:01 PM PDT 24
Peak memory 201756 kb
Host smart-c84192af-9b4e-4f1c-9b59-616c7c61ad04
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434070754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fix
ed.2434070754
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.3012384783
Short name T731
Test name
Test status
Simulation time 202911725212 ps
CPU time 115.55 seconds
Started Jul 18 06:36:34 PM PDT 24
Finished Jul 18 06:38:31 PM PDT 24
Peak memory 201832 kb
Host smart-64337123-09ec-4016-a3be-8dcfb0824eaa
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012384783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters
_wakeup.3012384783
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.777189462
Short name T578
Test name
Test status
Simulation time 187957680892 ps
CPU time 106.88 seconds
Started Jul 18 06:36:35 PM PDT 24
Finished Jul 18 06:38:23 PM PDT 24
Peak memory 201736 kb
Host smart-7588795e-9d11-4873-b961-73e09b66ba30
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777189462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
adc_ctrl_filters_wakeup_fixed.777189462
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.1536103056
Short name T202
Test name
Test status
Simulation time 93639978582 ps
CPU time 331.65 seconds
Started Jul 18 06:36:34 PM PDT 24
Finished Jul 18 06:42:07 PM PDT 24
Peak memory 202124 kb
Host smart-9ac67212-9f80-483a-ad4b-2cae1bdabe15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536103056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.1536103056
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.2341752752
Short name T499
Test name
Test status
Simulation time 30977597543 ps
CPU time 28.65 seconds
Started Jul 18 06:36:34 PM PDT 24
Finished Jul 18 06:37:04 PM PDT 24
Peak memory 201600 kb
Host smart-ea8c6bda-b3c6-414c-bd17-79b1cfb2a944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341752752 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.2341752752
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.1977321896
Short name T381
Test name
Test status
Simulation time 4035199054 ps
CPU time 3.58 seconds
Started Jul 18 06:36:33 PM PDT 24
Finished Jul 18 06:36:37 PM PDT 24
Peak memory 201604 kb
Host smart-3df8c651-8251-4733-bc62-1be542b9d88b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977321896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.1977321896
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.3023292787
Short name T487
Test name
Test status
Simulation time 5640082416 ps
CPU time 13.81 seconds
Started Jul 18 06:36:34 PM PDT 24
Finished Jul 18 06:36:48 PM PDT 24
Peak memory 201592 kb
Host smart-9c63a8b6-bd3b-466f-9e05-05792a2b923d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023292787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.3023292787
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.291571954
Short name T345
Test name
Test status
Simulation time 90598989406 ps
CPU time 53.07 seconds
Started Jul 18 06:36:52 PM PDT 24
Finished Jul 18 06:37:46 PM PDT 24
Peak memory 210136 kb
Host smart-4260a328-4b45-4d5d-8dac-0b1eadf693fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291571954 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.291571954
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.491357753
Short name T376
Test name
Test status
Simulation time 324459840 ps
CPU time 1.15 seconds
Started Jul 18 06:32:03 PM PDT 24
Finished Jul 18 06:32:07 PM PDT 24
Peak memory 201620 kb
Host smart-ae613d64-d1fc-4a94-9c87-c8c863cc79d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491357753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.491357753
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.3940492695
Short name T301
Test name
Test status
Simulation time 350690459381 ps
CPU time 197.1 seconds
Started Jul 18 06:31:46 PM PDT 24
Finished Jul 18 06:35:08 PM PDT 24
Peak memory 201636 kb
Host smart-f23325d9-5c66-420b-9aac-8056ffb7d69e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940492695 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gati
ng.3940492695
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.2919645719
Short name T619
Test name
Test status
Simulation time 499098426509 ps
CPU time 1078.51 seconds
Started Jul 18 06:31:46 PM PDT 24
Finished Jul 18 06:49:48 PM PDT 24
Peak memory 201660 kb
Host smart-192899ae-9ef6-48aa-99d2-6ea42909d240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919645719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.2919645719
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.3787578654
Short name T455
Test name
Test status
Simulation time 493333843606 ps
CPU time 291.41 seconds
Started Jul 18 06:31:46 PM PDT 24
Finished Jul 18 06:36:42 PM PDT 24
Peak memory 201732 kb
Host smart-588a8846-8df1-4375-ab45-d98667f4cd16
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787578654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrup
t_fixed.3787578654
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.2494262887
Short name T154
Test name
Test status
Simulation time 168201488749 ps
CPU time 399.32 seconds
Started Jul 18 06:31:47 PM PDT 24
Finished Jul 18 06:38:30 PM PDT 24
Peak memory 201824 kb
Host smart-1f809b56-8e02-42ea-ad58-da3cd7baa6e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494262887 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.2494262887
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.3362371085
Short name T404
Test name
Test status
Simulation time 172267663055 ps
CPU time 97.95 seconds
Started Jul 18 06:31:47 PM PDT 24
Finished Jul 18 06:33:29 PM PDT 24
Peak memory 201740 kb
Host smart-1134ab55-ffc9-436b-9be6-62516d578a64
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362371085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixe
d.3362371085
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.698669545
Short name T337
Test name
Test status
Simulation time 525367009789 ps
CPU time 288.15 seconds
Started Jul 18 06:31:43 PM PDT 24
Finished Jul 18 06:36:34 PM PDT 24
Peak memory 201752 kb
Host smart-bd65e87e-36f6-47b1-a571-a49c8b38c473
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698669545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_w
akeup.698669545
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.3931206771
Short name T544
Test name
Test status
Simulation time 409415459000 ps
CPU time 224.52 seconds
Started Jul 18 06:31:43 PM PDT 24
Finished Jul 18 06:35:31 PM PDT 24
Peak memory 201804 kb
Host smart-eda7ffba-97d0-4d74-83cc-86217e9292f2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931206771 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
adc_ctrl_filters_wakeup_fixed.3931206771
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.4186139059
Short name T199
Test name
Test status
Simulation time 102819500585 ps
CPU time 522.55 seconds
Started Jul 18 06:32:02 PM PDT 24
Finished Jul 18 06:40:46 PM PDT 24
Peak memory 202148 kb
Host smart-1ea07a52-2c41-4ee9-b876-ba8d47c4a0b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186139059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.4186139059
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.3716979906
Short name T377
Test name
Test status
Simulation time 42429737553 ps
CPU time 92.47 seconds
Started Jul 18 06:32:01 PM PDT 24
Finished Jul 18 06:33:35 PM PDT 24
Peak memory 201600 kb
Host smart-da2691a3-0ebf-42e9-96de-311256c1440d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716979906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.3716979906
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.1589846264
Short name T383
Test name
Test status
Simulation time 4537065552 ps
CPU time 11.29 seconds
Started Jul 18 06:31:50 PM PDT 24
Finished Jul 18 06:32:04 PM PDT 24
Peak memory 201568 kb
Host smart-624d1633-abb2-40b8-be16-7e5a3875f581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589846264 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.1589846264
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.1849589019
Short name T86
Test name
Test status
Simulation time 3935467885 ps
CPU time 2.73 seconds
Started Jul 18 06:32:06 PM PDT 24
Finished Jul 18 06:32:14 PM PDT 24
Peak memory 217208 kb
Host smart-3875cb5d-deb9-4962-9b00-8e01a0cfba9f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849589019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.1849589019
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.234070054
Short name T34
Test name
Test status
Simulation time 5907314388 ps
CPU time 4.23 seconds
Started Jul 18 06:31:46 PM PDT 24
Finished Jul 18 06:31:55 PM PDT 24
Peak memory 201492 kb
Host smart-b137a516-a90e-4c6a-872d-30ebcf7588f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234070054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.234070054
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.3396286987
Short name T352
Test name
Test status
Simulation time 412921688725 ps
CPU time 1241.47 seconds
Started Jul 18 06:32:04 PM PDT 24
Finished Jul 18 06:52:48 PM PDT 24
Peak memory 210308 kb
Host smart-7850a6e1-411e-4f97-ad88-28aadba53818
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396286987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.
3396286987
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.4170097910
Short name T699
Test name
Test status
Simulation time 395682831686 ps
CPU time 487.26 seconds
Started Jul 18 06:32:08 PM PDT 24
Finished Jul 18 06:40:20 PM PDT 24
Peak memory 210528 kb
Host smart-032fcdef-9473-42d4-a866-147be2325f73
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170097910 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.4170097910
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.1297001283
Short name T415
Test name
Test status
Simulation time 443781268 ps
CPU time 1.1 seconds
Started Jul 18 06:36:51 PM PDT 24
Finished Jul 18 06:36:53 PM PDT 24
Peak memory 201540 kb
Host smart-5f768cc2-4328-4d6c-89b2-9c5f1609c7fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297001283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.1297001283
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.2510737297
Short name T486
Test name
Test status
Simulation time 171807454942 ps
CPU time 377.83 seconds
Started Jul 18 06:36:52 PM PDT 24
Finished Jul 18 06:43:11 PM PDT 24
Peak memory 201760 kb
Host smart-54125bf0-3987-4430-8f61-864803b9fdeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510737297 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.2510737297
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.923755847
Short name T727
Test name
Test status
Simulation time 161364307097 ps
CPU time 285.15 seconds
Started Jul 18 06:36:50 PM PDT 24
Finished Jul 18 06:41:36 PM PDT 24
Peak memory 201724 kb
Host smart-a32845a9-0589-4e86-a7fe-dec8dffcc5ee
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=923755847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrup
t_fixed.923755847
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.2337401169
Short name T289
Test name
Test status
Simulation time 159651955760 ps
CPU time 166.86 seconds
Started Jul 18 06:36:49 PM PDT 24
Finished Jul 18 06:39:37 PM PDT 24
Peak memory 201772 kb
Host smart-16eb4d3f-6fd5-4e99-a3d0-a2cc0bea45da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337401169 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.2337401169
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.3568705961
Short name T583
Test name
Test status
Simulation time 162976814787 ps
CPU time 31.08 seconds
Started Jul 18 06:36:51 PM PDT 24
Finished Jul 18 06:37:24 PM PDT 24
Peak memory 201756 kb
Host smart-060af6b4-bdc8-460e-b428-3130b06f4da4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568705961 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fix
ed.3568705961
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.601482167
Short name T163
Test name
Test status
Simulation time 544523834770 ps
CPU time 363.13 seconds
Started Jul 18 06:36:50 PM PDT 24
Finished Jul 18 06:42:54 PM PDT 24
Peak memory 201724 kb
Host smart-e52e2178-b737-441c-af01-3d0144f0b635
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601482167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_
wakeup.601482167
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.950632696
Short name T359
Test name
Test status
Simulation time 390771707835 ps
CPU time 405.65 seconds
Started Jul 18 06:36:50 PM PDT 24
Finished Jul 18 06:43:37 PM PDT 24
Peak memory 201716 kb
Host smart-e20ac64c-5634-44f5-98b5-3d317fc1030e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950632696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
adc_ctrl_filters_wakeup_fixed.950632696
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.2679611837
Short name T439
Test name
Test status
Simulation time 59937134815 ps
CPU time 261.48 seconds
Started Jul 18 06:36:50 PM PDT 24
Finished Jul 18 06:41:13 PM PDT 24
Peak memory 202088 kb
Host smart-9cc4d796-e431-4760-9327-59ca4be67297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679611837 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.2679611837
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.3558631561
Short name T702
Test name
Test status
Simulation time 25864089080 ps
CPU time 16.59 seconds
Started Jul 18 06:36:50 PM PDT 24
Finished Jul 18 06:37:08 PM PDT 24
Peak memory 201680 kb
Host smart-bf825794-1550-4810-9819-0dc200efa2fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558631561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.3558631561
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.706472613
Short name T387
Test name
Test status
Simulation time 4788785179 ps
CPU time 3.4 seconds
Started Jul 18 06:36:49 PM PDT 24
Finished Jul 18 06:36:54 PM PDT 24
Peak memory 201608 kb
Host smart-8db27eb8-1f00-47d7-ac1b-7e893700f5cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706472613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.706472613
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.4186480849
Short name T418
Test name
Test status
Simulation time 5921515372 ps
CPU time 2.24 seconds
Started Jul 18 06:36:53 PM PDT 24
Finished Jul 18 06:36:57 PM PDT 24
Peak memory 201392 kb
Host smart-dee31008-c844-4121-b4c6-c93789cbd958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186480849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.4186480849
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.1976072249
Short name T562
Test name
Test status
Simulation time 752445321193 ps
CPU time 1912.22 seconds
Started Jul 18 06:36:51 PM PDT 24
Finished Jul 18 07:08:45 PM PDT 24
Peak memory 210428 kb
Host smart-0a853a04-c39b-41af-a39c-f9afa256789b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976072249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all
.1976072249
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.3606138026
Short name T41
Test name
Test status
Simulation time 73973056089 ps
CPU time 195.27 seconds
Started Jul 18 06:36:50 PM PDT 24
Finished Jul 18 06:40:06 PM PDT 24
Peak memory 218580 kb
Host smart-f4e1f163-6c3c-4a2b-8050-c52f84cb8dc9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606138026 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.3606138026
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.3413186523
Short name T509
Test name
Test status
Simulation time 331093551 ps
CPU time 0.81 seconds
Started Jul 18 06:37:05 PM PDT 24
Finished Jul 18 06:37:08 PM PDT 24
Peak memory 201536 kb
Host smart-e81728ad-a6a7-4f9c-9f84-a5749fba9f00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413186523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.3413186523
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.637832905
Short name T210
Test name
Test status
Simulation time 174718300299 ps
CPU time 160.7 seconds
Started Jul 18 06:37:06 PM PDT 24
Finished Jul 18 06:39:49 PM PDT 24
Peak memory 201696 kb
Host smart-4fa7542a-11fb-41c7-9714-14e9f3e6e590
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637832905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gati
ng.637832905
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.2282739566
Short name T632
Test name
Test status
Simulation time 201564331686 ps
CPU time 127.31 seconds
Started Jul 18 06:37:06 PM PDT 24
Finished Jul 18 06:39:15 PM PDT 24
Peak memory 201660 kb
Host smart-efa537ac-36a1-4748-bfac-c921960e1c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282739566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.2282739566
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.3631241559
Short name T618
Test name
Test status
Simulation time 486248615150 ps
CPU time 1148.49 seconds
Started Jul 18 06:37:05 PM PDT 24
Finished Jul 18 06:56:16 PM PDT 24
Peak memory 201816 kb
Host smart-31201bb2-9399-4380-a348-81fb94bfb9b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631241559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.3631241559
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.2495593326
Short name T648
Test name
Test status
Simulation time 496616984133 ps
CPU time 1214.82 seconds
Started Jul 18 06:37:05 PM PDT 24
Finished Jul 18 06:57:22 PM PDT 24
Peak memory 201732 kb
Host smart-dfe91236-b8ce-42e3-a798-bce8d192099c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495593326 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interru
pt_fixed.2495593326
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.3799284708
Short name T308
Test name
Test status
Simulation time 327612272316 ps
CPU time 680.3 seconds
Started Jul 18 06:36:50 PM PDT 24
Finished Jul 18 06:48:11 PM PDT 24
Peak memory 201752 kb
Host smart-115b8daf-3275-494c-b827-66fbd7bf460e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799284708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.3799284708
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.2994855254
Short name T395
Test name
Test status
Simulation time 162776615829 ps
CPU time 92.23 seconds
Started Jul 18 06:37:06 PM PDT 24
Finished Jul 18 06:38:40 PM PDT 24
Peak memory 201744 kb
Host smart-3dc21635-0699-497b-ba39-ebadc229e469
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994855254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fix
ed.2994855254
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.2248329951
Short name T762
Test name
Test status
Simulation time 406239750580 ps
CPU time 222.95 seconds
Started Jul 18 06:37:10 PM PDT 24
Finished Jul 18 06:40:54 PM PDT 24
Peak memory 201744 kb
Host smart-31c8a0c0-82f3-49a5-8188-f047e64d833a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248329951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.adc_ctrl_filters_wakeup_fixed.2248329951
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.3734385723
Short name T678
Test name
Test status
Simulation time 120625895364 ps
CPU time 616.76 seconds
Started Jul 18 06:37:05 PM PDT 24
Finished Jul 18 06:47:24 PM PDT 24
Peak memory 202204 kb
Host smart-244174ee-0b16-44ab-93e2-36dd0fa71d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734385723 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.3734385723
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.2976066857
Short name T721
Test name
Test status
Simulation time 44761677262 ps
CPU time 97.18 seconds
Started Jul 18 06:37:10 PM PDT 24
Finished Jul 18 06:38:48 PM PDT 24
Peak memory 201620 kb
Host smart-61e94d4d-10cf-4f39-8260-8638ddd3c3d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976066857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.2976066857
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.3429655444
Short name T174
Test name
Test status
Simulation time 5103309363 ps
CPU time 12.22 seconds
Started Jul 18 06:37:06 PM PDT 24
Finished Jul 18 06:37:20 PM PDT 24
Peak memory 201500 kb
Host smart-e29eeed9-d5ed-46fe-ba14-0fcad4b26247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429655444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.3429655444
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.3949110329
Short name T361
Test name
Test status
Simulation time 5891628575 ps
CPU time 14.27 seconds
Started Jul 18 06:36:53 PM PDT 24
Finished Jul 18 06:37:09 PM PDT 24
Peak memory 201340 kb
Host smart-554c72e9-839c-41eb-80b1-0a32476db09e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949110329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.3949110329
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.1639069977
Short name T561
Test name
Test status
Simulation time 366130031752 ps
CPU time 921.2 seconds
Started Jul 18 06:37:08 PM PDT 24
Finished Jul 18 06:52:31 PM PDT 24
Peak memory 201728 kb
Host smart-de0ba2c9-cb0d-4acd-b027-14a3272e44a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639069977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all
.1639069977
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.455924493
Short name T221
Test name
Test status
Simulation time 123796765088 ps
CPU time 150.98 seconds
Started Jul 18 06:37:05 PM PDT 24
Finished Jul 18 06:39:38 PM PDT 24
Peak memory 211880 kb
Host smart-314b5bc8-4503-41d7-b06a-d387600df97f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455924493 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.455924493
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.946705021
Short name T661
Test name
Test status
Simulation time 488271526 ps
CPU time 0.89 seconds
Started Jul 18 06:37:17 PM PDT 24
Finished Jul 18 06:37:19 PM PDT 24
Peak memory 201544 kb
Host smart-1d40e62b-01b8-4dfc-9eb1-454916d149f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946705021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.946705021
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.2435565040
Short name T142
Test name
Test status
Simulation time 182816514582 ps
CPU time 223.94 seconds
Started Jul 18 06:37:04 PM PDT 24
Finished Jul 18 06:40:49 PM PDT 24
Peak memory 201804 kb
Host smart-fa7ed897-78f0-45ad-af73-d89b411d07ae
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435565040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gat
ing.2435565040
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.1320460368
Short name T594
Test name
Test status
Simulation time 159675289792 ps
CPU time 170.66 seconds
Started Jul 18 06:37:19 PM PDT 24
Finished Jul 18 06:40:11 PM PDT 24
Peak memory 201744 kb
Host smart-a448de96-1a51-4907-977b-532f4fa4dca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320460368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.1320460368
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.1005160234
Short name T258
Test name
Test status
Simulation time 166978245591 ps
CPU time 375.87 seconds
Started Jul 18 06:37:05 PM PDT 24
Finished Jul 18 06:43:24 PM PDT 24
Peak memory 201892 kb
Host smart-6f2d5535-3410-4db4-9232-32ff2d8cbd40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005160234 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.1005160234
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.2805879998
Short name T730
Test name
Test status
Simulation time 167773495722 ps
CPU time 375.57 seconds
Started Jul 18 06:37:09 PM PDT 24
Finished Jul 18 06:43:26 PM PDT 24
Peak memory 201724 kb
Host smart-9bed1605-ed36-4716-880c-b59610005b26
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805879998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interru
pt_fixed.2805879998
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.3261094805
Short name T666
Test name
Test status
Simulation time 324387092364 ps
CPU time 380.18 seconds
Started Jul 18 06:37:10 PM PDT 24
Finished Jul 18 06:43:31 PM PDT 24
Peak memory 201764 kb
Host smart-2becf32c-3a83-4e47-9386-0f19ed104907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261094805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.3261094805
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.4240602349
Short name T371
Test name
Test status
Simulation time 164640734896 ps
CPU time 386.33 seconds
Started Jul 18 06:37:04 PM PDT 24
Finished Jul 18 06:43:32 PM PDT 24
Peak memory 201764 kb
Host smart-935cd41b-471c-4687-b695-598c50779605
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240602349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fix
ed.4240602349
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.2200359053
Short name T144
Test name
Test status
Simulation time 177278986499 ps
CPU time 106.33 seconds
Started Jul 18 06:37:05 PM PDT 24
Finished Jul 18 06:38:54 PM PDT 24
Peak memory 201760 kb
Host smart-aef70d67-85b8-49c2-b22c-79b28928deae
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200359053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters
_wakeup.2200359053
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.3292569035
Short name T565
Test name
Test status
Simulation time 417572291196 ps
CPU time 259.79 seconds
Started Jul 18 06:37:10 PM PDT 24
Finished Jul 18 06:41:30 PM PDT 24
Peak memory 201704 kb
Host smart-910648c8-f469-4ec4-9260-35c3ce6e3b45
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292569035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.adc_ctrl_filters_wakeup_fixed.3292569035
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.1513017618
Short name T10
Test name
Test status
Simulation time 103173697422 ps
CPU time 578.06 seconds
Started Jul 18 06:37:19 PM PDT 24
Finished Jul 18 06:46:58 PM PDT 24
Peak memory 202132 kb
Host smart-9f1e609f-f6ae-4c22-b3b7-ef99fe67d172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513017618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.1513017618
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.2500108966
Short name T421
Test name
Test status
Simulation time 42747435009 ps
CPU time 98.97 seconds
Started Jul 18 06:37:19 PM PDT 24
Finished Jul 18 06:38:58 PM PDT 24
Peak memory 201608 kb
Host smart-e0e01816-a1a4-43eb-9737-62e374da6537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500108966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.2500108966
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.358036175
Short name T160
Test name
Test status
Simulation time 3013956516 ps
CPU time 3.61 seconds
Started Jul 18 06:37:18 PM PDT 24
Finished Jul 18 06:37:23 PM PDT 24
Peak memory 201612 kb
Host smart-622161ea-34eb-463b-b038-fbcd03cb2958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358036175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.358036175
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.1235168538
Short name T664
Test name
Test status
Simulation time 5862060390 ps
CPU time 4.19 seconds
Started Jul 18 06:37:06 PM PDT 24
Finished Jul 18 06:37:12 PM PDT 24
Peak memory 201600 kb
Host smart-2d6bb6e2-f1bd-4f4b-884e-20ed02b4e393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235168538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.1235168538
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.3205930573
Short name T267
Test name
Test status
Simulation time 301035088803 ps
CPU time 538.47 seconds
Started Jul 18 06:37:20 PM PDT 24
Finished Jul 18 06:46:19 PM PDT 24
Peak memory 212724 kb
Host smart-3274a6b5-f4b8-4868-8efe-be4699fd2d4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205930573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all
.3205930573
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.1319623734
Short name T13
Test name
Test status
Simulation time 175578589390 ps
CPU time 110.79 seconds
Started Jul 18 06:37:20 PM PDT 24
Finished Jul 18 06:39:12 PM PDT 24
Peak memory 210588 kb
Host smart-05988070-2f96-4d72-bd6c-0e5479218079
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319623734 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.1319623734
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.1788184657
Short name T596
Test name
Test status
Simulation time 329854275 ps
CPU time 1.4 seconds
Started Jul 18 06:37:33 PM PDT 24
Finished Jul 18 06:37:36 PM PDT 24
Peak memory 201548 kb
Host smart-3731ba28-b0f6-4017-a031-eb06e86f0985
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788184657 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.1788184657
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.2065859367
Short name T227
Test name
Test status
Simulation time 164375327824 ps
CPU time 381.79 seconds
Started Jul 18 06:37:34 PM PDT 24
Finished Jul 18 06:43:57 PM PDT 24
Peak memory 201736 kb
Host smart-da98fbe9-c87e-40f8-b815-bb7449fd4a74
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065859367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gat
ing.2065859367
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.4043839814
Short name T241
Test name
Test status
Simulation time 330086025901 ps
CPU time 210.31 seconds
Started Jul 18 06:37:18 PM PDT 24
Finished Jul 18 06:40:49 PM PDT 24
Peak memory 201752 kb
Host smart-376c2973-9780-4eb3-a517-75e6b8fbedce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043839814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.4043839814
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.794375727
Short name T645
Test name
Test status
Simulation time 491747528672 ps
CPU time 594.55 seconds
Started Jul 18 06:37:18 PM PDT 24
Finished Jul 18 06:47:14 PM PDT 24
Peak memory 201692 kb
Host smart-faee7489-555b-449b-a8b6-17c73b645f0a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=794375727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrup
t_fixed.794375727
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.2620252661
Short name T314
Test name
Test status
Simulation time 167506018703 ps
CPU time 101.05 seconds
Started Jul 18 06:37:21 PM PDT 24
Finished Jul 18 06:39:03 PM PDT 24
Peak memory 201764 kb
Host smart-5c3e8ea5-a7d1-4fd5-9ef6-f3f39eb9bffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620252661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.2620252661
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.663662538
Short name T602
Test name
Test status
Simulation time 322625404927 ps
CPU time 211.99 seconds
Started Jul 18 06:37:18 PM PDT 24
Finished Jul 18 06:40:51 PM PDT 24
Peak memory 201796 kb
Host smart-64ea4bf7-e6db-4ea2-8190-b6dc5e4d95fa
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=663662538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fixe
d.663662538
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.2606773283
Short name T516
Test name
Test status
Simulation time 614253413742 ps
CPU time 280.75 seconds
Started Jul 18 06:37:35 PM PDT 24
Finished Jul 18 06:42:17 PM PDT 24
Peak memory 201728 kb
Host smart-92ff1866-0190-43db-b1dc-26d7a5da9f0b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606773283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.adc_ctrl_filters_wakeup_fixed.2606773283
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.3757932910
Short name T740
Test name
Test status
Simulation time 128414641988 ps
CPU time 418.2 seconds
Started Jul 18 06:37:33 PM PDT 24
Finished Jul 18 06:44:33 PM PDT 24
Peak memory 202172 kb
Host smart-a0e293db-b998-474a-9253-0bc9efe98878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757932910 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.3757932910
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.881933379
Short name T785
Test name
Test status
Simulation time 41478724522 ps
CPU time 96.14 seconds
Started Jul 18 06:37:33 PM PDT 24
Finished Jul 18 06:39:11 PM PDT 24
Peak memory 201620 kb
Host smart-e535b82d-a053-4a5a-a16c-97cdf2c5b4f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881933379 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.881933379
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.683942226
Short name T451
Test name
Test status
Simulation time 3153446732 ps
CPU time 1.16 seconds
Started Jul 18 06:37:33 PM PDT 24
Finished Jul 18 06:37:35 PM PDT 24
Peak memory 201608 kb
Host smart-39f8d432-f550-4c54-a9e0-95e8ccf049a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683942226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.683942226
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.324633132
Short name T535
Test name
Test status
Simulation time 5949907099 ps
CPU time 13.98 seconds
Started Jul 18 06:37:17 PM PDT 24
Finished Jul 18 06:37:32 PM PDT 24
Peak memory 201596 kb
Host smart-977fa573-450d-48d7-accb-94c8ed7b6285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324633132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.324633132
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.2267509939
Short name T449
Test name
Test status
Simulation time 52514987827 ps
CPU time 125.43 seconds
Started Jul 18 06:37:32 PM PDT 24
Finished Jul 18 06:39:38 PM PDT 24
Peak memory 201608 kb
Host smart-807136b2-f5e6-4d9d-9fc8-efc90007213f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267509939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all
.2267509939
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.3311206221
Short name T188
Test name
Test status
Simulation time 793761653127 ps
CPU time 609.07 seconds
Started Jul 18 06:37:41 PM PDT 24
Finished Jul 18 06:47:51 PM PDT 24
Peak memory 210436 kb
Host smart-2abe3a53-f457-4a86-bf64-c29b7f6d497e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311206221 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.3311206221
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.3456266070
Short name T631
Test name
Test status
Simulation time 446422261 ps
CPU time 0.75 seconds
Started Jul 18 06:37:48 PM PDT 24
Finished Jul 18 06:37:51 PM PDT 24
Peak memory 201528 kb
Host smart-0d6e5848-5c91-4631-9a5b-80470ee95d7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456266070 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.3456266070
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.3351866151
Short name T211
Test name
Test status
Simulation time 167512581443 ps
CPU time 63.15 seconds
Started Jul 18 06:37:31 PM PDT 24
Finished Jul 18 06:38:35 PM PDT 24
Peak memory 201752 kb
Host smart-25f7ee2c-b0d3-4fd9-a263-c5cb85f8056a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351866151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.3351866151
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.1461703750
Short name T480
Test name
Test status
Simulation time 163113469810 ps
CPU time 190.91 seconds
Started Jul 18 06:37:33 PM PDT 24
Finished Jul 18 06:40:45 PM PDT 24
Peak memory 201728 kb
Host smart-61340813-3411-42b3-a103-dd117fc2ffdd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461703750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interru
pt_fixed.1461703750
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.2460535884
Short name T172
Test name
Test status
Simulation time 168542619923 ps
CPU time 371.83 seconds
Started Jul 18 06:37:35 PM PDT 24
Finished Jul 18 06:43:48 PM PDT 24
Peak memory 201820 kb
Host smart-b6d01e92-fd9f-4468-8e1d-546782564c70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460535884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.2460535884
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.3596204337
Short name T140
Test name
Test status
Simulation time 325950719422 ps
CPU time 108.21 seconds
Started Jul 18 06:37:33 PM PDT 24
Finished Jul 18 06:39:23 PM PDT 24
Peak memory 201720 kb
Host smart-c216188d-bc2d-427a-b439-b1a3e4095313
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596204337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fix
ed.3596204337
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.2909840887
Short name T180
Test name
Test status
Simulation time 538441158235 ps
CPU time 128.39 seconds
Started Jul 18 06:37:32 PM PDT 24
Finished Jul 18 06:39:41 PM PDT 24
Peak memory 201820 kb
Host smart-3c7e99ca-34a0-4974-a252-ca6dafb764c9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909840887 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters
_wakeup.2909840887
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.658849004
Short name T45
Test name
Test status
Simulation time 419746574546 ps
CPU time 481.49 seconds
Started Jul 18 06:37:32 PM PDT 24
Finished Jul 18 06:45:35 PM PDT 24
Peak memory 201720 kb
Host smart-0f88df0f-4c6e-4692-a939-c95a66b73e33
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658849004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
adc_ctrl_filters_wakeup_fixed.658849004
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.3734229357
Short name T724
Test name
Test status
Simulation time 121898954662 ps
CPU time 450.99 seconds
Started Jul 18 06:37:33 PM PDT 24
Finished Jul 18 06:45:05 PM PDT 24
Peak memory 202168 kb
Host smart-d92d040e-b5aa-4517-a6d6-d2f162807e4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734229357 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.3734229357
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.3712001933
Short name T374
Test name
Test status
Simulation time 39506036363 ps
CPU time 44.19 seconds
Started Jul 18 06:37:34 PM PDT 24
Finished Jul 18 06:38:20 PM PDT 24
Peak memory 201600 kb
Host smart-953960f5-e697-4551-87b1-f81dc19b1c5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712001933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.3712001933
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.1529917877
Short name T788
Test name
Test status
Simulation time 5018259398 ps
CPU time 3.6 seconds
Started Jul 18 06:37:34 PM PDT 24
Finished Jul 18 06:37:38 PM PDT 24
Peak memory 201612 kb
Host smart-7902229d-4892-469a-93ba-dd97291e79c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529917877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.1529917877
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.1648588633
Short name T655
Test name
Test status
Simulation time 5746204117 ps
CPU time 15.39 seconds
Started Jul 18 06:37:32 PM PDT 24
Finished Jul 18 06:37:48 PM PDT 24
Peak memory 201620 kb
Host smart-ae6f9e5b-b084-45a2-b521-c22d83b7fed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648588633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.1648588633
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.1294520874
Short name T51
Test name
Test status
Simulation time 109766197689 ps
CPU time 397.41 seconds
Started Jul 18 06:37:47 PM PDT 24
Finished Jul 18 06:44:27 PM PDT 24
Peak memory 202120 kb
Host smart-33bb9fee-22c0-4f8c-a827-28192e0ba355
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294520874 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all
.1294520874
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.1131029043
Short name T62
Test name
Test status
Simulation time 42238286858 ps
CPU time 14.59 seconds
Started Jul 18 06:37:47 PM PDT 24
Finished Jul 18 06:38:04 PM PDT 24
Peak memory 201968 kb
Host smart-90ad227f-67d3-45c8-b334-c1ab15e27b57
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131029043 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.1131029043
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.865271473
Short name T75
Test name
Test status
Simulation time 340835252 ps
CPU time 1.39 seconds
Started Jul 18 06:38:00 PM PDT 24
Finished Jul 18 06:38:02 PM PDT 24
Peak memory 201568 kb
Host smart-cd6a7465-f13a-4336-ba16-38b6c7fe0f80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865271473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.865271473
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.1850869344
Short name T262
Test name
Test status
Simulation time 170314123061 ps
CPU time 192.89 seconds
Started Jul 18 06:37:47 PM PDT 24
Finished Jul 18 06:41:02 PM PDT 24
Peak memory 201816 kb
Host smart-98d2cddc-1d92-4c1d-acfe-de70d7ff8017
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850869344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gat
ing.1850869344
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.1862343463
Short name T630
Test name
Test status
Simulation time 331770987411 ps
CPU time 126.13 seconds
Started Jul 18 06:37:47 PM PDT 24
Finished Jul 18 06:39:56 PM PDT 24
Peak memory 201724 kb
Host smart-72383332-fe9b-4301-bfe2-46061d7d772b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862343463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interru
pt_fixed.1862343463
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.1608437013
Short name T118
Test name
Test status
Simulation time 164222118299 ps
CPU time 185.84 seconds
Started Jul 18 06:37:47 PM PDT 24
Finished Jul 18 06:40:54 PM PDT 24
Peak memory 201740 kb
Host smart-e2314864-8e45-48d9-af4c-494cb9eed5a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608437013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.1608437013
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.1749815901
Short name T560
Test name
Test status
Simulation time 499682058104 ps
CPU time 305.26 seconds
Started Jul 18 06:37:47 PM PDT 24
Finished Jul 18 06:42:54 PM PDT 24
Peak memory 201796 kb
Host smart-187026a9-611e-426c-8876-bed12ffc80d8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749815901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fix
ed.1749815901
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.698536375
Short name T250
Test name
Test status
Simulation time 182926197135 ps
CPU time 210.92 seconds
Started Jul 18 06:37:46 PM PDT 24
Finished Jul 18 06:41:18 PM PDT 24
Peak memory 201760 kb
Host smart-564b3e5e-e417-4098-b129-01404f477675
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698536375 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_
wakeup.698536375
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.951980657
Short name T365
Test name
Test status
Simulation time 403623076415 ps
CPU time 876.15 seconds
Started Jul 18 06:37:47 PM PDT 24
Finished Jul 18 06:52:25 PM PDT 24
Peak memory 201716 kb
Host smart-d28b5873-4d46-4c37-b2dd-245cc6e5380d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951980657 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
adc_ctrl_filters_wakeup_fixed.951980657
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.1408683654
Short name T715
Test name
Test status
Simulation time 98668771969 ps
CPU time 396.18 seconds
Started Jul 18 06:37:47 PM PDT 24
Finished Jul 18 06:44:26 PM PDT 24
Peak memory 202112 kb
Host smart-5eda6e6c-8112-45a7-b5aa-c6c82ab3adf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408683654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.1408683654
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.435283393
Short name T799
Test name
Test status
Simulation time 21214736513 ps
CPU time 12.77 seconds
Started Jul 18 06:37:48 PM PDT 24
Finished Jul 18 06:38:03 PM PDT 24
Peak memory 201580 kb
Host smart-070420a5-9b3b-424d-b9d1-3e02bd9a3d65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435283393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.435283393
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.593335755
Short name T443
Test name
Test status
Simulation time 4598721668 ps
CPU time 11.18 seconds
Started Jul 18 06:37:46 PM PDT 24
Finished Jul 18 06:37:58 PM PDT 24
Peak memory 201604 kb
Host smart-3168c3c0-f219-475e-b5e7-dd0ec891c56d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593335755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.593335755
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.3317780932
Short name T495
Test name
Test status
Simulation time 5867815970 ps
CPU time 7.54 seconds
Started Jul 18 06:37:48 PM PDT 24
Finished Jul 18 06:37:58 PM PDT 24
Peak memory 201620 kb
Host smart-4f26051f-4246-4dfa-969c-9f0ed00dca1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317780932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.3317780932
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.1651692580
Short name T135
Test name
Test status
Simulation time 363789179835 ps
CPU time 752.6 seconds
Started Jul 18 06:38:01 PM PDT 24
Finished Jul 18 06:50:35 PM PDT 24
Peak memory 201748 kb
Host smart-08e0c9a3-0d9d-4e53-acb6-076850a08014
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651692580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all
.1651692580
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.1401716747
Short name T528
Test name
Test status
Simulation time 19232131281 ps
CPU time 40.56 seconds
Started Jul 18 06:37:48 PM PDT 24
Finished Jul 18 06:38:31 PM PDT 24
Peak memory 210124 kb
Host smart-948b7094-4cef-4429-b163-d4b659795168
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401716747 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.1401716747
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.2887391368
Short name T493
Test name
Test status
Simulation time 369365281 ps
CPU time 0.88 seconds
Started Jul 18 06:38:01 PM PDT 24
Finished Jul 18 06:38:03 PM PDT 24
Peak memory 201552 kb
Host smart-2fcc3464-c199-42c3-a995-4c2516d73271
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887391368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.2887391368
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.944855889
Short name T275
Test name
Test status
Simulation time 244383844319 ps
CPU time 108.97 seconds
Started Jul 18 06:38:02 PM PDT 24
Finished Jul 18 06:39:53 PM PDT 24
Peak memory 201792 kb
Host smart-d13d81ea-db55-40f5-85b0-a699d7260afb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944855889 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.944855889
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.3725768905
Short name T607
Test name
Test status
Simulation time 329273656369 ps
CPU time 737.42 seconds
Started Jul 18 06:38:03 PM PDT 24
Finished Jul 18 06:50:21 PM PDT 24
Peak memory 201812 kb
Host smart-090598e6-ce5b-4322-a8fc-5b7e42aa41fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725768905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.3725768905
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.2322020869
Short name T576
Test name
Test status
Simulation time 493578376254 ps
CPU time 77.89 seconds
Started Jul 18 06:38:00 PM PDT 24
Finished Jul 18 06:39:19 PM PDT 24
Peak memory 201696 kb
Host smart-788fd355-fb40-4460-95b5-6a3878c2d3fd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322020869 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interru
pt_fixed.2322020869
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.71664307
Short name T254
Test name
Test status
Simulation time 165278790261 ps
CPU time 370.3 seconds
Started Jul 18 06:37:59 PM PDT 24
Finished Jul 18 06:44:11 PM PDT 24
Peak memory 201768 kb
Host smart-547faef4-7d2d-4a78-afc0-26850012f3c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71664307 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.71664307
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.795909864
Short name T388
Test name
Test status
Simulation time 324169453435 ps
CPU time 105.55 seconds
Started Jul 18 06:38:02 PM PDT 24
Finished Jul 18 06:39:49 PM PDT 24
Peak memory 201796 kb
Host smart-af7b03cb-28d7-4477-b974-fb4b276f4429
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=795909864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fixe
d.795909864
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.3775087607
Short name T24
Test name
Test status
Simulation time 194962102575 ps
CPU time 451.07 seconds
Started Jul 18 06:37:58 PM PDT 24
Finished Jul 18 06:45:30 PM PDT 24
Peak memory 201812 kb
Host smart-c4321335-8f7d-4d5d-be6e-3ce0087dcb2c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775087607 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters
_wakeup.3775087607
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.28209101
Short name T636
Test name
Test status
Simulation time 415512312096 ps
CPU time 501.3 seconds
Started Jul 18 06:38:02 PM PDT 24
Finished Jul 18 06:46:24 PM PDT 24
Peak memory 201728 kb
Host smart-a3eb4cea-ee23-46af-98a6-f0f78aa2a5dc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28209101 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.a
dc_ctrl_filters_wakeup_fixed.28209101
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.1039006424
Short name T200
Test name
Test status
Simulation time 106805495781 ps
CPU time 584.15 seconds
Started Jul 18 06:37:59 PM PDT 24
Finished Jul 18 06:47:44 PM PDT 24
Peak memory 202120 kb
Host smart-cc73df1b-9aea-4eee-b9fd-da0d6727b3e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039006424 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.1039006424
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.4085249599
Short name T530
Test name
Test status
Simulation time 27047525060 ps
CPU time 32.99 seconds
Started Jul 18 06:38:00 PM PDT 24
Finished Jul 18 06:38:35 PM PDT 24
Peak memory 201608 kb
Host smart-a43a53b5-46ef-472c-90bc-524cf597e2fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085249599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.4085249599
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.1843152394
Short name T517
Test name
Test status
Simulation time 3271955685 ps
CPU time 8.49 seconds
Started Jul 18 06:37:59 PM PDT 24
Finished Jul 18 06:38:08 PM PDT 24
Peak memory 201608 kb
Host smart-b8aa0438-198a-4a0e-990f-26d4af93f894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843152394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.1843152394
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.3336884168
Short name T769
Test name
Test status
Simulation time 5370699521 ps
CPU time 3.28 seconds
Started Jul 18 06:37:59 PM PDT 24
Finished Jul 18 06:38:04 PM PDT 24
Peak memory 201600 kb
Host smart-3002cd9b-4696-441c-8a31-22d12ece8904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336884168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.3336884168
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.3027337498
Short name T290
Test name
Test status
Simulation time 494777140951 ps
CPU time 221.25 seconds
Started Jul 18 06:38:00 PM PDT 24
Finished Jul 18 06:41:43 PM PDT 24
Peak memory 201808 kb
Host smart-60d4b3f8-9b69-419f-8372-1d2abaddb910
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027337498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all
.3027337498
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.1849867986
Short name T593
Test name
Test status
Simulation time 46756381157 ps
CPU time 26.18 seconds
Started Jul 18 06:38:01 PM PDT 24
Finished Jul 18 06:38:28 PM PDT 24
Peak memory 210064 kb
Host smart-eacda0b1-c9a9-4dc9-8580-12fb514a1981
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849867986 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.1849867986
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.3006727297
Short name T363
Test name
Test status
Simulation time 322271074 ps
CPU time 0.95 seconds
Started Jul 18 06:38:25 PM PDT 24
Finished Jul 18 06:38:29 PM PDT 24
Peak memory 201532 kb
Host smart-1b9c09df-4280-4565-b9f0-07858ebed78d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006727297 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.3006727297
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.3908263206
Short name T273
Test name
Test status
Simulation time 158786096496 ps
CPU time 96.78 seconds
Started Jul 18 06:38:11 PM PDT 24
Finished Jul 18 06:39:49 PM PDT 24
Peak memory 201728 kb
Host smart-98e7c439-8e37-485a-93d2-36585a5a6d8f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908263206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gat
ing.3908263206
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.377039338
Short name T261
Test name
Test status
Simulation time 194950538626 ps
CPU time 425.21 seconds
Started Jul 18 06:38:13 PM PDT 24
Finished Jul 18 06:45:19 PM PDT 24
Peak memory 201740 kb
Host smart-aee4d3f0-89b8-42cc-9114-9ad9c61abc9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377039338 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.377039338
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.3564914515
Short name T341
Test name
Test status
Simulation time 330909492531 ps
CPU time 453.31 seconds
Started Jul 18 06:38:14 PM PDT 24
Finished Jul 18 06:45:48 PM PDT 24
Peak memory 201808 kb
Host smart-32bb14e6-8d16-4a1a-8613-170e213e7abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564914515 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.3564914515
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.2159095614
Short name T409
Test name
Test status
Simulation time 162412848419 ps
CPU time 91.38 seconds
Started Jul 18 06:38:14 PM PDT 24
Finished Jul 18 06:39:46 PM PDT 24
Peak memory 201720 kb
Host smart-6fb28310-b9ce-4ecb-9bba-fea672dd2a9e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159095614 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interru
pt_fixed.2159095614
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.2567352495
Short name T541
Test name
Test status
Simulation time 332570459520 ps
CPU time 214.91 seconds
Started Jul 18 06:38:13 PM PDT 24
Finished Jul 18 06:41:49 PM PDT 24
Peak memory 201708 kb
Host smart-97a47068-641e-49ef-88f1-d4c605ceff8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567352495 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.2567352495
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.1106328010
Short name T465
Test name
Test status
Simulation time 162170049448 ps
CPU time 332.16 seconds
Started Jul 18 06:38:13 PM PDT 24
Finished Jul 18 06:43:46 PM PDT 24
Peak memory 201716 kb
Host smart-fa6bb9fb-495e-4174-942b-1aedace4a4a6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106328010 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fix
ed.1106328010
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.1550079730
Short name T577
Test name
Test status
Simulation time 453849847300 ps
CPU time 278.85 seconds
Started Jul 18 06:38:11 PM PDT 24
Finished Jul 18 06:42:51 PM PDT 24
Peak memory 201812 kb
Host smart-fc5dca7f-41a4-4375-a977-eeedd673f164
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550079730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters
_wakeup.1550079730
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.2764260687
Short name T456
Test name
Test status
Simulation time 197362142016 ps
CPU time 459.55 seconds
Started Jul 18 06:38:14 PM PDT 24
Finished Jul 18 06:45:55 PM PDT 24
Peak memory 201720 kb
Host smart-55156668-16fb-4b8c-a4e9-81826f862a9a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764260687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.adc_ctrl_filters_wakeup_fixed.2764260687
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.1560594880
Short name T350
Test name
Test status
Simulation time 132861426749 ps
CPU time 483.15 seconds
Started Jul 18 06:38:12 PM PDT 24
Finished Jul 18 06:46:17 PM PDT 24
Peak memory 202104 kb
Host smart-2bb15bf8-62b8-46ed-817e-16aa4849af5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560594880 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.1560594880
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.2541357377
Short name T522
Test name
Test status
Simulation time 24529113677 ps
CPU time 29.27 seconds
Started Jul 18 06:38:13 PM PDT 24
Finished Jul 18 06:38:43 PM PDT 24
Peak memory 201608 kb
Host smart-2498f6d3-3256-4d09-bc63-c58e06258540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541357377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.2541357377
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.246349322
Short name T694
Test name
Test status
Simulation time 3582910821 ps
CPU time 4.6 seconds
Started Jul 18 06:38:14 PM PDT 24
Finished Jul 18 06:38:20 PM PDT 24
Peak memory 201796 kb
Host smart-a1bd2426-cdbd-481f-a25f-c96fa5ce774b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246349322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.246349322
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.4082185428
Short name T434
Test name
Test status
Simulation time 5615962909 ps
CPU time 14.01 seconds
Started Jul 18 06:38:00 PM PDT 24
Finished Jul 18 06:38:15 PM PDT 24
Peak memory 201596 kb
Host smart-900a887f-a553-43f8-8798-da02e753cf11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082185428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.4082185428
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.75324776
Short name T226
Test name
Test status
Simulation time 327872648877 ps
CPU time 705.5 seconds
Started Jul 18 06:38:12 PM PDT 24
Finished Jul 18 06:49:59 PM PDT 24
Peak memory 201808 kb
Host smart-b63a04cd-30ad-4db3-bbce-0d0e1a5a08d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75324776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all.75324776
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.2979926080
Short name T19
Test name
Test status
Simulation time 50626734842 ps
CPU time 32.15 seconds
Started Jul 18 06:38:12 PM PDT 24
Finished Jul 18 06:38:45 PM PDT 24
Peak memory 201876 kb
Host smart-b9a957e4-af21-4fdd-a2a2-1610ea9a566d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979926080 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.2979926080
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.3343840803
Short name T433
Test name
Test status
Simulation time 332773114 ps
CPU time 1.32 seconds
Started Jul 18 06:38:25 PM PDT 24
Finished Jul 18 06:38:29 PM PDT 24
Peak memory 201560 kb
Host smart-e06ac18d-3ff0-4de9-aa2d-2a2896273767
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343840803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.3343840803
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.1878838884
Short name T770
Test name
Test status
Simulation time 162056162306 ps
CPU time 195.41 seconds
Started Jul 18 06:38:27 PM PDT 24
Finished Jul 18 06:41:45 PM PDT 24
Peak memory 201800 kb
Host smart-4d613d59-918e-41da-8c02-a0ddc8afc87d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878838884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gat
ing.1878838884
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.3761128328
Short name T6
Test name
Test status
Simulation time 162992644786 ps
CPU time 380.07 seconds
Started Jul 18 06:38:27 PM PDT 24
Finished Jul 18 06:44:49 PM PDT 24
Peak memory 201812 kb
Host smart-a3aae2e6-7a38-44a5-a1ad-89b6268b751d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761128328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.3761128328
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.2151178306
Short name T335
Test name
Test status
Simulation time 481749212326 ps
CPU time 276.5 seconds
Started Jul 18 06:38:27 PM PDT 24
Finished Jul 18 06:43:06 PM PDT 24
Peak memory 201752 kb
Host smart-698ba1c1-960c-4def-b9e8-252322d5cae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151178306 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.2151178306
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.2142661448
Short name T592
Test name
Test status
Simulation time 329411751863 ps
CPU time 388.9 seconds
Started Jul 18 06:38:26 PM PDT 24
Finished Jul 18 06:44:58 PM PDT 24
Peak memory 201696 kb
Host smart-1a2d7f57-9d4c-46f9-bfe6-f0ddd2a328cf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142661448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interru
pt_fixed.2142661448
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.1010533579
Short name T121
Test name
Test status
Simulation time 165487815317 ps
CPU time 377.33 seconds
Started Jul 18 06:38:25 PM PDT 24
Finished Jul 18 06:44:44 PM PDT 24
Peak memory 201980 kb
Host smart-2c1e0e3f-3c12-4ed0-8b71-8692eac1b3ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010533579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.1010533579
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.3403939859
Short name T604
Test name
Test status
Simulation time 166741691584 ps
CPU time 393.23 seconds
Started Jul 18 06:38:24 PM PDT 24
Finished Jul 18 06:44:59 PM PDT 24
Peak memory 201796 kb
Host smart-0f686db8-de21-43fe-9549-b8912f86fe2e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403939859 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fix
ed.3403939859
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.202317209
Short name T256
Test name
Test status
Simulation time 539573972261 ps
CPU time 1324.46 seconds
Started Jul 18 06:38:25 PM PDT 24
Finished Jul 18 07:00:32 PM PDT 24
Peak memory 201816 kb
Host smart-44a51edb-252e-4cb9-8615-338470f767c9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202317209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_
wakeup.202317209
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.3191041907
Short name T793
Test name
Test status
Simulation time 197432596783 ps
CPU time 414.4 seconds
Started Jul 18 06:38:27 PM PDT 24
Finished Jul 18 06:45:24 PM PDT 24
Peak memory 201784 kb
Host smart-c6db2329-d171-4c7e-a323-dc79c103c79c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191041907 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.adc_ctrl_filters_wakeup_fixed.3191041907
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.3735449088
Short name T357
Test name
Test status
Simulation time 125635682245 ps
CPU time 442.32 seconds
Started Jul 18 06:38:25 PM PDT 24
Finished Jul 18 06:45:50 PM PDT 24
Peak memory 202180 kb
Host smart-1b579304-915c-4671-ba54-bac7e5c2546d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735449088 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.3735449088
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.3283520345
Short name T590
Test name
Test status
Simulation time 38563766264 ps
CPU time 15.78 seconds
Started Jul 18 06:38:27 PM PDT 24
Finished Jul 18 06:38:45 PM PDT 24
Peak memory 201800 kb
Host smart-59c4147d-4445-46b1-a868-6ba28f319d46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283520345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.3283520345
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.2414456695
Short name T115
Test name
Test status
Simulation time 3448407825 ps
CPU time 8.64 seconds
Started Jul 18 06:38:25 PM PDT 24
Finished Jul 18 06:38:37 PM PDT 24
Peak memory 201596 kb
Host smart-2435998b-0da4-4401-9114-650ffce0c5f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414456695 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.2414456695
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.3117791994
Short name T651
Test name
Test status
Simulation time 6040827818 ps
CPU time 13.56 seconds
Started Jul 18 06:38:26 PM PDT 24
Finished Jul 18 06:38:42 PM PDT 24
Peak memory 201592 kb
Host smart-6af90867-167e-49fb-b646-567fbad9f6fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117791994 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.3117791994
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.3451622763
Short name T663
Test name
Test status
Simulation time 211001281861 ps
CPU time 478.05 seconds
Started Jul 18 06:38:25 PM PDT 24
Finished Jul 18 06:46:25 PM PDT 24
Peak memory 201636 kb
Host smart-031479e7-da98-48fc-a76c-bbb24a74ce51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451622763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all
.3451622763
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.1098766700
Short name T611
Test name
Test status
Simulation time 1436781494518 ps
CPU time 667.67 seconds
Started Jul 18 06:38:26 PM PDT 24
Finished Jul 18 06:49:36 PM PDT 24
Peak memory 210404 kb
Host smart-98ed7078-fe31-4ae2-a4f4-bcae29680c5e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098766700 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.1098766700
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.1935795425
Short name T170
Test name
Test status
Simulation time 405441327 ps
CPU time 1.45 seconds
Started Jul 18 06:38:39 PM PDT 24
Finished Jul 18 06:38:42 PM PDT 24
Peak memory 201540 kb
Host smart-4360a9d4-b1d9-4a48-b8be-c7cc9ff0db6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935795425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.1935795425
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.226501426
Short name T319
Test name
Test status
Simulation time 515152693679 ps
CPU time 1071.61 seconds
Started Jul 18 06:38:39 PM PDT 24
Finished Jul 18 06:56:31 PM PDT 24
Peak memory 201796 kb
Host smart-d31eaace-648c-4c9b-964b-cecf705e13d9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226501426 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gati
ng.226501426
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.4216884042
Short name T162
Test name
Test status
Simulation time 339528464238 ps
CPU time 802.36 seconds
Started Jul 18 06:38:40 PM PDT 24
Finished Jul 18 06:52:04 PM PDT 24
Peak memory 201752 kb
Host smart-41a4a71c-d19b-42e5-8017-95f58dbac734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216884042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.4216884042
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.3851761527
Short name T774
Test name
Test status
Simulation time 325043384091 ps
CPU time 753.15 seconds
Started Jul 18 06:38:39 PM PDT 24
Finished Jul 18 06:51:14 PM PDT 24
Peak memory 201764 kb
Host smart-7e4eb835-f841-42fb-856e-66c911c4cf09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851761527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.3851761527
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.684899805
Short name T649
Test name
Test status
Simulation time 335957788799 ps
CPU time 193.34 seconds
Started Jul 18 06:38:40 PM PDT 24
Finished Jul 18 06:41:55 PM PDT 24
Peak memory 201728 kb
Host smart-fbcc1e4f-d33d-4a6a-aba0-83f13eea7076
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=684899805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrup
t_fixed.684899805
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.1214987504
Short name T634
Test name
Test status
Simulation time 161097863503 ps
CPU time 363.93 seconds
Started Jul 18 06:38:24 PM PDT 24
Finished Jul 18 06:44:29 PM PDT 24
Peak memory 201876 kb
Host smart-3739f598-db2b-4643-aef4-c1bbde07a4d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214987504 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.1214987504
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.761131250
Short name T711
Test name
Test status
Simulation time 327064357200 ps
CPU time 633.34 seconds
Started Jul 18 06:38:26 PM PDT 24
Finished Jul 18 06:49:02 PM PDT 24
Peak memory 201740 kb
Host smart-7a037140-b33a-43da-9b15-d4b97527ea1f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=761131250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fixe
d.761131250
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.3230840728
Short name T332
Test name
Test status
Simulation time 380956278906 ps
CPU time 850.81 seconds
Started Jul 18 06:38:40 PM PDT 24
Finished Jul 18 06:52:52 PM PDT 24
Peak memory 201656 kb
Host smart-9ef0458e-89e1-432f-b5f7-5a6f30afb224
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230840728 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters
_wakeup.3230840728
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.2359861063
Short name T44
Test name
Test status
Simulation time 612109148725 ps
CPU time 334.85 seconds
Started Jul 18 06:38:40 PM PDT 24
Finished Jul 18 06:44:16 PM PDT 24
Peak memory 201732 kb
Host smart-d332bb1b-fd14-45fa-a321-6bf5158ea937
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359861063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.adc_ctrl_filters_wakeup_fixed.2359861063
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.2344214540
Short name T567
Test name
Test status
Simulation time 117331195905 ps
CPU time 530.19 seconds
Started Jul 18 06:38:39 PM PDT 24
Finished Jul 18 06:47:30 PM PDT 24
Peak memory 202052 kb
Host smart-604aea6f-0d1a-4ce6-874b-7fa8665854ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344214540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.2344214540
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.4058000058
Short name T612
Test name
Test status
Simulation time 35200338121 ps
CPU time 43.17 seconds
Started Jul 18 06:38:40 PM PDT 24
Finished Jul 18 06:39:25 PM PDT 24
Peak memory 201580 kb
Host smart-b0e2d9ca-eb95-4b9c-bb54-0d337a5b255b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058000058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.4058000058
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.842178487
Short name T481
Test name
Test status
Simulation time 3819633010 ps
CPU time 9.95 seconds
Started Jul 18 06:38:40 PM PDT 24
Finished Jul 18 06:38:51 PM PDT 24
Peak memory 201608 kb
Host smart-49d76c5c-95ad-4e8e-8256-169bd8c85d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842178487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.842178487
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.3425686422
Short name T549
Test name
Test status
Simulation time 5872100752 ps
CPU time 4.9 seconds
Started Jul 18 06:38:24 PM PDT 24
Finished Jul 18 06:38:31 PM PDT 24
Peak memory 201616 kb
Host smart-013bd898-a79f-47d4-a1c9-a78d3ca0a503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425686422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.3425686422
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.1379063288
Short name T30
Test name
Test status
Simulation time 197206645848 ps
CPU time 413.59 seconds
Started Jul 18 06:38:41 PM PDT 24
Finished Jul 18 06:45:36 PM PDT 24
Peak memory 201728 kb
Host smart-35b22080-b216-4aba-9153-0437dcc74290
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379063288 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all
.1379063288
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.3754318214
Short name T321
Test name
Test status
Simulation time 118885745428 ps
CPU time 187.76 seconds
Started Jul 18 06:38:41 PM PDT 24
Finished Jul 18 06:41:50 PM PDT 24
Peak memory 210508 kb
Host smart-d7ae5cac-7b51-49fb-bf23-7dc450ee9cf9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754318214 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.3754318214
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.2004821587
Short name T425
Test name
Test status
Simulation time 456922447 ps
CPU time 1.55 seconds
Started Jul 18 06:32:04 PM PDT 24
Finished Jul 18 06:32:08 PM PDT 24
Peak memory 201544 kb
Host smart-c1512ce9-0ba0-4dc5-b37f-dce2142bf6a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004821587 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.2004821587
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.1622881900
Short name T88
Test name
Test status
Simulation time 344231590333 ps
CPU time 389.01 seconds
Started Jul 18 06:32:05 PM PDT 24
Finished Jul 18 06:38:38 PM PDT 24
Peak memory 201736 kb
Host smart-a78706d5-1030-4d81-9adb-22c0d8bc0371
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622881900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gati
ng.1622881900
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.1988284724
Short name T761
Test name
Test status
Simulation time 323039347319 ps
CPU time 410.96 seconds
Started Jul 18 06:32:06 PM PDT 24
Finished Jul 18 06:39:02 PM PDT 24
Peak memory 201396 kb
Host smart-0d224131-8f2a-4b87-92a3-32d15f4f34f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988284724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.1988284724
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.102512658
Short name T29
Test name
Test status
Simulation time 170202661987 ps
CPU time 98.74 seconds
Started Jul 18 06:32:03 PM PDT 24
Finished Jul 18 06:33:43 PM PDT 24
Peak memory 201704 kb
Host smart-f56c349c-8a04-43ea-920c-f0e655864856
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=102512658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt
_fixed.102512658
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.3913694391
Short name T131
Test name
Test status
Simulation time 165809054893 ps
CPU time 366.48 seconds
Started Jul 18 06:32:05 PM PDT 24
Finished Jul 18 06:38:16 PM PDT 24
Peak memory 201688 kb
Host smart-87cd0a6f-66e9-4a99-bf55-ca51d94c6e85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913694391 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.3913694391
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.2068376065
Short name T653
Test name
Test status
Simulation time 328634447579 ps
CPU time 758.04 seconds
Started Jul 18 06:32:03 PM PDT 24
Finished Jul 18 06:44:42 PM PDT 24
Peak memory 201712 kb
Host smart-c88666ff-83c0-43d7-90ac-349e910956e4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068376065 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixe
d.2068376065
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.4005514885
Short name T677
Test name
Test status
Simulation time 612012783336 ps
CPU time 1505.33 seconds
Started Jul 18 06:32:04 PM PDT 24
Finished Jul 18 06:57:12 PM PDT 24
Peak memory 201756 kb
Host smart-e3c8b6e6-912e-4cb3-ad01-f5f09a5fbd56
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005514885 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
adc_ctrl_filters_wakeup_fixed.4005514885
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.2251589453
Short name T628
Test name
Test status
Simulation time 22489089728 ps
CPU time 27.59 seconds
Started Jul 18 06:32:03 PM PDT 24
Finished Jul 18 06:32:32 PM PDT 24
Peak memory 201364 kb
Host smart-78880e93-8e3d-412b-9a12-a5d94b318624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251589453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.2251589453
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.3018341149
Short name T688
Test name
Test status
Simulation time 4123922407 ps
CPU time 5.32 seconds
Started Jul 18 06:32:01 PM PDT 24
Finished Jul 18 06:32:07 PM PDT 24
Peak memory 201576 kb
Host smart-a4cefae9-5214-42db-8b91-4b9ab7bd7c06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018341149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.3018341149
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.3529352611
Short name T638
Test name
Test status
Simulation time 5648878833 ps
CPU time 12.34 seconds
Started Jul 18 06:32:03 PM PDT 24
Finished Jul 18 06:32:16 PM PDT 24
Peak memory 201592 kb
Host smart-f4a96654-031d-451d-b494-1b8fbdd55970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529352611 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.3529352611
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.3314299982
Short name T48
Test name
Test status
Simulation time 307332508614 ps
CPU time 562.29 seconds
Started Jul 18 06:32:01 PM PDT 24
Finished Jul 18 06:41:24 PM PDT 24
Peak memory 202100 kb
Host smart-f18d827e-89bf-45ca-b08d-dcff0cf64c7d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314299982 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.
3314299982
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.3773184041
Short name T683
Test name
Test status
Simulation time 46879938619 ps
CPU time 49.7 seconds
Started Jul 18 06:32:04 PM PDT 24
Finished Jul 18 06:32:56 PM PDT 24
Peak memory 210064 kb
Host smart-9ef71056-a9a6-4d68-b129-ec7bdb807745
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773184041 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.3773184041
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.2623996225
Short name T367
Test name
Test status
Simulation time 303186868 ps
CPU time 1.42 seconds
Started Jul 18 06:32:04 PM PDT 24
Finished Jul 18 06:32:08 PM PDT 24
Peak memory 201564 kb
Host smart-d2e6d351-d8d3-4824-a972-cc5daeefb7ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623996225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.2623996225
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.3515380322
Short name T285
Test name
Test status
Simulation time 170320318409 ps
CPU time 328.85 seconds
Started Jul 18 06:32:06 PM PDT 24
Finished Jul 18 06:37:40 PM PDT 24
Peak memory 201708 kb
Host smart-79bb15b1-8052-426c-b4c7-c6a2f2f7c8cb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515380322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gati
ng.3515380322
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.1834389492
Short name T295
Test name
Test status
Simulation time 340146756345 ps
CPU time 826.99 seconds
Started Jul 18 06:32:01 PM PDT 24
Finished Jul 18 06:45:49 PM PDT 24
Peak memory 201780 kb
Host smart-ff6b4898-c24e-4421-bbed-a636f4461efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834389492 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.1834389492
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.1324424925
Short name T316
Test name
Test status
Simulation time 166477965930 ps
CPU time 107.13 seconds
Started Jul 18 06:32:06 PM PDT 24
Finished Jul 18 06:33:59 PM PDT 24
Peak memory 201748 kb
Host smart-e0d5f89e-c14a-4f08-a840-91bdca3f7107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324424925 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.1324424925
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.247487396
Short name T543
Test name
Test status
Simulation time 160896865186 ps
CPU time 88.75 seconds
Started Jul 18 06:32:05 PM PDT 24
Finished Jul 18 06:33:38 PM PDT 24
Peak memory 201720 kb
Host smart-aa1c981e-c7f4-4436-82df-867ce2c818cd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=247487396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt
_fixed.247487396
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.2765052782
Short name T149
Test name
Test status
Simulation time 323061153938 ps
CPU time 746.51 seconds
Started Jul 18 06:32:04 PM PDT 24
Finished Jul 18 06:44:33 PM PDT 24
Peak memory 201744 kb
Host smart-4b61c81b-1a22-4d9b-a47c-ddd891d6fd43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765052782 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.2765052782
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.3323122419
Short name T138
Test name
Test status
Simulation time 487919036811 ps
CPU time 104.1 seconds
Started Jul 18 06:32:01 PM PDT 24
Finished Jul 18 06:33:46 PM PDT 24
Peak memory 201728 kb
Host smart-e76acf0b-35a8-4ae4-a688-f12afbcd0250
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323122419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixe
d.3323122419
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.3249626742
Short name T629
Test name
Test status
Simulation time 362978452871 ps
CPU time 852.68 seconds
Started Jul 18 06:32:06 PM PDT 24
Finished Jul 18 06:46:24 PM PDT 24
Peak memory 201740 kb
Host smart-3810b09f-86df-4868-9d7b-b019c1bbb5dd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249626742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_
wakeup.3249626742
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.3664962241
Short name T91
Test name
Test status
Simulation time 405161432263 ps
CPU time 67.36 seconds
Started Jul 18 06:32:05 PM PDT 24
Finished Jul 18 06:33:17 PM PDT 24
Peak memory 201736 kb
Host smart-2e1e9f4b-60f0-4573-9963-2c0f3aaad8b5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664962241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
adc_ctrl_filters_wakeup_fixed.3664962241
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.2241951015
Short name T201
Test name
Test status
Simulation time 131668949455 ps
CPU time 682.46 seconds
Started Jul 18 06:32:03 PM PDT 24
Finished Jul 18 06:43:29 PM PDT 24
Peak memory 202120 kb
Host smart-f2d37339-da58-4506-b4e3-e7768cae7d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241951015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.2241951015
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.459084549
Short name T654
Test name
Test status
Simulation time 32708727191 ps
CPU time 35.37 seconds
Started Jul 18 06:32:03 PM PDT 24
Finished Jul 18 06:32:41 PM PDT 24
Peak memory 201596 kb
Host smart-3de3521a-a7cf-48de-895b-ff333578736c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459084549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.459084549
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.3811523005
Short name T507
Test name
Test status
Simulation time 3724316954 ps
CPU time 1.64 seconds
Started Jul 18 06:32:03 PM PDT 24
Finished Jul 18 06:32:08 PM PDT 24
Peak memory 201612 kb
Host smart-8c8ad3d5-0f37-4abb-b540-4070a27be44a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811523005 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.3811523005
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.1547225144
Short name T720
Test name
Test status
Simulation time 6022488871 ps
CPU time 14.44 seconds
Started Jul 18 06:32:03 PM PDT 24
Finished Jul 18 06:32:19 PM PDT 24
Peak memory 201680 kb
Host smart-d7489a35-dbff-4dfc-8f30-8d06793523d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547225144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.1547225144
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.4119440026
Short name T292
Test name
Test status
Simulation time 506473243733 ps
CPU time 308.15 seconds
Started Jul 18 06:32:04 PM PDT 24
Finished Jul 18 06:37:15 PM PDT 24
Peak memory 201788 kb
Host smart-c6072151-0715-4f72-915b-5a37bbf1c54e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119440026 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.
4119440026
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.3013679188
Short name T503
Test name
Test status
Simulation time 365598137 ps
CPU time 0.9 seconds
Started Jul 18 06:32:10 PM PDT 24
Finished Jul 18 06:32:16 PM PDT 24
Peak memory 201612 kb
Host smart-fc4d4bb7-6e7e-49f0-9dab-056080841020
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013679188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.3013679188
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.3346458062
Short name T781
Test name
Test status
Simulation time 352382014274 ps
CPU time 462.89 seconds
Started Jul 18 06:32:06 PM PDT 24
Finished Jul 18 06:39:54 PM PDT 24
Peak memory 201780 kb
Host smart-afeba91f-5c90-4f40-8585-5f12e4c47ff4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346458062 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gati
ng.3346458062
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.675579655
Short name T534
Test name
Test status
Simulation time 383211764834 ps
CPU time 884.67 seconds
Started Jul 18 06:32:03 PM PDT 24
Finished Jul 18 06:46:50 PM PDT 24
Peak memory 201744 kb
Host smart-1f912e1d-e18b-4bd3-8a13-4eafaa36fe51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675579655 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.675579655
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.1960700515
Short name T358
Test name
Test status
Simulation time 161829375174 ps
CPU time 97.92 seconds
Started Jul 18 06:32:08 PM PDT 24
Finished Jul 18 06:33:51 PM PDT 24
Peak memory 201788 kb
Host smart-7c4ec63d-449d-496e-9f96-6da269ffbbc9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960700515 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrup
t_fixed.1960700515
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.3701596689
Short name T591
Test name
Test status
Simulation time 163377013140 ps
CPU time 252.65 seconds
Started Jul 18 06:32:03 PM PDT 24
Finished Jul 18 06:36:17 PM PDT 24
Peak memory 201828 kb
Host smart-cb86cdaf-f99b-41dd-802a-0d912a232ec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701596689 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.3701596689
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.2799996247
Short name T370
Test name
Test status
Simulation time 500498345378 ps
CPU time 274.8 seconds
Started Jul 18 06:32:04 PM PDT 24
Finished Jul 18 06:36:43 PM PDT 24
Peak memory 201784 kb
Host smart-c771be57-69ea-409f-8b77-8a152d06c1cf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799996247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixe
d.2799996247
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.2294914956
Short name T182
Test name
Test status
Simulation time 598963802625 ps
CPU time 311.78 seconds
Started Jul 18 06:32:02 PM PDT 24
Finished Jul 18 06:37:15 PM PDT 24
Peak memory 201828 kb
Host smart-5ee31bb6-5084-4836-aa35-c84a467adb21
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294914956 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_
wakeup.2294914956
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.3668153625
Short name T784
Test name
Test status
Simulation time 594645114366 ps
CPU time 628.85 seconds
Started Jul 18 06:32:03 PM PDT 24
Finished Jul 18 06:42:33 PM PDT 24
Peak memory 201784 kb
Host smart-af927e2f-ba9d-4a47-9094-12906e14a146
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668153625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
adc_ctrl_filters_wakeup_fixed.3668153625
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.3007710641
Short name T537
Test name
Test status
Simulation time 136781076688 ps
CPU time 525.36 seconds
Started Jul 18 06:32:05 PM PDT 24
Finished Jul 18 06:40:54 PM PDT 24
Peak memory 202136 kb
Host smart-0533f316-4377-4d69-b660-52c1d75a8ed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007710641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.3007710641
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.2535651027
Short name T126
Test name
Test status
Simulation time 27852235367 ps
CPU time 17.86 seconds
Started Jul 18 06:32:01 PM PDT 24
Finished Jul 18 06:32:20 PM PDT 24
Peak memory 201608 kb
Host smart-90cece60-b41f-4aa1-995f-967a109401cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535651027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.2535651027
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.1629765364
Short name T582
Test name
Test status
Simulation time 3354931479 ps
CPU time 8.08 seconds
Started Jul 18 06:32:05 PM PDT 24
Finished Jul 18 06:32:17 PM PDT 24
Peak memory 201548 kb
Host smart-7dd2c4ee-6c0d-453e-82d3-210606433dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629765364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.1629765364
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.1263597377
Short name T392
Test name
Test status
Simulation time 5669844717 ps
CPU time 4.03 seconds
Started Jul 18 06:32:00 PM PDT 24
Finished Jul 18 06:32:05 PM PDT 24
Peak memory 201616 kb
Host smart-8efb9e81-b9d7-49ae-b9a6-c65672f4fd3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263597377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.1263597377
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.2501668397
Short name T437
Test name
Test status
Simulation time 40633966921 ps
CPU time 53.46 seconds
Started Jul 18 06:32:08 PM PDT 24
Finished Jul 18 06:33:06 PM PDT 24
Peak memory 201680 kb
Host smart-73be2592-9c22-4e4e-8df1-b21cbcecb986
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501668397 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.
2501668397
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.3889347452
Short name T723
Test name
Test status
Simulation time 191147578262 ps
CPU time 116.32 seconds
Started Jul 18 06:32:00 PM PDT 24
Finished Jul 18 06:33:57 PM PDT 24
Peak memory 201880 kb
Host smart-b84c9b5a-ec47-49cc-8037-5ec498726c24
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889347452 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.3889347452
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.2156165480
Short name T652
Test name
Test status
Simulation time 488291894 ps
CPU time 0.88 seconds
Started Jul 18 06:32:08 PM PDT 24
Finished Jul 18 06:32:14 PM PDT 24
Peak memory 201520 kb
Host smart-65c591ce-bc48-422f-8e2d-ddf0227a9f36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156165480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.2156165480
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.1011537159
Short name T519
Test name
Test status
Simulation time 368617423570 ps
CPU time 406.52 seconds
Started Jul 18 06:32:05 PM PDT 24
Finished Jul 18 06:38:57 PM PDT 24
Peak memory 201728 kb
Host smart-85868d94-594e-45d4-be65-ab9cb6fddcc4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011537159 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gati
ng.1011537159
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.3562094564
Short name T331
Test name
Test status
Simulation time 490755588464 ps
CPU time 554.86 seconds
Started Jul 18 06:32:06 PM PDT 24
Finished Jul 18 06:41:27 PM PDT 24
Peak memory 201832 kb
Host smart-b2bbc65c-60db-4721-842d-a2dbe7dff607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562094564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.3562094564
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.716875683
Short name T259
Test name
Test status
Simulation time 161834766356 ps
CPU time 351.98 seconds
Started Jul 18 06:32:05 PM PDT 24
Finished Jul 18 06:38:02 PM PDT 24
Peak memory 201648 kb
Host smart-f4ec5047-09d3-4556-85fe-8f2a5509a12e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716875683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.716875683
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.1786790612
Short name T407
Test name
Test status
Simulation time 492475766081 ps
CPU time 1206.12 seconds
Started Jul 18 06:32:05 PM PDT 24
Finished Jul 18 06:52:15 PM PDT 24
Peak memory 201728 kb
Host smart-0d27d60b-3f57-4ea1-b318-58dca96933d5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786790612 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrup
t_fixed.1786790612
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.1217258647
Short name T696
Test name
Test status
Simulation time 164880518933 ps
CPU time 164.19 seconds
Started Jul 18 06:32:03 PM PDT 24
Finished Jul 18 06:34:50 PM PDT 24
Peak memory 201820 kb
Host smart-c3ff42b6-ee04-41e3-8f27-3ca893420623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217258647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.1217258647
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.1178140791
Short name T1
Test name
Test status
Simulation time 161639254692 ps
CPU time 25.93 seconds
Started Jul 18 06:32:06 PM PDT 24
Finished Jul 18 06:32:37 PM PDT 24
Peak memory 201724 kb
Host smart-049e58f9-dad3-4f88-8677-d1c308427c05
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178140791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixe
d.1178140791
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.2224796764
Short name T156
Test name
Test status
Simulation time 360741048075 ps
CPU time 210.13 seconds
Started Jul 18 06:32:04 PM PDT 24
Finished Jul 18 06:35:37 PM PDT 24
Peak memory 201760 kb
Host smart-4bf8c881-6eaa-4b6b-a18a-96eb0aab7265
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224796764 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_
wakeup.2224796764
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.3888203203
Short name T687
Test name
Test status
Simulation time 602962524216 ps
CPU time 1508.98 seconds
Started Jul 18 06:32:06 PM PDT 24
Finished Jul 18 06:57:21 PM PDT 24
Peak memory 201720 kb
Host smart-5ba29c11-4354-4717-919c-4d7e196e2bf2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888203203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
adc_ctrl_filters_wakeup_fixed.3888203203
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.1378953320
Short name T776
Test name
Test status
Simulation time 71553683831 ps
CPU time 393.75 seconds
Started Jul 18 06:32:03 PM PDT 24
Finished Jul 18 06:38:39 PM PDT 24
Peak memory 201812 kb
Host smart-7fc3bdd8-f18f-44fa-8640-9cff7f1e98d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378953320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.1378953320
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.2983251812
Short name T513
Test name
Test status
Simulation time 22904605663 ps
CPU time 13.49 seconds
Started Jul 18 06:32:06 PM PDT 24
Finished Jul 18 06:32:25 PM PDT 24
Peak memory 201508 kb
Host smart-1dad36f7-d2c3-45ea-ae9b-e0871d719f77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983251812 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.2983251812
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.1371362185
Short name T477
Test name
Test status
Simulation time 4833435862 ps
CPU time 3.59 seconds
Started Jul 18 06:32:06 PM PDT 24
Finished Jul 18 06:32:15 PM PDT 24
Peak memory 201600 kb
Host smart-0989d8a2-c2b8-4863-91b3-62444f5c34a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371362185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.1371362185
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.3917846636
Short name T498
Test name
Test status
Simulation time 6038392309 ps
CPU time 14.49 seconds
Started Jul 18 06:32:01 PM PDT 24
Finished Jul 18 06:32:16 PM PDT 24
Peak memory 201608 kb
Host smart-12c522d7-1dee-4415-8b12-41e3c7676f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917846636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.3917846636
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.1002776786
Short name T306
Test name
Test status
Simulation time 328453487283 ps
CPU time 400.49 seconds
Started Jul 18 06:32:06 PM PDT 24
Finished Jul 18 06:38:52 PM PDT 24
Peak memory 201740 kb
Host smart-615235a7-bd5e-4d7a-9d57-3cab6a20c923
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002776786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.
1002776786
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.2671880780
Short name T725
Test name
Test status
Simulation time 51553533032 ps
CPU time 129.8 seconds
Started Jul 18 06:32:06 PM PDT 24
Finished Jul 18 06:34:22 PM PDT 24
Peak memory 211080 kb
Host smart-2d5aa0be-644a-479c-a51d-699f7a19aab8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671880780 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.2671880780
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.3644467981
Short name T440
Test name
Test status
Simulation time 465340435 ps
CPU time 1.61 seconds
Started Jul 18 06:32:07 PM PDT 24
Finished Jul 18 06:32:14 PM PDT 24
Peak memory 201556 kb
Host smart-cf0bb7ce-78a8-4f30-ac2a-33f667833480
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644467981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.3644467981
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.313394548
Short name T264
Test name
Test status
Simulation time 525062360205 ps
CPU time 1149.88 seconds
Started Jul 18 06:32:12 PM PDT 24
Finished Jul 18 06:51:27 PM PDT 24
Peak memory 201736 kb
Host smart-55a1123a-950f-4860-87cd-a61730a950c1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313394548 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gatin
g.313394548
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.254388013
Short name T269
Test name
Test status
Simulation time 341590036252 ps
CPU time 216.82 seconds
Started Jul 18 06:32:07 PM PDT 24
Finished Jul 18 06:35:49 PM PDT 24
Peak memory 201604 kb
Host smart-0ccd9247-8307-4ea9-a161-56bd844d4845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254388013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.254388013
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.299185933
Short name T364
Test name
Test status
Simulation time 485147252166 ps
CPU time 975.51 seconds
Started Jul 18 06:32:05 PM PDT 24
Finished Jul 18 06:48:25 PM PDT 24
Peak memory 201740 kb
Host smart-228770da-df8c-4463-881b-7c95d9490a49
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=299185933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt
_fixed.299185933
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.1572988043
Short name T529
Test name
Test status
Simulation time 332825227569 ps
CPU time 95.83 seconds
Started Jul 18 06:32:06 PM PDT 24
Finished Jul 18 06:33:47 PM PDT 24
Peak memory 201656 kb
Host smart-5ed29b71-c673-433a-9e10-e45e5eb53872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572988043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.1572988043
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.1310302277
Short name T405
Test name
Test status
Simulation time 333562957308 ps
CPU time 117.57 seconds
Started Jul 18 06:32:07 PM PDT 24
Finished Jul 18 06:34:10 PM PDT 24
Peak memory 201632 kb
Host smart-31c25748-eacb-4dd8-9f34-b50f79d16534
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310302277 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixe
d.1310302277
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.2409158670
Short name T334
Test name
Test status
Simulation time 372627042243 ps
CPU time 231.22 seconds
Started Jul 18 06:32:07 PM PDT 24
Finished Jul 18 06:36:04 PM PDT 24
Peak memory 201564 kb
Host smart-d97f096c-9944-4b93-b9da-961e8b7733fa
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409158670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_
wakeup.2409158670
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.2875585713
Short name T459
Test name
Test status
Simulation time 201491343404 ps
CPU time 478.41 seconds
Started Jul 18 06:32:07 PM PDT 24
Finished Jul 18 06:40:11 PM PDT 24
Peak memory 201728 kb
Host smart-d27fe81f-6097-47f8-8685-7255e4b609b0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875585713 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
adc_ctrl_filters_wakeup_fixed.2875585713
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.638865457
Short name T49
Test name
Test status
Simulation time 110147883809 ps
CPU time 398.47 seconds
Started Jul 18 06:32:07 PM PDT 24
Finished Jul 18 06:38:51 PM PDT 24
Peak memory 202168 kb
Host smart-22f1ca96-1ae0-4c27-9983-dcdc5a636063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638865457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.638865457
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.1096883780
Short name T660
Test name
Test status
Simulation time 32273995907 ps
CPU time 9.78 seconds
Started Jul 18 06:32:07 PM PDT 24
Finished Jul 18 06:32:22 PM PDT 24
Peak memory 201672 kb
Host smart-93da8889-65b8-48f6-a174-96755e404274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096883780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.1096883780
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.1792920626
Short name T448
Test name
Test status
Simulation time 5088603531 ps
CPU time 7.41 seconds
Started Jul 18 06:32:07 PM PDT 24
Finished Jul 18 06:32:20 PM PDT 24
Peak memory 201672 kb
Host smart-11ba2790-b7bc-48c8-a029-c14098a6019e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792920626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.1792920626
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.3940724087
Short name T380
Test name
Test status
Simulation time 5754406441 ps
CPU time 13.96 seconds
Started Jul 18 06:32:07 PM PDT 24
Finished Jul 18 06:32:27 PM PDT 24
Peak memory 201600 kb
Host smart-566d9379-db2d-4622-ac3e-057d7bf1f124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940724087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.3940724087
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.2757560711
Short name T276
Test name
Test status
Simulation time 169499554215 ps
CPU time 108.99 seconds
Started Jul 18 06:32:07 PM PDT 24
Finished Jul 18 06:34:02 PM PDT 24
Peak memory 201724 kb
Host smart-6b505f11-8f8f-41a6-807d-689060e00c00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757560711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.
2757560711
Directory /workspace/9.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.3397134006
Short name T342
Test name
Test status
Simulation time 266336081039 ps
CPU time 327.46 seconds
Started Jul 18 06:32:12 PM PDT 24
Finished Jul 18 06:37:44 PM PDT 24
Peak memory 210408 kb
Host smart-a4a816eb-23ac-4524-966b-0b88590e81a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397134006 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.3397134006
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%