Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	7039	1			T1	7		T3	18		T4	20
testmodes[AdcCtrlTestmodeNormal]	5555	1			T1	4		T3	29		T5	2
testmodes[AdcCtrlTestmodeLowpower]	5470	1			T2	1		T3	65		T8	1
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	3925	1			T1	3		T3	5		T4	19
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1740	1			T1	3		T3	9		T38	20
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1268	1			T3	4		T38	17		T39	19
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1728	1			T1	3		T3	12		T38	15
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	2140	1			T1	1		T3	12		T5	1
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1340	1			T3	5		T38	23		T39	21
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1270	1			T3	1		T38	22		T39	17
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1331	1			T3	8		T38	18		T39	22
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2622	1			T3	55		T33	2		T44	11