Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26593

1

T1

11

T2

27

T3

125

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22809

1

T1

11

T3

124

T4

20

auto[ADC_CTRL_FILTER_COND_OUT]

3784

1

T2

27

T3

1

T5

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20563

1

T1

11

T2

27

T3

107

auto[1]

6030

1

T3

18

T5

1

T6

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22300

1

T1

11

T2

14

T3

119

auto[1]

4293

1

T2

13

T3

6

T12

28

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	10	1			T173	1		T194	9		-	-
values[0]	68	1			T195	12		T196	12		T197	6
values[1]	676	1			T6	1		T12	14		T135	10
values[2]	731	1			T12	3		T124	1		T73	25
values[3]	834	1			T3	15		T10	14		T35	25
values[4]	708	1			T2	27		T125	1		T36	21
values[5]	2772	1			T7	1		T8	16		T9	13
values[6]	687	1			T3	4		T34	19		T25	5
values[7]	830	1			T33	18		T35	11		T36	33
values[8]	893	1			T5	1		T36	20		T37	25
values[9]	1305	1			T5	1		T12	14		T124	1
minimum	17079	1			T1	11		T3	106		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	968	1			T6	1		T12	17		T124	1
values[1]	693	1			T73	25		T123	1		T27	4
values[2]	742	1			T3	15		T10	14		T136	29
values[3]	2831	1			T8	16		T9	13		T11	2
values[4]	730	1			T2	27		T3	3		T7	1
values[5]	779	1			T3	1		T34	19		T161	4
values[6]	729	1			T33	18		T35	11		T36	53
values[7]	807	1			T5	1		T73	1		T135	4
values[8]	1051	1			T124	1		T33	26		T74	10
values[9]	184	1			T5	1		T12	14		T33	7
minimum	17079	1			T1	11		T3	106		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22357

1

T1

11

T2

14

T3

118

auto[1]

4236

1

T2

13

T3

7

T8

15

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T12	1		T124	1		T26	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	324	1			T6	1		T12	1		T135	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T27	4		T119	11		T122	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T73	2		T123	1		T127	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T3	10		T10	14		T136	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T136	3		T126	1		T137	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1568	1			T8	16		T9	13		T11	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T35	15		T13	7		T161	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T3	2		T7	1		T123	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T2	14		T72	1		T30	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T34	9		T161	1		T120	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T3	1		T34	1		T27	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T35	1		T36	21		T37	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T33	10		T36	13		T74	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T135	1		T170	15		T198	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T5	1		T73	1		T127	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	300	1			T124	1		T33	14		T13	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T74	10		T123	1		T13	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T5	1		T33	7		T119	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T12	1		T125	1		T159	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16945	1			T1	11		T3	106		T4	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T12	2		T26	2		T121	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T12	13		T135	9		T120	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T119	10		T199	2		T200	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T73	23		T127	5		T28	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T3	5		T136	9		T126	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T136	7		T126	6		T201	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	954	1			T36	10		T177	23		T202	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T35	10		T13	2		T161	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T3	1		T25	1		T120	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T2	13		T30	12		T203	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T34	9		T161	3		T120	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T27	1		T138	9		T145	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T35	10		T36	12		T37	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T33	8		T36	7		T117	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T135	3		T198	14		T204	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T127	10		T114	18		T30	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T33	12		T13	1		T135	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T13	1		T117	11		T143	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T205	1		T206	2		T207	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T12	13		T208	12		T200	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T13	2		T27	7		T114	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T173	1		T194	8		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T195	12		T196	3		T209	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T197	6		T210	11		T211	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T26	7		T27	4		T119	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T6	1		T12	1		T135	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T12	1		T124	1		T170	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T73	2		T127	1		T28	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T3	10		T10	14		T136	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T35	15		T123	1		T126	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T125	1		T36	11		T212	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T2	14		T161	1		T136	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1480	1			T7	1		T8	16		T9	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T72	1		T13	7		T29	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T3	2		T34	9		T25	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T3	1		T34	1		T138	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T35	1		T36	21		T161	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T33	10		T117	1		T27	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T37	13		T26	2		T170	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T5	1		T36	13		T74	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	348	1			T5	1		T124	1		T33	21
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	398	1			T12	1		T125	1		T73	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16945	1			T1	11		T3	106		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T194	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T196	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T211	1		T213	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T26	2		T119	10		T121	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T12	13		T135	9		T120	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T12	2		T121	7		T199	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T73	23		T127	5		T28	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T3	5		T136	9		T126	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T35	10		T126	6		T140	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T36	10		T30	1		T145	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T2	13		T161	6		T136	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1016	1			T177	23		T202	11		T94	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T13	2		T30	12		T214	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T3	1		T34	9		T25	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T138	9		T145	8		T23	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T35	10		T36	12		T161	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T33	8		T117	10		T27	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T37	12		T215	12		T216	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T36	7		T201	5		T217	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T33	12		T13	1		T135	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	360	1			T12	13		T13	1		T117	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T13	2		T27	7		T114	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T12	3		T124	1		T26	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	317	1			T6	1		T12	14		T135	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T27	2		T119	11		T122	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T73	25		T123	1		T127	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T3	8		T10	1		T136	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T136	8		T126	7		T137	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1289	1			T8	1		T9	1		T11	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T35	11		T13	5		T161	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T3	3		T7	1		T123	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T2	14		T72	1		T30	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T34	10		T161	4		T120	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T3	1		T34	1		T27	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T35	11		T36	13		T37	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T33	9		T36	8		T74	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T135	4		T170	1		T198	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T5	1		T73	1		T127	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T124	1		T33	13		T13	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	321	1			T74	1		T123	1		T13	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T5	1		T33	1		T119	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T12	14		T125	1		T159	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17079	1			T1	11		T3	106		T4	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T26	4		T170	10		T128	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T118	11		T30	9		T218	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T27	2		T119	10		T122	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T28	3		T140	5		T219	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T3	7		T10	13		T136	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T136	2		T201	12		T220	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1233	1			T8	15		T9	12		T36	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T35	14		T13	4		T118	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T25	1		T221	5		T199	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T2	13		T222	15		T203	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T34	8		T139	10		T198	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T27	1		T145	9		T219	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T36	20		T37	12		T160	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T33	9		T36	12		T74	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T170	14		T198	14		T204	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T127	5		T114	12		T201	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T33	13		T13	3		T26	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T74	9		T13	1		T143	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T33	6		T119	4		T223	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T208	8		T175	16		T224	8

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T173	1		T194	2		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T195	1		T196	10		T209	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T197	1		T210	1		T211	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T26	5		T27	2		T119	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T6	1		T12	14		T135	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T12	3		T124	1		T170	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T73	25		T127	6		T28	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T3	8		T10	1		T136	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T35	11		T123	1		T126	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T125	1		T36	11		T212	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T2	14		T161	7		T136	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1350	1			T7	1		T8	1		T9	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T72	1		T13	5		T29	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T3	3		T34	10		T25	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T3	1		T34	1		T138	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T35	11		T36	13		T161	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T33	9		T117	11		T27	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T37	13		T26	1		T170	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T5	1		T36	8		T74	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T5	1		T124	1		T33	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	442	1			T12	14		T125	1		T73	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17079	1			T1	11		T3	106		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T194	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T195	11		T196	2		T209	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T197	5		T210	10		T213	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T26	4		T27	2		T119	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T118	11		T30	9		T31	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T170	10		T199	12		T225	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T28	3		T218	10		T219	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T3	7		T10	13		T136	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T35	14		T140	5		T201	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T36	10		T212	2		T30	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T2	13		T136	2		T118	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1146	1			T8	15		T9	12		T75	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T13	4		T222	15		T226	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T34	8		T25	1		T221	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T145	9		T23	7		T219	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T36	20		T160	9		T139	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T33	9		T27	1		T127	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T37	12		T26	1		T170	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T36	12		T74	9		T201	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T33	19		T13	3		T119	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	316	1			T74	9		T13	1		T143	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22357

1

T1

11

T2

14

T3

118

auto[1]

auto[0]

4236

1

T2

13

T3

7

T8

15

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26593

1

T1

11

T2

27

T3

125

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22920

1

T1

11

T2

27

T3

125

auto[ADC_CTRL_FILTER_COND_OUT]

3673

1

T5

1

T6

1

T10

14

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20745

1

T1

11

T3

110

T4

20

auto[1]

5848

1

T2

27

T3

15

T6

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22300

1

T1

11

T2

14

T3

119

auto[1]

4293

1

T2

13

T3

6

T12

28

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	6	1			T227	5		T228	1		-	-
values[0]	36	1			T13	3		T136	19		T26	9
values[1]	545	1			T3	15		T74	10		T136	10
values[2]	3081	1			T3	3		T5	1		T8	16
values[3]	614	1			T6	1		T125	1		T72	1
values[4]	1035	1			T3	1		T5	1		T124	1
values[5]	635	1			T12	3		T34	1		T135	4
values[6]	605	1			T7	1		T10	14		T33	7
values[7]	815	1			T2	27		T12	14		T36	20
values[8]	669	1			T12	14		T34	18		T36	33
values[9]	1473	1			T33	18		T125	1		T36	21
minimum	17079	1			T1	11		T3	106		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	792	1			T3	18		T124	1		T35	25
values[1]	2994	1			T5	1		T8	16		T9	13
values[2]	851	1			T6	1		T125	1		T72	1
values[3]	796	1			T5	1		T124	1		T34	1
values[4]	619	1			T3	1		T7	1		T10	14
values[5]	714	1			T36	20		T73	1		T126	5
values[6]	774	1			T2	27		T12	14		T37	25
values[7]	745	1			T12	14		T34	18		T36	54
values[8]	1035	1			T33	18		T125	1		T25	5
values[9]	194	1			T73	14		T26	2		T28	8
minimum	17079	1			T1	11		T3	106		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22357

1

T1

11

T2

14

T3

118

auto[1]

4236

1

T2

13

T3

7

T8

15

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T3	12		T124	1		T35	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T117	1		T136	3		T26	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1528	1			T5	1		T8	16		T9	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T33	14		T74	10		T123	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T72	1		T73	1		T117	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T6	1		T125	1		T135	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T34	1		T13	7		T118	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T5	1		T124	1		T121	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T3	1		T7	1		T12	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T10	14		T33	7		T229	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T36	13		T73	1		T126	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T27	4		T127	1		T137	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T2	14		T12	1		T37	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T123	1		T114	13		T160	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T34	9		T13	4		T118	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T12	1		T36	32		T123	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T33	10		T125	1		T126	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	309	1			T25	4		T120	1		T212	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T26	2		T230	1		T231	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T73	1		T28	5		T225	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16945	1			T1	11		T3	106		T4	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T3	6		T35	10		T13	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T117	11		T136	7		T26	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1014	1			T35	10		T177	23		T202	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T33	12		T161	6		T138	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T73	10		T117	10		T119	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T135	9		T198	9		T219	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T13	2		T127	2		T160	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T121	10		T139	8		T199	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T12	2		T135	3		T221	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T140	6		T232	7		T233	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T36	7		T126	4		T120	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T127	5		T199	11		T200	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T2	13		T12	13		T37	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T114	18		T160	11		T14	21
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T34	9		T13	1		T127	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T12	13		T36	22		T135	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T33	8		T126	6		T27	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T25	1		T120	9		T138	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T231	4		T227	4		T234	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T73	13		T28	3		T164	22
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T13	2		T27	7		T114	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T227	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T228	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T13	2		T136	10		T29	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T26	7		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T3	10		T74	10		T30	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T136	3		T120	1		T114	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1574	1			T3	2		T5	1		T8	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T33	14		T74	10		T161	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T72	1		T13	7		T117	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T6	1		T125	1		T123	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	301	1			T3	1		T118	12		T160	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T5	1		T124	1		T121	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T12	1		T34	1		T135	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T137	1		T229	12		T140	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T7	1		T120	1		T159	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T10	14		T33	7		T127	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T2	14		T12	1		T36	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T27	4		T114	13		T160	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T34	9		T37	13		T27	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T12	1		T36	21		T123	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	375	1			T33	10		T125	1		T13	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	420	1			T36	11		T73	1		T25	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16945	1			T1	11		T3	106		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T227	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T13	1		T136	9		T29	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T26	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T3	5		T30	24		T232	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T136	7		T120	7		T114	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1032	1			T3	1		T35	20		T73	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T33	12		T161	6		T117	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T13	2		T117	10		T119	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T135	9		T208	12		T198	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T160	7		T154	2		T145	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T121	10		T139	8		T199	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T12	2		T135	3		T127	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T140	6		T235	12		T233	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T120	2		T131	13		T236	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T127	5		T199	11		T200	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T2	13		T12	13		T36	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T114	18		T160	11		T14	21
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T34	9		T37	12		T27	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T12	13		T36	12		T135	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T33	8		T13	1		T126	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	406	1			T36	10		T73	13		T25	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T13	2		T27	7		T114	1