Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26593

1

T1

11

T2

27

T3

125

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22797

1

T1

11

T3

109

T4

20

auto[ADC_CTRL_FILTER_COND_OUT]

3796

1

T2

27

T3

16

T5

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20679

1

T1

11

T2

27

T3

121

auto[1]

5914

1

T3

4

T8

16

T9

13

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22300

1

T1

11

T2

14

T3

119

auto[1]

4293

1

T2

13

T3

6

T12

28

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	27	1			T36	21		T297	2		T298	4
values[0]	24	1			T225	13		T277	1		T299	9
values[1]	708	1			T12	14		T161	7		T136	29
values[2]	899	1			T3	4		T10	14		T34	19
values[3]	756	1			T73	14		T74	10		T123	1
values[4]	794	1			T5	1		T36	20		T37	25
values[5]	669	1			T33	7		T118	1		T127	16
values[6]	746	1			T7	1		T33	26		T125	1
values[7]	666	1			T3	15		T73	1		T13	5
values[8]	2928	1			T2	27		T5	1		T8	16
values[9]	1297	1			T6	1		T12	3		T124	1
minimum	17079	1			T1	11		T3	106		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	983	1			T12	14		T35	25		T161	7
values[1]	834	1			T3	4		T10	14		T34	19
values[2]	769	1			T74	10		T127	6		T155	1
values[3]	778	1			T36	20		T37	25		T117	11
values[4]	621	1			T5	1		T33	7		T135	4
values[5]	749	1			T7	1		T33	26		T125	1
values[6]	2950	1			T3	15		T8	16		T9	13
values[7]	663	1			T2	27		T12	14		T124	1
values[8]	901	1			T5	1		T6	1		T12	3
values[9]	246	1			T124	1		T36	33		T135	13
minimum	17099	1			T1	11		T3	106		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22357

1

T1

11

T2

14

T3

118

auto[1]

4236

1

T2

13

T3

7

T8

15

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T12	1		T161	1		T136	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	322	1			T35	15		T120	1		T218	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T3	2		T10	14		T73	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T3	1		T34	10		T74	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T74	10		T127	1		T155	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T200	1		T140	6		T220	23
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T37	13		T117	1		T27	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T36	13		T26	7		T170	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T5	1		T33	7		T135	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T159	1		T199	12		T300	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T7	1		T33	14		T125	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T72	1		T13	4		T117	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1556	1			T8	16		T9	13		T11	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T3	10		T114	13		T212	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T73	1		T30	1		T269	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T2	14		T12	1		T124	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T12	1		T35	1		T123	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T5	1		T6	1		T125	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T135	1		T141	4		T293	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T124	1		T36	21		T301	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16946	1			T1	11		T3	106		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T145	10		T302	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T12	13		T161	6		T136	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T35	10		T120	7		T218	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T3	1		T73	13		T13	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T34	9		T161	3		T135	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T127	5		T203	11		T199	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T200	12		T140	6		T220	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T37	12		T117	10		T127	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T36	7		T26	2		T160	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T135	3		T28	3		T138	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T199	11		T198	14		T219	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T33	12		T114	4		T138	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T13	1		T117	11		T143	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1015	1			T177	23		T202	11		T126	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T3	5		T114	18		T138	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T73	10		T30	5		T269	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T2	13		T12	13		T33	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T12	2		T35	10		T25	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T36	10		T127	2		T208	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T135	12		T293	9		T83	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T36	12		T255	13		T152	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T13	2		T27	7		T114	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T145	8		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T298	4		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T36	11		T297	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T225	13		T303	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T277	1		T299	9		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T12	1		T161	1		T136	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T218	11		T145	10		T268	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T3	2		T10	14		T13	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T3	1		T34	10		T35	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T73	1		T123	1		T127	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T74	10		T161	1		T119	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T5	1		T37	13		T74	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T36	13		T26	7		T170	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T33	7		T118	1		T127	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T159	1		T199	12		T300	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T7	1		T33	14		T125	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T72	1		T117	1		T143	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T73	1		T170	12		T29	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T3	10		T13	4		T114	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1520	1			T8	16		T9	13		T11	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T2	14		T5	1		T12	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	347	1			T12	1		T35	1		T123	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	335	1			T6	1		T124	1		T33	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16945	1			T1	11		T3	106		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T36	10		T297	1		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T12	13		T161	6		T136	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T218	12		T145	8		T148	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T3	1		T13	2		T126	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T34	9		T35	10		T135	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T73	13		T127	5		T199	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T161	3		T119	10		T208	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T37	12		T117	10		T221	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T36	7		T26	2		T160	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T127	10		T28	3		T139	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T199	11		T198	14		T201	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T33	12		T135	3		T114	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T117	11		T143	4		T27	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T138	13		T30	8		T132	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T3	5		T13	1		T114	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1028	1			T73	10		T177	23		T202	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T2	13		T12	13		T30	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	302	1			T12	2		T35	10		T25	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	313	1			T33	8		T36	12		T13	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T13	2		T27	7		T114	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T12	14		T161	7		T136	18
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T35	11		T120	8		T218	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T3	3		T10	1		T73	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T3	1		T34	11		T74	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T74	1		T127	6		T155	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T200	13		T140	7		T220	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T37	13		T117	11		T27	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T36	8		T26	5		T170	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T5	1		T33	1		T135	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T159	1		T199	12		T300	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T7	1		T33	13		T125	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T72	1		T13	2		T117	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1352	1			T8	1		T9	1		T11	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T3	8		T114	19		T212	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T73	11		T30	6		T269	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T2	14		T12	14		T124	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T12	3		T35	11		T123	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T5	1		T6	1		T125	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T135	13		T141	1		T293	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T124	1		T36	13		T301	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17080	1			T1	11		T3	106		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T145	9		T302	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T136	11		T170	14		T221	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T35	14		T218	10		T219	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T10	13		T13	4		T154	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T34	8		T74	9		T118	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T74	9		T128	11		T203	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T140	5		T220	21		T147	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T37	12		T27	2		T127	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T36	12		T26	4		T170	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T33	6		T118	11		T28	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T199	11		T225	3		T198	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T33	13		T114	8		T30	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T13	3		T143	13		T26	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1219	1			T8	15		T9	12		T75	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T3	7		T114	12		T212	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T140	6		T304	11		T32	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T2	13		T33	9		T13	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T25	1		T119	4		T128	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T36	10		T127	7		T208	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T141	3		T293	5		T83	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T36	20		T195	11		T305	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T145	9		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T298	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T36	11		T297	2		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T225	1		T303	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T277	1		T299	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T12	14		T161	7		T136	18
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T218	13		T145	9		T268	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T3	3		T10	1		T13	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T3	1		T34	11		T35	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T73	14		T123	1		T127	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T74	1		T161	4		T119	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T5	1		T37	13		T74	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T36	8		T26	5		T170	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T33	1		T118	1		T127	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T159	1		T199	12		T300	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T7	1		T33	13		T125	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T72	1		T117	12		T143	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T73	1		T170	1		T29	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T3	8		T13	2		T114	19
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1358	1			T8	1		T9	1		T11	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T2	14		T5	1		T12	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	379	1			T12	3		T35	11		T123	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	389	1			T6	1		T124	1		T33	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17079	1			T1	11		T3	106		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T298	3		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T36	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T225	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T299	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T136	11		T170	14		T221	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T218	10		T145	9		T224	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T10	13		T13	4		T154	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T34	8		T35	14		T118	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T128	11		T199	12		T174	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T74	9		T119	10		T208	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T37	12		T74	9		T27	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T36	12		T26	4		T170	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T33	6		T127	5		T28	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T199	11		T198	14		T201	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T33	13		T118	11		T114	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T143	13		T26	1		T27	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T170	11		T30	9		T237	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T3	7		T13	3		T114	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1190	1			T8	15		T9	12		T75	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T2	13		T198	11		T145	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T25	1		T119	4		T128	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T33	9		T36	20		T13	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22357

1

T1

11

T2

14

T3

118

auto[1]

auto[0]

4236

1

T2

13

T3

7

T8

15