Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26593

1

T1

11

T2

27

T3

125

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23005

1

T1

11

T3

122

T4

20

auto[ADC_CTRL_FILTER_COND_OUT]

3588

1

T2

27

T3

3

T6

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20276

1

T1

11

T3

121

T4

20

auto[1]

6317

1

T2

27

T3

4

T5

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22300

1

T1

11

T2

14

T3

119

auto[1]

4293

1

T2

13

T3

6

T12

28

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	86	1			T143	18		T226	7		T149	24
values[0]	66	1			T306	1		T223	9		T262	20
values[1]	735	1			T36	20		T117	12		T27	6
values[2]	852	1			T3	15		T35	25		T73	1
values[3]	877	1			T7	1		T124	1		T34	18
values[4]	572	1			T124	1		T36	33		T13	9
values[5]	3041	1			T5	1		T8	16		T9	13
values[6]	682	1			T3	3		T10	14		T125	1
values[7]	714	1			T3	1		T12	3		T33	44
values[8]	714	1			T5	1		T6	1		T36	21
values[9]	1175	1			T2	27		T12	14		T33	7
minimum	17079	1			T1	11		T3	106		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1122	1			T3	15		T35	25		T117	23
values[1]	709	1			T36	20		T73	1		T13	5
values[2]	785	1			T7	1		T124	2		T34	18
values[3]	3045	1			T5	1		T8	16		T9	13
values[4]	629	1			T3	3		T12	14		T125	1
values[5]	746	1			T10	14		T12	3		T33	18
values[6]	748	1			T3	1		T33	26		T36	21
values[7]	529	1			T5	1		T6	1		T33	7
values[8]	850	1			T2	27		T12	14		T34	1
values[9]	342	1			T125	1		T118	1		T26	2
minimum	17088	1			T1	11		T3	106		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22357

1

T1

11

T2

14

T3

118

auto[1]

4236

1

T2

13

T3

7

T8

15

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	358	1			T3	10		T35	15		T117	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T117	1		T135	1		T27	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T36	13		T73	1		T13	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T199	13		T198	12		T174	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T124	2		T123	1		T155	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T7	1		T34	9		T74	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1579	1			T5	1		T8	16		T9	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T36	21		T73	1		T135	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T12	1		T26	7		T30	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T3	2		T125	1		T160	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T73	1		T161	1		T126	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T10	14		T12	1		T33	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T3	1		T33	14		T36	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T118	12		T128	12		T145	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T5	1		T123	1		T25	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T6	1		T33	7		T123	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T74	10		T135	1		T118	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T2	14		T12	1		T34	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T125	1		T118	1		T219	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T26	2		T119	11		T127	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16945	1			T1	11		T3	106		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T214	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T3	5		T35	10		T117	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T117	10		T135	9		T27	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T36	7		T13	1		T136	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T199	2		T198	9		T174	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T139	8		T174	11		T220	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T34	9		T138	13		T203	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1043	1			T13	2		T161	6		T177	23
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T36	12		T73	10		T135	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T12	13		T26	2		T30	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T3	1		T160	7		T121	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T73	13		T161	3		T126	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T12	2		T33	8		T35	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T33	12		T36	10		T37	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T145	4		T219	11		T172	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T25	1		T136	7		T221	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T138	9		T140	10		T214	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T135	3		T143	4		T29	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T2	13		T12	13		T120	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T219	11		T220	12		T171	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T119	10		T127	10		T226	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T13	2		T27	7		T114	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T214	8		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T143	14		T283	1		T266	11
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T226	4		T149	11		T307	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T262	20		T308	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T306	1		T223	9		T151	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T36	13		T117	1		T121	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T27	5		T159	1		T14	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T3	10		T35	15		T73	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T117	1		T135	1		T138	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T124	1		T13	4		T127	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T7	1		T34	9		T74	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T124	1		T13	7		T28	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T36	21		T135	1		T119	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1567	1			T5	1		T8	16		T9	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T73	1		T126	1		T170	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T73	1		T161	1		T26	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T3	2		T10	14		T125	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T3	1		T33	14		T37	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T12	1		T33	10		T128	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T5	1		T36	11		T123	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T6	1		T123	1		T118	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	355	1			T125	1		T74	10		T25	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T2	14		T12	1		T33	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16945	1			T1	11		T3	106		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T143	4		T266	3		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T226	3		T149	13		T307	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T151	7		T288	14		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T36	7		T117	11		T121	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T27	1		T14	21		T214	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T3	5		T35	10		T136	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T117	10		T135	9		T138	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T13	1		T127	2		T139	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T34	9		T121	11		T203	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T13	2		T28	3		T198	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T36	12		T135	12		T120	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1091	1			T12	13		T161	6		T177	23
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T73	10		T126	6		T160	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T73	13		T161	3		T26	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T3	1		T35	10		T13	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T33	12		T37	12		T126	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T12	2		T33	8		T219	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T36	10		T136	7		T221	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T138	9		T145	4		T140	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T25	1		T135	3		T29	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T2	13		T12	13		T119	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T13	2		T27	7		T114	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	329	1			T3	8		T35	11		T117	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T117	11		T135	10		T27	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T36	8		T73	1		T13	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T199	3		T198	10		T174	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T124	2		T123	1		T155	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T7	1		T34	10		T74	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1391	1			T5	1		T8	1		T9	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T36	13		T73	11		T135	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T12	14		T26	5		T30	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T3	3		T125	1		T160	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T73	14		T161	4		T126	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T10	1		T12	3		T33	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T3	1		T33	13		T36	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T118	1		T128	1		T145	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T5	1		T123	1		T25	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T6	1		T33	1		T123	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T74	1		T135	4		T118	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T2	14		T12	14		T34	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T125	1		T118	1		T219	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T26	1		T119	11		T127	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17079	1			T1	11		T3	106		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T214	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T3	7		T35	14		T208	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T27	1		T222	15		T14	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T36	12		T13	3		T136	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T199	12		T198	11		T174	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T139	10		T225	10		T174	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T34	8		T74	9		T203	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1231	1			T8	15		T9	12		T75	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T36	20		T170	11		T119	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T26	4		T225	3		T198	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T160	9		T217	3		T241	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T114	8		T122	2		T145	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T10	13		T33	9		T13	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T33	13		T36	10		T37	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T118	11		T128	11		T145	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T25	1		T136	2		T221	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T33	6		T27	2		T140	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T74	9		T118	7		T143	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T2	13		T154	4		T128	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T219	7		T220	12		T274	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T26	1		T119	10		T127	5

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T143	5		T283	1		T266	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T226	4		T149	14		T307	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T262	1		T308	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T306	1		T223	1		T151	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T36	8		T117	12		T121	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T27	5		T159	1		T14	26
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T3	8		T35	11		T73	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T117	11		T135	10		T138	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T124	1		T13	2		T127	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T7	1		T34	10		T74	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T124	1		T13	5		T28	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T36	13		T135	13		T119	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1431	1			T5	1		T8	1		T9	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T73	11		T126	7		T170	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T73	14		T161	4		T26	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T3	3		T10	1		T125	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T3	1		T33	13		T37	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T12	3		T33	9		T128	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T5	1		T36	11		T123	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T6	1		T123	1		T118	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	313	1			T125	1		T74	1		T25	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	351	1			T2	14		T12	14		T33	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17079	1			T1	11		T3	106		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T143	13		T266	10		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T226	3		T149	10		T307	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T262	19		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T223	8		T151	5		T197	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T36	12		T208	11		T229	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T27	1		T14	11		T164	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T3	7		T35	14		T136	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T222	15		T174	11		T141	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T13	3		T127	7		T139	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T34	8		T74	9		T203	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T13	4		T28	3		T198	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T36	20		T119	4		T212	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1227	1			T8	15		T9	12		T75	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T170	11		T160	9		T238	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T26	4		T225	3		T248	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T10	13		T13	1		T114	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T33	13		T37	12		T114	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T33	9		T128	11		T219	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T36	10		T136	2		T221	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T118	11		T128	12		T145	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T74	9		T25	1		T118	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T2	13		T33	6		T26	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22357

1

T1

11

T2

14

T3

118

auto[1]

auto[0]

4236

1

T2

13

T3

7

T8

15