Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26593

1

T1

11

T2

27

T3

125

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22825

1

T1

11

T3

122

T4

20

auto[ADC_CTRL_FILTER_COND_OUT]

3768

1

T2

27

T3

3

T6

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20077

1

T1

11

T3

121

T4

20

auto[1]

6516

1

T2

27

T3

4

T5

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22300

1

T1

11

T2

14

T3

119

auto[1]

4293

1

T2

13

T3

6

T12

28

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	291	1			T125	1		T72	1		T118	1
values[0]	40	1			T117	12		T223	9		T151	13
values[1]	777	1			T36	20		T135	10		T27	6
values[2]	908	1			T3	15		T35	25		T73	1
values[3]	776	1			T124	1		T34	18		T74	10
values[4]	589	1			T7	1		T124	1		T36	33
values[5]	3008	1			T5	1		T8	16		T9	13
values[6]	752	1			T3	3		T10	14		T125	1
values[7]	710	1			T3	1		T12	3		T33	44
values[8]	699	1			T5	1		T6	1		T36	21
values[9]	964	1			T2	27		T12	14		T33	7
minimum	17079	1			T1	11		T3	106		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	877	1			T3	15		T35	25		T36	20
values[1]	764	1			T73	1		T123	1		T13	5
values[2]	781	1			T7	1		T124	2		T34	18
values[3]	3006	1			T5	1		T8	16		T9	13
values[4]	657	1			T3	3		T12	14		T125	1
values[5]	732	1			T10	14		T12	3		T35	11
values[6]	723	1			T3	1		T33	44		T36	21
values[7]	569	1			T5	1		T6	1		T33	7
values[8]	992	1			T2	27		T12	14		T34	1
values[9]	188	1			T125	1		T118	1		T26	2
minimum	17304	1			T1	11		T3	106		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22357

1

T1

11

T2

14

T3

118

auto[1]

4236

1

T2

13

T3

7

T8

15

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T3	10		T35	15		T127	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T36	13		T135	1		T27	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T73	1		T123	1		T13	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T117	1		T199	13		T198	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T7	1		T124	2		T74	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T34	9		T127	8		T138	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1580	1			T5	1		T8	16		T9	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T36	21		T126	1		T170	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T26	7		T225	4		T198	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T3	2		T12	1		T125	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T37	13		T73	1		T161	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T10	14		T12	1		T35	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T3	1		T33	14		T36	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T33	10		T118	12		T128	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T5	1		T123	1		T25	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T6	1		T33	7		T123	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	297	1			T74	10		T136	3		T118	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T2	14		T12	1		T34	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T125	1		T118	1		T26	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T127	6		T226	4		T149	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17015	1			T1	11		T3	106		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T159	1		T223	9		T235	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T3	5		T35	10		T127	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T36	7		T135	9		T27	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T13	1		T136	9		T269	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T117	10		T199	2		T198	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T139	8		T174	11		T220	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T34	9		T127	2		T138	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1063	1			T13	2		T161	6		T177	23
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T36	12		T126	6		T120	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T26	2		T198	14		T132	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T3	1		T12	13		T73	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T37	12		T73	13		T161	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T12	2		T35	10		T13	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T33	12		T36	10		T160	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T33	8		T145	4		T219	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T25	1		T221	5		T30	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T138	9		T140	10		T214	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T136	7		T143	4		T29	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T2	13		T12	13		T135	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T274	10		T266	3		T20	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T127	10		T226	3		T149	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T13	2		T117	11		T27	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T235	12		T256	2		T151	7

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T125	1		T118	1		T143	14
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T72	1		T170	15		T127	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T117	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T223	9		T151	6		T197	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T121	1		T208	12		T229	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T36	13		T135	1		T27	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T3	10		T35	15		T73	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T117	1		T138	1		T222	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T124	1		T74	10		T13	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T34	9		T127	8		T29	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T7	1		T124	1		T13	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T36	21		T119	5		T120	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1555	1			T5	1		T8	16		T9	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T12	1		T73	1		T126	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T37	13		T73	1		T161	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T3	2		T10	14		T125	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T3	1		T33	14		T120	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T12	1		T33	10		T126	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T5	1		T36	11		T123	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T6	1		T123	1		T118	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T74	10		T25	4		T136	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T2	14		T12	1		T33	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16945	1			T1	11		T3	106		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T143	4		T29	2		T201	5
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T127	10		T154	2		T226	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T117	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T151	7		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T121	7		T208	10		T14	21
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T36	7		T135	9		T27	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T3	5		T35	10		T136	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T117	10		T138	13		T198	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T13	1		T139	8		T174	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T34	9		T127	2		T203	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T13	2		T135	12		T23	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T36	12		T120	2		T28	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1061	1			T161	6		T177	23		T202	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T12	13		T73	10		T126	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T37	12		T73	13		T161	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T3	1		T35	10		T13	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T33	12		T120	7		T160	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T12	2		T33	8		T126	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T36	10		T221	5		T30	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T138	9		T145	4		T140	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T25	1		T136	7		T145	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T2	13		T12	13		T135	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T13	2		T27	7		T114	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T3	8		T35	11		T127	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T36	8		T135	10		T27	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T73	1		T123	1		T13	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T117	11		T199	3		T198	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T7	1		T124	2		T74	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T34	10		T127	3		T138	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1414	1			T5	1		T8	1		T9	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T36	13		T126	7		T170	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T26	5		T225	1		T198	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T3	3		T12	14		T125	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T37	13		T73	14		T161	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T10	1		T12	3		T35	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T3	1		T33	13		T36	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T33	9		T118	1		T128	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T5	1		T123	1		T25	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T6	1		T33	1		T123	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T74	1		T136	8		T118	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T2	14		T12	14		T34	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T125	1		T118	1		T26	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T127	11		T226	4		T149	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17163	1			T1	11		T3	106		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T159	1		T223	1		T235	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T3	7		T35	14		T208	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T36	12		T27	1		T222	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T13	3		T136	9		T170	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T199	12		T198	11		T174	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T74	9		T139	10		T225	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T34	8		T127	7		T203	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1229	1			T8	15		T9	12		T75	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T36	20		T170	11		T119	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T26	4		T225	3		T198	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T160	9		T217	3		T241	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T37	12		T114	8		T122	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T10	13		T13	1		T114	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T33	13		T36	10		T160	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T33	9		T118	11		T128	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T25	1		T221	5		T30	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T33	6		T27	2		T128	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T74	9		T136	2		T118	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T2	13		T170	14		T119	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T26	1		T274	10		T266	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T127	5		T226	3		T149	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T147	9		T131	13		T239	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T223	8		T235	11		T151	5

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T125	1		T118	1		T143	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T72	1		T170	1		T127	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T117	12		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T223	1		T151	8		T197	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T121	8		T208	11		T229	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T36	8		T135	10		T27	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T3	8		T35	11		T73	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T117	11		T138	14		T222	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T124	1		T74	1		T13	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T34	10		T127	3		T29	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T7	1		T124	1		T13	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T36	13		T119	1		T120	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1397	1			T5	1		T8	1		T9	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T12	14		T73	11		T126	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T37	13		T73	14		T161	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T3	3		T10	1		T125	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T3	1		T33	13		T120	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T12	3		T33	9		T126	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T5	1		T36	11		T123	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T6	1		T123	1		T118	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T74	1		T25	4		T136	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	311	1			T2	14		T12	14		T33	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17079	1			T1	11		T3	106		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T143	13		T26	1		T29	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T170	14		T127	5		T154	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T223	8		T151	5		T197	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T208	11		T229	11		T14	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T36	12		T27	1		T164	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T3	7		T35	14		T136	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T222	15		T198	11		T140	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T74	9		T13	3		T139	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T34	8		T127	7		T203	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T13	4		T212	2		T23	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T36	20		T119	4		T28	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1219	1			T8	15		T9	12		T75	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T170	11		T160	9		T238	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T37	12		T26	4		T114	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T10	13		T13	1		T114	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T33	13		T160	10		T30	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T33	9		T128	11		T219	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T36	10		T221	5		T30	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T118	11		T128	12		T145	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T74	9		T25	1		T136	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T2	13		T33	6		T27	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22357

1

T1

11

T2

14

T3

118

auto[1]

auto[0]

4236

1

T2

13

T3

7

T8

15