Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26593

1

T1

11

T2

27

T3

125

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22724

1

T1

11

T3

106

T4

20

auto[ADC_CTRL_FILTER_COND_OUT]

3869

1

T2

27

T3

19

T5

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20729

1

T1

11

T2

27

T3

121

auto[1]

5864

1

T3

4

T8

16

T9

13

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22300

1

T1

11

T2

14

T3

119

auto[1]

4293

1

T2

13

T3

6

T12

28

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	337	1			T36	21		T135	13		T127	10
values[0]	39	1			T225	13		T297	2		T299	9
values[1]	687	1			T12	14		T161	7		T136	29
values[2]	879	1			T3	4		T10	14		T34	18
values[3]	824	1			T34	1		T73	14		T74	10
values[4]	781	1			T36	20		T37	25		T74	10
values[5]	643	1			T5	1		T33	7		T118	1
values[6]	766	1			T7	1		T33	26		T125	1
values[7]	703	1			T3	15		T73	1		T170	12
values[8]	2895	1			T2	27		T8	16		T9	13
values[9]	960	1			T5	1		T6	1		T12	3
minimum	17079	1			T1	11		T3	106		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	844	1			T35	25		T161	7		T136	29
values[1]	893	1			T3	4		T10	14		T34	19
values[2]	710	1			T123	1		T26	9		T127	6
values[3]	760	1			T36	20		T37	25		T74	10
values[4]	638	1			T5	1		T33	7		T72	1
values[5]	785	1			T7	1		T33	26		T125	1
values[6]	2929	1			T3	15		T8	16		T9	13
values[7]	644	1			T2	27		T12	14		T124	1
values[8]	961	1			T5	1		T6	1		T12	3
values[9]	199	1			T135	13		T301	1		T195	12
minimum	17230	1			T1	11		T3	106		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22357

1

T1

11

T2

14

T3

118

auto[1]

4236

1

T2

13

T3

7

T8

15

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T161	1		T136	13		T170	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T35	15		T120	1		T218	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T10	14		T13	7		T126	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T3	3		T34	10		T73	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T123	1		T127	1		T128	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T26	7		T155	1		T200	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T37	13		T74	10		T117	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T36	13		T170	11		T29	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T5	1		T33	7		T135	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T72	1		T159	1		T199	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T7	1		T33	14		T125	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T13	4		T117	1		T143	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1560	1			T8	16		T9	13		T11	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T3	10		T114	13		T212	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T73	1		T30	1		T140	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T2	14		T12	1		T124	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T12	1		T35	1		T123	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T5	1		T6	1		T124	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T135	1		T293	6		T236	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T301	1		T195	12		T255	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16986	1			T1	11		T3	106		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T145	10		T247	1		T297	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T161	6		T136	16		T120	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T35	10		T120	7		T218	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T13	2		T126	6		T30	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T3	1		T34	9		T73	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T127	5		T203	11		T199	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T26	2		T200	12		T140	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T37	12		T117	10		T127	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T36	7		T29	2		T160	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T135	3		T28	3		T31	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T199	11		T198	14		T201	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T33	12		T114	4		T138	22
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T13	1		T117	11		T143	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1031	1			T177	23		T202	11		T126	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T3	5		T114	18		T30	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T73	10		T30	5		T140	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T2	13		T12	13		T13	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T12	2		T35	10		T25	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T33	8		T36	22		T127	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T135	12		T293	9		T236	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T255	13		T152	11		T309	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T12	13		T13	2		T27	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T145	8		T310	11		T311	5

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T135	1		T195	5		T290	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T36	11		T127	8		T195	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T225	13		T303	1		T302	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T297	2		T299	9		T311	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T12	1		T161	1		T136	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T120	1		T218	11		T145	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T10	14		T13	7		T126	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T3	3		T34	9		T35	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T123	1		T127	1		T30	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T34	1		T73	1		T74	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T37	13		T74	10		T117	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T36	13		T26	7		T170	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T5	1		T33	7		T118	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T159	1		T199	12		T300	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T7	1		T33	14		T125	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T72	1		T13	4		T117	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T73	1		T170	12		T29	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T3	10		T114	13		T212	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1524	1			T8	16		T9	13		T11	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T2	14		T12	1		T124	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T12	1		T35	1		T123	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T5	1		T6	1		T124	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16945	1			T1	11		T3	106		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T135	12		T236	16		T312	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T36	10		T127	2		T255	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T311	5		T313	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T12	13		T161	6		T136	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T120	7		T218	12		T145	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T13	2		T126	6		T154	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T3	1		T34	9		T35	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T127	5		T30	12		T203	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T73	13		T161	3		T119	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T37	12		T117	10		T221	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T36	7		T26	2		T29	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T127	10		T28	3		T139	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T199	11		T198	14		T147	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T33	12		T135	3		T114	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T13	1		T117	11		T143	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T30	8		T214	8		T132	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T3	5		T114	18		T138	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1039	1			T73	10		T177	23		T202	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T2	13		T12	13		T30	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T12	2		T35	10		T25	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T33	8		T36	12		T13	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T13	2		T27	7		T114	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T161	7		T136	18		T170	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T35	11		T120	8		T218	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T10	1		T13	5		T126	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T3	4		T34	11		T73	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T123	1		T127	6		T128	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T26	5		T155	1		T200	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T37	13		T74	1		T117	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T36	8		T170	1		T29	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T5	1		T33	1		T135	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T72	1		T159	1		T199	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T7	1		T33	13		T125	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T13	2		T117	12		T143	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1375	1			T8	1		T9	1		T11	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T3	8		T114	19		T212	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T73	11		T30	6		T140	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T2	14		T12	14		T124	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T12	3		T35	11		T123	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	335	1			T5	1		T6	1		T124	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T135	13		T293	10		T236	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T301	1		T195	1		T255	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17135	1			T1	11		T3	106		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T145	9		T247	1		T297	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T136	11		T170	14		T221	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T35	14		T218	10		T223	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T10	13		T13	4		T154	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T34	8		T74	9		T118	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T128	11		T203	14		T199	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T26	4		T140	5		T220	21
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T37	12		T74	9		T27	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T36	12		T170	10		T29	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T33	6		T118	11		T28	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T199	11		T225	3		T198	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T33	13		T114	8		T30	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T13	3		T143	13		T26	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1216	1			T8	15		T9	12		T75	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T3	7		T114	12		T212	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T140	6		T258	5		T304	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T2	13		T13	1		T198	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T25	1		T119	4		T128	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T33	9		T36	30		T127	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T293	5		T236	15		T83	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T195	11		T305	6		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T225	12		T270	5		T286	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T145	9		T310	11		T311	4

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T135	13		T195	1		T290	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T36	11		T127	3		T195	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T225	1		T303	1		T302	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T297	2		T299	1		T311	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T12	14		T161	7		T136	18
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T120	8		T218	13		T145	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T10	1		T13	5		T126	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	310	1			T3	4		T34	10		T35	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T123	1		T127	6		T30	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T34	1		T73	14		T74	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T37	13		T74	1		T117	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T36	8		T26	5		T170	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T5	1		T33	1		T118	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T159	1		T199	12		T300	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T7	1		T33	13		T125	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T72	1		T13	2		T117	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T73	1		T170	1		T29	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T3	8		T114	19		T212	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1371	1			T8	1		T9	1		T11	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T2	14		T12	14		T124	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T12	3		T35	11		T123	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T5	1		T6	1		T124	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17079	1			T1	11		T3	106		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T195	4		T236	15		T298	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T36	10		T127	7		T195	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T225	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T299	8		T311	4		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T136	11		T170	14		T221	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T218	10		T145	9		T224	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T10	13		T13	4		T154	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T34	8		T35	14		T118	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T128	11		T203	14		T174	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T74	9		T119	10		T220	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T37	12		T74	9		T27	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T36	12		T26	4		T170	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T33	6		T127	5		T28	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T199	11		T198	14		T147	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T33	13		T118	11		T114	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T13	3		T143	13		T26	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T170	11		T30	9		T237	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T3	7		T114	12		T212	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1192	1			T8	15		T9	12		T75	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T2	13		T145	10		T201	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T25	1		T119	4		T128	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T33	9		T36	20		T13	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22357

1

T1

11

T2

14

T3

118

auto[1]

auto[0]

4236

1

T2

13

T3

7

T8

15