Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26593

1

T1

11

T2

27

T3

125

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22839

1

T1

11

T2

27

T3

121

auto[ADC_CTRL_FILTER_COND_OUT]

3754

1

T3

4

T5

1

T7

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20388

1

T1

11

T3

110

T4

20

auto[1]

6205

1

T2

27

T3

15

T5

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22300

1

T1

11

T2

14

T3

119

auto[1]

4293

1

T2

13

T3

6

T12

28

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	215	1			T35	11		T25	5		T225	11
values[0]	67	1			T135	13		T29	1		T30	21
values[1]	716	1			T12	14		T33	7		T35	25
values[2]	547	1			T2	27		T5	1		T7	1
values[3]	1027	1			T124	1		T34	18		T161	4
values[4]	3013	1			T8	16		T9	13		T11	2
values[5]	590	1			T5	1		T37	25		T13	9
values[6]	787	1			T3	16		T12	3		T124	1
values[7]	707	1			T10	14		T143	18		T127	6
values[8]	720	1			T3	3		T33	44		T125	1
values[9]	1125	1			T6	1		T36	33		T73	14
minimum	17079	1			T1	11		T3	106		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	712	1			T2	27		T33	7		T35	25
values[1]	557	1			T5	1		T7	1		T12	14
values[2]	964	1			T124	1		T34	18		T161	4
values[3]	3011	1			T8	16		T9	13		T11	2
values[4]	686	1			T5	1		T37	25		T13	9
values[5]	714	1			T3	16		T12	3		T124	1
values[6]	713	1			T10	14		T73	11		T143	18
values[7]	723	1			T3	3		T33	44		T125	1
values[8]	1147	1			T6	1		T73	14		T74	20
values[9]	36	1			T35	11		T146	1		T245	1
minimum	17330	1			T1	11		T3	106		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22357

1

T1

11

T2

14

T3

118

auto[1]

4236

1

T2

13

T3

7

T8

15

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T2	14		T33	7		T123	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T35	15		T72	1		T161	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T13	4		T136	10		T137	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T5	1		T7	1		T12	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	312	1			T161	1		T26	7		T114	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T124	1		T34	9		T118	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1608	1			T8	16		T9	13		T11	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T125	1		T119	11		T203	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T5	1		T120	1		T30	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T37	13		T13	7		T135	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T3	10		T12	1		T124	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T3	1		T170	11		T114	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T10	14		T73	1		T143	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T126	1		T121	1		T122	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T33	10		T73	1		T123	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T3	2		T33	14		T125	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T6	1		T73	1		T74	20
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	343	1			T25	4		T126	1		T26	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T245	1		T286	3		T279	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T35	1		T146	1		T256	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16986	1			T1	11		T3	106		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T12	1		T221	1		T29	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T2	13		T135	15		T138	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T35	10		T161	6		T201	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T13	1		T136	9		T138	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T12	13		T117	10		T127	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T161	3		T26	2		T114	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T34	9		T200	9		T140	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1081	1			T177	23		T202	11		T94	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T119	10		T203	11		T139	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T120	2		T30	1		T139	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T37	12		T13	2		T135	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T3	5		T12	2		T36	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T114	4		T140	10		T23	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T73	10		T143	4		T127	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T126	6		T121	10		T208	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T33	8		T14	3		T145	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T3	1		T33	12		T36	19
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T73	13		T13	1		T127	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	314	1			T25	1		T126	4		T27	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T279	7		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T35	10		T256	2		T227	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T13	2		T27	7		T28	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T12	13		T221	1		T30	8

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T270	6		T230	1		T245	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T35	1		T25	4		T225	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T135	1		T314	1		T315	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T29	1		T30	13		T316	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T33	7		T135	1		T28	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T12	1		T35	15		T72	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T2	14		T123	1		T13	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T5	1		T7	1		T12	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	300	1			T161	1		T114	13		T137	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T124	1		T34	9		T117	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1653	1			T8	16		T9	13		T11	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T125	1		T119	11		T203	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T5	1		T120	1		T139	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T37	13		T13	7		T135	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T3	10		T12	1		T124	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T3	1		T118	8		T170	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T10	14		T143	14		T127	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T114	9		T121	1		T159	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T33	10		T73	2		T123	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T3	2		T33	14		T125	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T6	1		T73	1		T74	20
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T36	21		T136	3		T118	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16945	1			T1	11		T3	106		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T270	5		T317	15		T318	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T35	10		T25	1		T281	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T135	12		T314	11		T315	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T30	8		T316	9		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T135	3		T28	3		T121	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T12	13		T35	10		T161	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T2	13		T13	1		T136	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T12	13		T219	3		T280	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T161	3		T114	18		T130	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T34	9		T117	10		T127	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1090	1			T177	23		T202	11		T26	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T119	10		T203	11		T139	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T120	2		T139	8		T201	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T37	12		T13	2		T135	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T3	5		T12	2		T36	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T14	21		T218	12		T140	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T143	4		T127	5		T121	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T114	4		T121	10		T269	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T33	8		T73	10		T14	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T3	1		T33	12		T36	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T73	13		T13	1		T127	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T36	12		T136	7		T126	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T13	2		T27	7		T114	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T2	14		T33	1		T123	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T35	11		T72	1		T161	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T13	2		T136	10		T137	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T5	1		T7	1		T12	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T161	4		T26	5		T114	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T124	1		T34	10		T118	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1422	1			T8	1		T9	1		T11	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T125	1		T119	11		T203	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T5	1		T120	3		T30	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T37	13		T13	5		T135	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T3	8		T12	3		T124	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T3	1		T170	1		T114	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T10	1		T73	11		T143	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T126	7		T121	11		T122	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T33	9		T73	1		T123	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T3	3		T33	13		T125	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T6	1		T73	14		T74	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	383	1			T25	4		T126	5		T26	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T245	1		T286	1		T279	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T35	11		T146	1		T256	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17159	1			T1	11		T3	106		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T12	14		T221	2		T29	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T2	13		T33	6		T225	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T35	14		T119	4		T222	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T13	3		T136	9		T199	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T127	7		T225	12		T219	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T26	4		T114	12		T130	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T34	8		T118	11		T27	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1267	1			T8	15		T9	12		T75	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T119	10		T203	14		T139	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T30	2		T139	10		T198	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T37	12		T13	4		T118	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T3	7		T36	10		T212	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T170	10		T114	8		T229	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T10	13		T143	13		T128	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T122	2		T208	8		T290	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T33	9		T145	9		T235	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T33	13		T36	32		T136	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T74	18		T13	1		T170	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T25	1		T26	1		T27	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T286	2		T279	1		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T319	2		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T28	3		T274	10		T320	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T30	9		T262	19		T321	6

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T270	6		T230	1		T245	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T35	11		T25	4		T225	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T135	13		T314	12		T315	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T29	1		T30	12		T316	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T33	1		T135	4		T28	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T12	14		T35	11		T72	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T2	14		T123	1		T13	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T5	1		T7	1		T12	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T161	4		T114	19		T137	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T124	1		T34	10		T117	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1437	1			T8	1		T9	1		T11	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T125	1		T119	11		T203	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T5	1		T120	3		T139	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T37	13		T13	5		T135	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T3	8		T12	3		T124	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T3	1		T118	1		T170	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T10	1		T143	5		T127	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T114	5		T121	11		T159	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T33	9		T73	12		T123	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T3	3		T33	13		T125	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	285	1			T6	1		T73	14		T74	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	373	1			T36	13		T136	8		T118	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17079	1			T1	11		T3	106		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T270	5		T317	12		T272	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T25	1		T225	10		T163	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T30	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T33	6		T28	3		T225	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T35	14		T119	4		T222	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T2	13		T13	3		T136	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T225	12		T219	7		T280	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T114	12		T145	10		T31	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T34	8		T118	11		T27	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1306	1			T8	15		T9	12		T75	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T119	10		T203	14		T139	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T139	10		T201	6		T195	24
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T37	12		T13	4		T219	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T3	7		T36	10		T160	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T118	7		T170	10		T14	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T10	13		T143	13		T212	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T114	8		T229	11		T216	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T33	9		T145	9		T261	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T33	13		T36	12		T122	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T74	18		T13	1		T170	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T36	20		T136	2		T26	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22357

1

T1

11

T2

14

T3

118

auto[1]

auto[0]

4236

1

T2

13

T3

7

T8

15