Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26593

1

T1

11

T2

27

T3

125

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22924

1

T1

11

T2

27

T3

125

auto[ADC_CTRL_FILTER_COND_OUT]

3669

1

T5

1

T6

1

T10

14

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20723

1

T1

11

T3

110

T4

20

auto[1]

5870

1

T2

27

T3

15

T6

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22300

1

T1

11

T2

14

T3

119

auto[1]

4293

1

T2

13

T3

6

T12

28

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	335	1			T26	2		T120	10		T212	3
values[0]	24	1			T3	15		T295	9		-	-
values[1]	507	1			T74	10		T13	3		T136	29
values[2]	3118	1			T3	3		T5	1		T8	16
values[3]	615	1			T6	1		T125	1		T72	1
values[4]	1075	1			T5	1		T124	1		T34	1
values[5]	587	1			T3	1		T12	3		T170	15
values[6]	644	1			T7	1		T10	14		T33	7
values[7]	807	1			T2	27		T36	20		T73	1
values[8]	673	1			T12	28		T34	18		T37	25
values[9]	1129	1			T33	18		T125	1		T36	54
minimum	17079	1			T1	11		T3	106		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	602	1			T3	3		T124	1		T35	25
values[1]	3028	1			T5	1		T8	16		T9	13
values[2]	764	1			T6	1		T125	1		T72	1
values[3]	896	1			T5	1		T124	1		T34	1
values[4]	619	1			T3	1		T7	1		T10	14
values[5]	728	1			T36	20		T73	1		T161	4
values[6]	748	1			T2	27		T37	25		T118	1
values[7]	663	1			T12	28		T34	18		T36	54
values[8]	1190	1			T33	18		T125	1		T73	14
values[9]	105	1			T28	8		T225	4		T195	12
minimum	17250	1			T1	11		T3	121		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22357

1

T1

11

T2

14

T3

118

auto[1]

4236

1

T2

13

T3

7

T8

15

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T3	2		T124	1		T35	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T117	1		T136	3		T114	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1530	1			T5	1		T8	16		T9	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T33	14		T74	10		T123	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T72	1		T13	7		T117	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T6	1		T125	1		T135	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T34	1		T118	12		T170	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T5	1		T124	1		T121	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T3	1		T7	1		T12	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T10	14		T33	7		T140	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T36	13		T73	1		T161	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T27	4		T127	1		T160	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T2	14		T37	13		T118	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T114	13		T301	1		T14	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T12	1		T34	9		T13	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T12	1		T36	32		T123	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	296	1			T33	10		T125	1		T126	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	334	1			T73	1		T25	4		T120	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T230	1		T81	1		T227	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T28	5		T225	4		T195	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16990	1			T1	11		T3	116		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T26	7		T120	1		T146	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T3	1		T35	10		T13	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T117	11		T136	7		T114	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1030	1			T35	10		T73	10		T177	23
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T33	12		T161	6		T138	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T13	2		T117	10		T119	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T135	9		T198	9		T174	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T127	2		T160	7		T154	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T121	10		T139	8		T199	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T12	2		T135	3		T221	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T140	6		T233	13		T194	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T36	7		T161	3		T126	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T127	5		T160	11		T199	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T2	13		T37	12		T203	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T114	18		T14	21		T214	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T12	13		T34	9		T13	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T12	13		T36	22		T135	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T33	8		T126	6		T221	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	339	1			T73	13		T25	1		T120	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T227	4		T313	17		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T28	3		T257	13		T322	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T3	5		T13	2		T27	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T26	2		T120	7		T16	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T26	2		T121	1		T300	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T120	1		T212	3		T30	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T3	10		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T295	9		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T74	10		T13	2		T136	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T136	3		T26	7		T120	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1592	1			T3	2		T5	1		T8	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T33	14		T74	10		T161	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T72	1		T117	1		T119	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T6	1		T125	1		T123	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	308	1			T34	1		T13	7		T118	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T5	1		T124	1		T121	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T3	1		T12	1		T170	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T229	12		T140	6		T163	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T7	1		T135	1		T120	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T10	14		T33	7		T127	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T2	14		T36	13		T73	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T27	4		T114	13		T160	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T12	1		T34	9		T37	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T12	1		T123	2		T135	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	337	1			T33	10		T125	1		T13	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T36	32		T73	1		T25	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16945	1			T1	11		T3	106		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T121	11		T289	2		T231	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T120	9		T30	1		T219	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T3	5		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T13	1		T136	9		T29	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T136	7		T26	2		T120	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1058	1			T3	1		T35	20		T73	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T33	12		T161	6		T117	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T117	10		T119	10		T220	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T135	9		T208	12		T198	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T13	2		T160	7		T154	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T121	10		T139	8		T199	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T12	2		T127	2		T221	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T140	6		T233	13		T256	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T135	3		T120	2		T138	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T127	5		T199	11		T200	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T2	13		T36	7		T161	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T114	18		T160	11		T14	21
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T12	13		T34	9		T37	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T12	13		T135	12		T30	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T33	8		T13	1		T126	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T36	22		T73	13		T25	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T13	2		T27	7		T114	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T3	3		T124	1		T35	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T117	12		T136	8		T114	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1369	1			T5	1		T8	1		T9	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T33	13		T74	1		T123	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T72	1		T13	5		T117	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T6	1		T125	1		T135	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T34	1		T118	1		T170	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T5	1		T124	1		T121	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T3	1		T7	1		T12	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T10	1		T33	1		T140	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T36	8		T73	1		T161	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T27	2		T127	6		T160	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T2	14		T37	13		T118	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T114	19		T301	1		T14	26
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T12	14		T34	10		T13	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T12	14		T36	24		T123	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T33	9		T125	1		T126	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	400	1			T73	14		T25	4		T120	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T230	1		T81	1		T227	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T28	5		T225	1		T195	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17127	1			T1	11		T3	114		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T26	5		T120	8		T146	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T35	14		T74	9		T13	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T136	2		T114	8		T128	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1191	1			T8	15		T9	12		T75	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T33	13		T74	9		T122	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T13	4		T119	14		T140	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T198	11		T174	11		T214	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T118	11		T170	14		T127	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T229	11		T139	10		T199	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T221	5		T139	9		T225	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T10	13		T33	6		T140	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T36	12		T128	12		T195	24
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T27	2		T160	10		T199	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T2	13		T37	12		T170	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T114	12		T14	11		T204	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T34	8		T13	3		T118	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T36	30		T198	8		T242	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T33	9		T26	1		T170	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T25	1		T212	2		T30	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T240	8		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T28	3		T225	3		T195	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T3	7		T29	1		T295	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T26	4		T16	1		T175	8

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T26	1		T121	12		T300	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T120	10		T212	1		T30	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T3	8		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T295	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T74	1		T13	2		T136	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T136	8		T26	5		T120	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1402	1			T3	3		T5	1		T8	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T33	13		T74	1		T161	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T72	1		T117	11		T119	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T6	1		T125	1		T123	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	303	1			T34	1		T13	5		T118	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T5	1		T124	1		T121	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T3	1		T12	3		T170	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T229	1		T140	7		T163	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T7	1		T135	4		T120	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T10	1		T33	1		T127	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T2	14		T36	8		T73	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T27	2		T114	19		T160	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T12	14		T34	10		T37	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T12	14		T123	2		T135	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	298	1			T33	9		T125	1		T13	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	336	1			T36	24		T73	14		T25	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17079	1			T1	11		T3	106		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T26	1		T246	9		T231	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T212	2		T30	2		T219	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T3	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T295	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T74	9		T13	1		T136	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T136	2		T26	4		T128	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1248	1			T8	15		T9	12		T35	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T33	13		T74	9		T114	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T119	14		T237	10		T220	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T208	8		T198	11		T201	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T13	4		T118	11		T160	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T139	10		T199	12		T238	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T170	14		T127	7		T221	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T229	11		T140	5		T163	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T128	12		T131	13		T236	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T10	13		T33	6		T199	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T2	13		T36	12		T170	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T27	2		T114	12		T160	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T34	8		T37	12		T127	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T198	8		T239	13		T242	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T33	9		T13	3		T118	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T36	30		T25	1		T28	3

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22357

1

T1

11

T2

14

T3

118

auto[1]

auto[0]

4236

1

T2

13

T3

7

T8

15