Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26593

1

T1

11

T2

27

T3

125

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22824

1

T1

11

T3

124

T4

20

auto[ADC_CTRL_FILTER_COND_OUT]

3769

1

T2

27

T3

1

T6

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20543

1

T1

11

T2

27

T3

107

auto[1]

6050

1

T3

18

T6

1

T8

16

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22300

1

T1

11

T2

14

T3

119

auto[1]

4293

1

T2

13

T3

6

T12

28

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	219	1			T5	1		T33	7		T13	5
values[0]	41	1			T219	21		T195	12		T234	3
values[1]	753	1			T6	1		T12	14		T135	10
values[2]	690	1			T12	3		T124	1		T73	25
values[3]	771	1			T3	15		T10	14		T123	1
values[4]	689	1			T125	1		T35	25		T36	21
values[5]	2792	1			T2	27		T7	1		T8	16
values[6]	780	1			T3	4		T34	19		T221	11
values[7]	856	1			T33	18		T35	11		T36	33
values[8]	817	1			T5	1		T36	20		T37	25
values[9]	1106	1			T12	14		T124	1		T33	26
minimum	17079	1			T1	11		T3	106		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	685	1			T6	1		T12	3		T124	1
values[1]	727	1			T73	25		T126	7		T27	4
values[2]	708	1			T3	15		T10	14		T123	1
values[3]	2882	1			T8	16		T9	13		T11	2
values[4]	690	1			T2	27		T3	3		T7	1
values[5]	783	1			T3	1		T34	19		T161	4
values[6]	796	1			T33	18		T35	11		T36	53
values[7]	835	1			T5	1		T73	1		T74	10
values[8]	1033	1			T12	14		T124	1		T33	33
values[9]	119	1			T5	1		T125	1		T135	13
minimum	17335	1			T1	11		T3	106		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22357

1

T1

11

T2

14

T3

118

auto[1]

4236

1

T2

13

T3

7

T8

15

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T12	1		T124	1		T26	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T6	1		T135	1		T118	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T27	4		T119	11		T122	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T73	2		T126	1		T127	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T3	10		T10	14		T136	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T123	1		T136	3		T137	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1584	1			T8	16		T9	13		T11	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T35	15		T13	7		T161	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T3	2		T7	1		T123	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T2	14		T72	1		T30	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T34	9		T161	1		T138	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T3	1		T34	1		T27	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T35	1		T36	21		T37	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T33	10		T36	13		T117	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T5	1		T135	1		T26	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T73	1		T74	10		T127	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T12	1		T124	1		T33	21
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	323	1			T74	10		T123	1		T13	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T5	1		T135	1		T119	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T125	1		T138	1		T159	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16980	1			T1	11		T3	106		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T12	1		T30	13		T300	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T12	2		T26	2		T121	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T135	9		T120	7		T218	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T119	10		T199	2		T200	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T73	23		T126	6		T127	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T3	5		T136	9		T126	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T136	7		T201	5		T220	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	976	1			T36	10		T177	23		T202	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T35	10		T13	2		T161	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T3	1		T25	1		T120	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T2	13		T30	12		T203	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T34	9		T161	3		T138	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T27	1		T138	9		T145	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T35	10		T36	12		T37	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T33	8		T36	7		T117	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T135	3		T198	14		T216	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T127	10		T114	18		T30	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T12	13		T33	12		T13	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T13	1		T117	11		T143	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T135	12		T293	9		T205	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T138	9		T194	1		T224	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T13	2		T27	7		T114	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T12	13		T30	8		T31	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T5	1		T33	7		T13	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T117	1		T154	5		T159	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T195	12		T234	2		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T219	10		T211	1		T323	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T26	7		T27	4		T121	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T6	1		T12	1		T135	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T12	1		T124	1		T170	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T73	2		T127	1		T28	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T3	10		T10	14		T136	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T123	1		T126	1		T140	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T125	1		T36	11		T114	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T35	15		T161	1		T136	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1467	1			T7	1		T8	16		T9	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T2	14		T72	1		T13	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T3	2		T34	9		T221	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T3	1		T34	1		T138	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T35	1		T36	21		T161	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T33	10		T117	1		T27	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T5	1		T37	13		T135	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T36	13		T73	1		T74	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	294	1			T12	1		T124	1		T33	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	340	1			T125	1		T74	10		T123	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16945	1			T1	11		T3	106		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T13	1		T135	12		T214	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T117	11		T154	2		T238	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T234	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T219	11		T211	1		T323	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T26	2		T121	10		T259	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T12	13		T135	9		T120	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T12	2		T119	10		T121	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T73	23		T127	5		T28	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T3	5		T136	9		T126	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T126	6		T140	6		T201	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T36	10		T114	4		T30	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T35	10		T161	6		T136	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1003	1			T25	1		T177	23		T202	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T2	13		T13	2		T203	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T3	1		T34	9		T221	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T138	9		T30	12		T145	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T35	10		T36	12		T161	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T33	8		T117	10		T27	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T37	12		T135	3		T216	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T36	7		T127	10		T201	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T12	13		T33	12		T127	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	316	1			T13	1		T143	4		T114	18
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T13	2		T27	7		T114	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T12	3		T124	1		T26	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T6	1		T135	10		T118	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T27	2		T119	11		T122	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T73	25		T126	7		T127	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T3	8		T10	1		T136	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T123	1		T136	8		T137	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1312	1			T8	1		T9	1		T11	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T35	11		T13	5		T161	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T3	3		T7	1		T123	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T2	14		T72	1		T30	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T34	10		T161	4		T138	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T3	1		T34	1		T27	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T35	11		T36	13		T37	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T33	9		T36	8		T117	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T5	1		T135	4		T26	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T73	1		T74	1		T127	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T12	14		T124	1		T33	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	357	1			T74	1		T123	1		T13	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T5	1		T135	13		T119	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T125	1		T138	10		T159	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17109	1			T1	11		T3	106		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T12	14		T30	12		T300	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T26	4		T170	10		T128	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T118	11		T218	10		T174	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T27	2		T119	10		T122	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T28	3		T140	5		T219	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T3	7		T10	13		T136	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T136	2		T201	12		T220	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1248	1			T8	15		T9	12		T36	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T35	14		T13	4		T118	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T25	1		T221	5		T199	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T2	13		T222	15		T203	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T34	8		T139	10		T198	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T27	1		T145	9		T219	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T36	20		T37	12		T160	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T33	9		T36	12		T208	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T26	1		T170	14		T198	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T74	9		T127	5		T114	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T33	19		T13	3		T127	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T74	9		T13	1		T143	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T119	4		T225	10		T223	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T194	7		T224	8		T324	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T195	11		T196	2		T319	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T30	9		T31	2		T219	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T5	1		T33	1		T13	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T117	12		T154	3		T159	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T195	1		T234	3		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T219	12		T211	2		T323	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T26	5		T27	2		T121	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T6	1		T12	14		T135	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T12	3		T124	1		T170	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T73	25		T127	6		T28	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T3	8		T10	1		T136	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T123	1		T126	7		T140	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T125	1		T36	11		T114	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T35	11		T161	7		T136	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1337	1			T7	1		T8	1		T9	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T2	14		T72	1		T13	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T3	3		T34	10		T221	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T3	1		T34	1		T138	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T35	11		T36	13		T161	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T33	9		T117	11		T27	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T5	1		T37	13		T135	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T36	8		T73	1		T74	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T12	14		T124	1		T33	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	384	1			T125	1		T74	1		T123	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17079	1			T1	11		T3	106		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T33	6		T13	3		T225	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T154	4		T238	11		T225	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T195	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T219	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T26	4		T27	2		T128	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T118	11		T30	9		T218	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T170	10		T119	10		T122	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T28	3		T219	7		T15	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T3	7		T10	13		T136	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T140	5		T201	12		T220	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T36	10		T114	8		T212	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T35	14		T136	2		T118	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1133	1			T8	15		T9	12		T75	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T2	13		T13	4		T170	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T34	8		T221	5		T198	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T145	9		T23	7		T219	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T36	20		T160	9		T139	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T33	9		T27	1		T208	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T37	12		T26	1		T170	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T36	12		T74	9		T127	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T33	13		T119	4		T127	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T74	9		T13	1		T143	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22357

1

T1

11

T2

14

T3

118

auto[1]

auto[0]

4236

1

T2

13

T3

7

T8

15