Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T3	11		T124	1		T35	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T117	12		T136	8		T26	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1354	1			T5	1		T8	1		T9	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T33	13		T74	1		T123	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T72	1		T73	11		T117	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T6	1		T125	1		T135	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T34	1		T13	5		T118	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T5	1		T124	1		T121	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T3	1		T7	1		T12	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T10	1		T33	1		T229	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T36	8		T73	1		T126	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T27	2		T127	6		T137	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T2	14		T12	14		T37	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T123	1		T114	19		T160	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T34	10		T13	2		T118	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T12	14		T36	24		T123	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T33	9		T125	1		T126	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	339	1			T25	4		T120	10		T212	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T26	1		T230	1		T231	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T73	14		T28	5		T225	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17079	1			T1	11		T3	106		T4	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T3	7		T35	14		T74	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T136	2		T26	4		T114	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1188	1			T8	15		T9	12		T75	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T33	13		T74	9		T122	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T119	14		T140	6		T237	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T198	11		T219	9		T174	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T13	4		T118	11		T170	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T139	10		T199	12		T238	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T221	5		T139	9		T225	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T10	13		T33	6		T229	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T36	12		T128	12		T131	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T27	2		T199	11		T201	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T2	13		T37	12		T170	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T114	12		T160	10		T14	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T34	8		T13	3		T118	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T36	30		T198	8		T239	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T33	9		T27	1		T170	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T25	1		T212	2		T30	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T26	1		T231	2		T240	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T28	3		T225	3		T195	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T227	5		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T228	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T13	2		T136	10		T29	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T26	5		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T3	8		T74	1		T30	26
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T136	8		T120	8		T114	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1379	1			T3	3		T5	1		T8	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T33	13		T74	1		T161	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T72	1		T13	5		T117	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T6	1		T125	1		T123	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	299	1			T3	1		T118	1		T160	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T5	1		T124	1		T121	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T12	3		T34	1		T135	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T137	1		T229	1		T140	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T7	1		T120	3		T159	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T10	1		T33	1		T127	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T2	14		T12	14		T36	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T27	2		T114	19		T160	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T34	10		T37	13		T27	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T12	14		T36	13		T123	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	354	1			T33	9		T125	1		T13	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	485	1			T36	11		T73	14		T25	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17079	1			T1	11		T3	106		T4	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T13	1		T136	9		T29	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T26	4		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T3	7		T74	9		T241	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T136	2		T114	8		T128	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1227	1			T8	15		T9	12		T35	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T33	13		T74	9		T122	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T13	4		T119	14		T237	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T208	8		T198	11		T214	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T118	11		T160	9		T154	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T139	10		T199	12		T238	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T170	14		T127	7		T221	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T229	11		T140	5		T163	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T128	12		T131	13		T236	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T10	13		T33	6		T199	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T2	13		T36	12		T170	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T27	2		T114	12		T160	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T34	8		T37	12		T27	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T36	20		T242	18		T243	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	293	1			T33	9		T13	3		T118	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	341	1			T36	10		T25	1		T28	3

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22357

1

T1

11

T2

14

T3

118

auto[1]

auto[0]

4236

1

T2

13

T3

7

T8

15