Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26593

1

T1

11

T2

27

T3

125

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22986

1

T1

11

T3

107

T4

20

auto[ADC_CTRL_FILTER_COND_OUT]

3607

1

T2

27

T3

18

T5

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19857

1

T1

11

T2

27

T3

120

auto[1]

6736

1

T3

5

T5

1

T7

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22300

1

T1

11

T2

14

T3

119

auto[1]

4293

1

T2

13

T3

6

T12

28

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	441	1			T3	5		T38	7		T39	3
values[0]	64	1			T117	12		T164	16		T244	16
values[1]	567	1			T3	1		T124	1		T27	4
values[2]	3211	1			T2	27		T8	16		T9	13
values[3]	743	1			T135	10		T137	1		T30	1
values[4]	744	1			T12	14		T34	1		T73	14
values[5]	656	1			T33	26		T72	1		T123	1
values[6]	502	1			T10	14		T124	1		T37	25
values[7]	923	1			T3	18		T5	1		T6	1
values[8]	797	1			T12	14		T125	1		T34	18
values[9]	1282	1			T5	1		T33	18		T36	20
minimum	16663	1			T1	11		T3	101		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	833	1			T3	1		T124	1		T117	12
values[1]	3208	1			T2	27		T8	16		T9	13
values[2]	712	1			T170	11		T127	16		T29	6
values[3]	616	1			T12	14		T34	1		T73	14
values[4]	820	1			T33	26		T72	1		T123	1
values[5]	600	1			T7	1		T10	14		T124	1
values[6]	925	1			T3	18		T5	1		T6	1
values[7]	667	1			T12	14		T36	33		T73	11
values[8]	910	1			T5	1		T33	18		T36	20
values[9]	223	1			T73	1		T120	8		T212	3
minimum	17079	1			T1	11		T3	106		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22357

1

T1

11

T2

14

T3

118

auto[1]

4236

1

T2

13

T3

7

T8

15

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T3	1		T117	1		T29	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T124	1		T135	1		T27	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1605	1			T8	16		T9	13		T11	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T2	14		T125	1		T161	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T154	5		T159	1		T199	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T170	11		T127	6		T29	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T34	1		T74	10		T118	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T12	1		T73	1		T170	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T33	14		T25	4		T126	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T72	1		T123	1		T203	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T7	1		T10	14		T124	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T26	7		T119	11		T28	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T5	1		T6	1		T125	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T3	12		T33	7		T35	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T73	1		T74	10		T143	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T12	1		T36	21		T13	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T33	10		T36	13		T126	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T5	1		T123	1		T160	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T73	1		T120	1		T212	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T132	1		T245	1		T246	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16945	1			T1	11		T3	106		T4	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T117	11		T23	1		T174	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T135	3		T114	4		T23	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1073	1			T12	2		T35	10		T161	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T2	13		T161	6		T136	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T154	2		T199	2		T200	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T127	10		T29	2		T247	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T127	7		T130	1		T248	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T12	13		T73	13		T114	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T33	12		T25	1		T126	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T203	11		T145	4		T219	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T37	12		T13	1		T117	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T26	2		T119	10		T28	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T34	9		T36	10		T221	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T3	6		T35	10		T13	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T73	10		T143	4		T120	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T12	13		T36	12		T13	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T33	8		T36	7		T126	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T160	11		T121	10		T138	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T120	7		T30	1		T194	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T132	11		T196	9		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T13	2		T27	7		T114	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	417	1			T3	5		T38	7		T39	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T249	1		T184	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T117	1		T164	8		T250	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T244	13		T192	2		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T3	1		T29	2		T137	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T124	1		T27	4		T114	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1644	1			T8	16		T9	13		T11	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T2	14		T125	1		T161	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T135	1		T30	1		T154	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T137	1		T208	12		T139	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T34	1		T74	10		T118	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T12	1		T73	1		T170	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T33	14		T25	4		T121	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T72	1		T123	1		T170	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T10	14		T124	1		T37	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T26	7		T225	11		T145	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T5	1		T6	1		T7	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	318	1			T3	12		T33	7		T35	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T125	1		T34	9		T73	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T12	1		T36	21		T123	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	434	1			T33	10		T36	13		T73	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	302	1			T5	1		T123	1		T13	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16529	1			T1	11		T3	101		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T251	12		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T249	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T117	11		T164	8		T252	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T244	3		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T23	1		T174	11		T201	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T114	4		T23	8		T31	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1111	1			T12	2		T35	10		T161	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T2	13		T161	6		T135	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T135	9		T154	2		T199	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T208	10		T139	8		T238	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T127	7		T130	1		T200	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T12	13		T73	13		T127	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T33	12		T25	1		T121	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T219	3		T131	13		T216	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T37	12		T13	1		T136	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T26	2		T145	4		T174	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T36	10		T117	10		T138	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T3	6		T35	10		T13	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T34	9		T73	10		T143	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T12	13		T36	12		T30	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T33	8		T36	7		T126	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T13	1		T160	11		T121	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T13	2		T27	7		T114	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T3	1		T117	12		T29	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T124	1		T135	4		T27	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1417	1			T8	1		T9	1		T11	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	316	1			T2	14		T125	1		T161	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T154	3		T159	1		T199	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T170	1		T127	11		T29	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T34	1		T74	1		T118	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T12	14		T73	14		T170	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T33	13		T25	4		T126	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T72	1		T123	1		T203	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T7	1		T10	1		T124	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T26	5		T119	11		T28	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T5	1		T6	1		T125	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T3	11		T33	1		T35	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T73	11		T74	1		T143	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T12	14		T36	13		T13	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T33	9		T36	8		T126	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	314	1			T5	1		T123	1		T160	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T73	1		T120	8		T212	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T132	12		T245	1		T246	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17079	1			T1	11		T3	106		T4	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T174	11		T237	10		T201	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T27	2		T114	8		T23	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1261	1			T8	15		T9	12		T35	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T2	13		T136	2		T118	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T154	4		T199	12		T237	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T170	10		T127	5		T29	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T74	9		T118	11		T127	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T170	14		T114	12		T141	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T33	13		T25	1		T122	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T203	14		T145	10		T219	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T10	13		T37	12		T13	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T26	4		T119	10		T28	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T34	8		T36	10		T170	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T3	7		T33	6		T13	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T74	9		T143	13		T26	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T36	20		T13	3		T198	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T33	9		T36	12		T119	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T160	10		T14	11		T218	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T212	2		T30	2		T128	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T246	12		T196	2		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	429	1			T3	5		T38	7		T39	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T249	11		T184	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T117	12		T164	9		T250	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T244	4		T192	2		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T3	1		T29	2		T137	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T124	1		T27	2		T114	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1456	1			T8	1		T9	1		T11	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T2	14		T125	1		T161	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T135	10		T30	1		T154	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T137	1		T208	11		T139	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T34	1		T74	1		T118	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T12	14		T73	14		T170	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T33	13		T25	4		T121	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T72	1		T123	1		T170	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T10	1		T124	1		T37	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T26	5		T225	1		T145	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T5	1		T6	1		T7	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T3	11		T33	1		T35	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T125	1		T34	10		T73	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T12	14		T36	13		T123	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	339	1			T33	9		T36	8		T73	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	360	1			T5	1		T123	1		T13	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16663	1			T1	11		T3	101		T4	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T164	7		T252	8		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T244	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T174	11		T237	10		T201	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T27	2		T114	8		T229	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1299	1			T8	15		T9	12		T35	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T2	13		T136	2		T118	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T154	4		T222	15		T199	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T208	11		T139	10		T238	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T74	9		T118	11		T127	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T170	10		T127	5		T114	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T33	13		T25	1		T122	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T170	14		T219	7		T131	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T10	13		T37	12		T13	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T26	4		T225	10		T145	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T36	10		T31	1		T219	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T3	7		T33	6		T13	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T34	8		T74	9		T143	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T36	20		T198	8		T195	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	356	1			T33	9		T36	12		T119	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T13	3		T160	10		T14	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22357

1

T1

11

T2

14

T3

118

auto[1]

auto[0]

4236

1

T2

13

T3

7

T8

15