Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26593

1

T1

11

T2

27

T3

125

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20797

1

T1

11

T2

27

T3

110

auto[ADC_CTRL_FILTER_COND_OUT]

5796

1

T3

15

T5

1

T7

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20237

1

T1

11

T3

122

T4

20

auto[1]

6356

1

T2

27

T3

3

T5

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22300

1

T1

11

T2

14

T3

119

auto[1]

4293

1

T2

13

T3

6

T12

28

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	328	1			T3	1		T125	1		T127	6
values[0]	1	1			T253	1		-	-		-	-
values[1]	615	1			T6	1		T124	1		T34	1
values[2]	654	1			T3	15		T5	1		T33	18
values[3]	890	1			T5	1		T36	33		T73	11
values[4]	754	1			T3	3		T12	3		T33	33
values[5]	671	1			T125	1		T123	1		T118	1
values[6]	741	1			T2	27		T124	1		T73	1
values[7]	738	1			T10	14		T12	14		T35	36
values[8]	775	1			T123	1		T25	5		T117	12
values[9]	3347	1			T7	1		T8	16		T9	13
minimum	17079	1			T1	11		T3	106		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	644	1			T3	15		T5	1		T34	1
values[1]	2959	1			T8	16		T9	13		T11	2
values[2]	846	1			T5	1		T36	33		T73	11
values[3]	747	1			T3	3		T12	3		T33	33
values[4]	756	1			T124	1		T125	1		T123	1
values[5]	688	1			T2	27		T10	14		T35	36
values[6]	685	1			T12	14		T72	1		T117	12
values[7]	763	1			T73	14		T74	10		T123	1
values[8]	1120	1			T3	1		T7	1		T12	14
values[9]	186	1			T127	6		T114	13		T30	1
minimum	17199	1			T1	11		T3	106		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22357

1

T1

11

T2

14

T3

118

auto[1]

4236

1

T2

13

T3

7

T8

15

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T5	1		T36	13		T117	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T3	10		T34	1		T123	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T33	10		T29	2		T160	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1581	1			T8	16		T9	13		T11	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T74	10		T13	2		T136	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T5	1		T36	21		T73	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T3	2		T12	1		T33	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T33	14		T27	4		T221	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T124	1		T125	1		T123	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T198	12		T23	1		T254	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T2	14		T35	1		T73	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T10	14		T35	15		T13	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T72	1		T117	1		T118	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T12	1		T170	11		T30	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T73	1		T74	10		T123	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T28	5		T138	1		T129	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	303	1			T3	1		T161	1		T26	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	328	1			T7	1		T12	1		T125	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T30	1		T195	12		T230	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T127	1		T114	9		T141	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16972	1			T1	11		T3	106		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T124	1		T170	12		T255	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T36	7		T117	10		T126	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T3	5		T13	1		T135	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T33	8		T160	11		T214	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1016	1			T36	10		T37	12		T177	23
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T13	1		T136	9		T26	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T36	12		T73	10		T208	22
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T3	1		T12	2		T135	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T33	12		T221	1		T235	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T114	18		T121	11		T30	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T198	9		T23	1		T201	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T2	13		T35	10		T161	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T35	10		T13	2		T135	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T117	11		T120	11		T138	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T12	13		T30	5		T130	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T73	13		T25	1		T136	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T28	3		T138	9		T199	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T161	6		T127	12		T120	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T12	13		T34	9		T160	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T256	13		T150	13		T257	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T127	5		T114	4		T171	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T13	2		T27	7		T114	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T255	13		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T3	1		T137	1		T30	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T125	1		T127	1		T141	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T253	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T6	1		T117	1		T126	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T124	1		T34	1		T13	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T5	1		T33	10		T36	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T3	10		T36	11		T37	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	298	1			T74	10		T13	2		T136	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T5	1		T36	21		T73	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T3	2		T12	1		T33	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T33	14		T27	4		T221	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T125	1		T123	1		T118	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T23	1		T254	1		T201	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T2	14		T124	1		T73	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T135	1		T154	5		T159	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T35	1		T72	1		T120	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T10	14		T12	1		T35	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T123	1		T25	4		T117	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T170	11		T28	5		T138	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T73	1		T74	10		T161	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1732	1			T7	1		T8	16		T9	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16945	1			T1	11		T3	106		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T30	12		T258	6		T15	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T127	5		T259	4		T260	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T117	10		T126	4		T121	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T13	1		T135	3		T30	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T33	8		T36	7		T160	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T3	5		T36	10		T37	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T13	1		T136	9		T26	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T36	12		T73	10		T221	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T3	1		T12	2		T135	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T33	12		T221	1		T208	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T114	18		T30	12		T199	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T23	1		T201	5		T261	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T2	13		T161	3		T121	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T135	12		T154	2		T198	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T35	10		T120	11		T138	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T12	13		T35	10		T13	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T25	1		T117	11		T136	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T28	3		T138	9		T199	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T73	13		T161	6		T127	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1161	1			T12	13		T34	9		T177	23
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T13	2		T27	7		T114	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T5	1		T36	8		T117	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T3	8		T34	1		T123	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T33	9		T29	2		T160	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1345	1			T8	1		T9	1		T11	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T74	1		T13	2		T136	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T5	1		T36	13		T73	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T3	3		T12	3		T33	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T33	13		T27	2		T221	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T124	1		T125	1		T123	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T198	10		T23	2		T254	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T2	14		T35	11		T73	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T10	1		T35	11		T13	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T72	1		T117	12		T118	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T12	14		T170	1		T30	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T73	14		T74	1		T123	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T28	5		T138	10		T129	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T3	1		T161	7		T26	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	331	1			T7	1		T12	14		T125	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T30	1		T195	1		T230	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T127	6		T114	5		T141	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17119	1			T1	11		T3	106		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T124	1		T170	1		T255	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T36	12		T170	14		T229	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T3	7		T13	3		T30	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T33	9		T160	10		T141	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1252	1			T8	15		T9	12		T36	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T74	9		T13	1		T136	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T36	20		T208	19		T262	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T33	6		T119	4		T128	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T33	13		T27	2		T235	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T114	12		T199	12		T14	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T198	11		T201	18		T261	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T2	13		T139	9		T225	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T10	13		T35	14		T13	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T118	11		T203	14		T237	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T170	10		T219	9		T131	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T74	9		T25	1		T136	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T28	3		T199	11		T238	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T26	1		T127	12		T139	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T34	8		T160	9		T23	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T195	11		T257	15		T211	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T114	8		T141	13		T263	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T212	2		T264	11		T265	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T170	11		T167	9		T242	18

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T3	1		T137	1		T30	13
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T125	1		T127	6		T141	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T253	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T6	1		T117	11		T126	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T124	1		T34	1		T13	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T5	1		T33	9		T36	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T3	8		T36	11		T37	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T74	1		T13	2		T136	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T5	1		T36	13		T73	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T3	3		T12	3		T33	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T33	13		T27	2		T221	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T125	1		T123	1		T118	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T23	2		T254	1		T201	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T2	14		T124	1		T73	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T135	13		T154	3		T159	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T35	11		T72	1		T120	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T10	1		T12	14		T35	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T123	1		T25	4		T117	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T170	1		T28	5		T138	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T73	14		T74	1		T161	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1513	1			T7	1		T8	1		T9	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17079	1			T1	11		T3	106		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T258	5		T195	11		T194	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T141	13		T259	4		T266	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T170	14		T212	2		T229	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T13	3		T170	11		T30	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T33	9		T36	12		T160	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T3	7		T36	10		T37	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T74	9		T13	1		T136	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T36	20		T221	5		T208	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T33	6		T29	1		T128	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T33	13		T27	2		T208	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T119	4		T114	12		T199	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T201	6		T261	14		T175	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T2	13		T139	9		T225	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T154	4		T198	11		T219	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T203	14		T198	14		T217	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T10	13		T35	14		T13	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T25	1		T136	2		T118	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T170	10		T28	3		T199	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T74	9		T26	1		T127	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1380	1			T8	15		T9	12		T34	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22357

1

T1

11

T2

14

T3

118

auto[1]

auto[0]

4236

1

T2

13

T3

7

T8

15