Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26593

1

T1

11

T2

27

T3

125

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22830

1

T1

11

T3

107

T4

20

auto[ADC_CTRL_FILTER_COND_OUT]

3763

1

T2

27

T3

18

T5

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20151

1

T1

11

T2

27

T3

107

auto[1]

6442

1

T3

18

T6

1

T7

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22300

1

T1

11

T2

14

T3

119

auto[1]

4293

1

T2

13

T3

6

T12

28

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	19	1			T249	2		T209	16		T267	1
values[0]	51	1			T268	1		T261	17		T20	4
values[1]	610	1			T2	27		T5	1		T6	1
values[2]	805	1			T7	1		T12	14		T125	1
values[3]	594	1			T33	18		T125	1		T34	1
values[4]	701	1			T34	18		T35	36		T123	1
values[5]	854	1			T3	15		T5	1		T124	1
values[6]	841	1			T3	4		T12	3		T124	1
values[7]	782	1			T36	41		T73	11		T13	5
values[8]	763	1			T10	14		T117	11		T135	13
values[9]	3494	1			T8	16		T9	13		T11	2
minimum	17079	1			T1	11		T3	106		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	955	1			T2	27		T5	1		T6	1
values[1]	528	1			T7	1		T33	26		T125	2
values[2]	713	1			T33	18		T34	19		T35	11
values[3]	708	1			T3	15		T35	25		T123	1
values[4]	836	1			T5	1		T124	1		T33	7
values[5]	983	1			T3	4		T12	3		T124	1
values[6]	3042	1			T8	16		T9	13		T11	2
values[7]	694	1			T10	14		T72	1		T135	13
values[8]	749	1			T36	33		T123	1		T117	11
values[9]	293	1			T13	3		T114	31		T121	11
minimum	17092	1			T1	11		T3	106		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22357

1

T1

11

T2

14

T3

118

auto[1]

4236

1

T2

13

T3

7

T8

15

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T12	2		T74	10		T135	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T2	14		T5	1		T6	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T125	2		T161	1		T27	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T7	1		T33	14		T123	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T33	10		T37	13		T161	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T34	10		T35	1		T73	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T26	7		T203	15		T14	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T3	10		T35	15		T123	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T5	1		T33	7		T135	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T124	1		T127	8		T160	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T3	1		T12	1		T114	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	348	1			T3	2		T124	1		T136	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1601	1			T8	16		T9	13		T11	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T36	24		T73	1		T26	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T212	3		T154	5		T254	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T10	14		T72	1		T135	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T36	21		T123	1		T127	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T117	1		T221	1		T225	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T114	13		T121	1		T269	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T13	2		T174	10		T195	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16946	1			T1	11		T3	106		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T128	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T12	26		T135	9		T120	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T2	13		T219	11		T214	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T161	6		T238	13		T198	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T33	12		T136	9		T23	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T33	8		T37	12		T161	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T34	9		T35	10		T73	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T26	2		T203	11		T14	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T3	5		T35	10		T25	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T135	3		T143	4		T28	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T127	2		T160	11		T218	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T12	2		T114	4		T221	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T3	1		T136	7		T126	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1048	1			T73	10		T13	1		T177	23
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T36	17		T199	2		T200	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T154	2		T201	5		T204	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T135	12		T30	5		T208	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T36	12		T127	10		T160	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T117	10		T221	1		T270	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T114	18		T121	10		T269	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T13	1		T174	11		T256	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T13	2		T27	7		T114	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T249	1		T209	16		T267	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T261	15		T78	1		T271	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T268	1		T20	3		T272	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T12	1		T74	10		T135	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T2	14		T5	1		T6	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T12	1		T125	1		T27	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T7	1		T123	1		T136	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T33	10		T125	1		T37	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T34	1		T73	1		T13	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T161	1		T26	7		T199	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T34	9		T35	16		T123	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T5	1		T135	1		T143	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T3	10		T124	1		T127	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T3	1		T12	1		T33	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T3	2		T124	1		T73	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T73	1		T13	4		T118	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T36	24		T126	1		T170	27
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T212	3		T198	15		T254	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T10	14		T117	1		T135	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1676	1			T8	16		T9	13		T11	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	387	1			T72	1		T13	2		T221	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16945	1			T1	11		T3	106		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T249	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T261	2		T271	8		T273	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T20	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T12	13		T135	9		T120	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T2	13		T33	12		T214	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T12	13		T120	7		T208	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T136	9		T23	1		T219	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T33	8		T37	12		T161	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T73	13		T13	2		T27	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T161	3		T26	2		T199	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T34	9		T35	20		T25	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T135	3		T143	4		T28	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T3	5		T127	2		T160	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T12	2		T114	4		T29	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T3	1		T136	7		T130	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T73	10		T13	1		T120	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T36	17		T126	6		T200	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T198	14		T248	5		T274	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T117	10		T135	12		T30	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1161	1			T36	12		T177	23		T202	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T13	1		T221	1		T208	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T13	2		T27	7		T114	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	326	1			T12	28		T74	1		T135	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T2	14		T5	1		T6	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T125	2		T161	7		T27	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T7	1		T33	13		T123	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T33	9		T37	13		T161	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T34	11		T35	11		T73	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T26	5		T203	12		T14	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T3	8		T35	11		T123	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T5	1		T33	1		T135	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T124	1		T127	3		T160	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T3	1		T12	3		T114	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	304	1			T3	3		T124	1		T136	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1384	1			T8	1		T9	1		T11	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T36	19		T73	1		T26	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T212	1		T154	3		T254	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T10	1		T72	1		T135	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T36	13		T123	1		T127	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T117	11		T221	2		T225	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T114	19		T121	11		T269	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T13	2		T174	12		T195	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17080	1			T1	11		T3	106		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T128	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T74	9		T208	8		T140	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T2	13		T74	9		T170	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T27	2		T238	11		T198	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T33	13		T136	9		T195	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T33	9		T37	12		T199	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T34	8		T13	4		T27	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T26	4		T203	14		T145	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T3	7		T35	14		T25	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T33	6		T143	13		T28	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T127	7		T160	10		T218	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T114	8		T221	5		T29	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T136	2		T118	7		T170	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1265	1			T8	15		T9	12		T75	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T36	22		T26	1		T170	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T212	2		T154	4		T201	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T10	13		T208	11		T216	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T36	20		T127	5		T160	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T225	12		T270	5		T223	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T114	12		T141	3		T275	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T13	1		T174	9		T195	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T128	11		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T249	2		T209	1		T267	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T261	3		T78	1		T271	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T268	1		T20	3		T272	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T12	14		T74	1		T135	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T2	14		T5	1		T6	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T12	14		T125	1		T27	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T7	1		T123	1		T136	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T33	9		T125	1		T37	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T34	1		T73	14		T13	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T161	4		T26	5		T199	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T34	10		T35	22		T123	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T5	1		T135	4		T143	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T3	8		T124	1		T127	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T3	1		T12	3		T33	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T3	3		T124	1		T73	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T73	11		T13	2		T118	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T36	19		T126	7		T170	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T212	1		T198	15		T254	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T10	1		T117	11		T135	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1519	1			T8	1		T9	1		T11	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	345	1			T72	1		T13	2		T221	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17079	1			T1	11		T3	106		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T209	15		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T261	14		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T20	1		T272	7		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T74	9		T140	5		T237	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T2	13		T33	13		T74	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T27	2		T208	8		T238	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T136	9		T170	10		T219	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T33	9		T37	12		T225	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T13	4		T27	1		T119	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T26	4		T199	11		T145	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T34	8		T35	14		T25	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T143	13		T28	3		T30	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T3	7		T127	7		T160	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T33	6		T114	8		T29	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T136	2		T118	7		T26	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T13	3		T118	11		T221	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T36	22		T170	25		T145	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T212	2		T198	14		T237	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T10	13		T199	12		T219	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1318	1			T8	15		T9	12		T36	20
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T13	1		T208	11		T225	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22357

1

T1

11

T2

14

T3

118

auto[1]

auto[0]

4236

1

T2

13

T3

7

T8

15