Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26593

1

T1

11

T2

27

T3

125

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22894

1

T1

11

T3

107

T4

20

auto[ADC_CTRL_FILTER_COND_OUT]

3699

1

T2

27

T3

18

T12

28

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20089

1

T1

11

T2

27

T3

119

auto[1]

6504

1

T3

6

T5

2

T6

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22300

1

T1

11

T2

14

T3

119

auto[1]

4293

1

T2

13

T3

6

T12

28

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	748	1			T3	5		T38	7		T39	3
values[0]	17	1			T252	17		-	-		-	-
values[1]	623	1			T3	1		T124	1		T117	12
values[2]	3164	1			T2	27		T8	16		T9	13
values[3]	760	1			T135	10		T137	1		T154	7
values[4]	708	1			T12	14		T34	1		T73	14
values[5]	692	1			T33	26		T72	1		T123	1
values[6]	576	1			T10	14		T124	1		T37	25
values[7]	903	1			T3	18		T5	1		T6	1
values[8]	787	1			T12	14		T125	1		T34	18
values[9]	952	1			T5	1		T33	18		T123	1
minimum	16663	1			T1	11		T3	101		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	636	1			T117	12		T135	4		T27	4
values[1]	3185	1			T2	27		T8	16		T9	13
values[2]	766	1			T170	11		T127	16		T29	5
values[3]	602	1			T12	14		T34	1		T73	14
values[4]	725	1			T33	26		T72	1		T123	1
values[5]	616	1			T6	1		T7	1		T10	14
values[6]	969	1			T3	18		T5	1		T33	7
values[7]	673	1			T12	14		T36	33		T73	11
values[8]	1020	1			T5	1		T33	18		T123	1
values[9]	140	1			T36	20		T73	1		T120	8
minimum	17261	1			T1	11		T3	107		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22357

1

T1

11

T2

14

T3

118

auto[1]

4236

1

T2

13

T3

7

T8

15

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T117	1		T27	4		T29	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T135	1		T114	9		T23	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1625	1			T8	16		T9	13		T11	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T2	14		T125	1		T35	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T137	1		T154	5		T159	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T170	11		T127	6		T29	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T34	1		T74	10		T118	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T12	1		T73	1		T170	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T33	14		T72	1		T123	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T200	1		T145	11		T131	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T6	1		T7	1		T10	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T124	1		T117	1		T119	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T5	1		T36	11		T123	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	319	1			T3	12		T33	7		T125	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T36	21		T74	10		T143	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T12	1		T73	1		T13	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T5	1		T123	1		T126	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	324	1			T33	10		T160	21		T121	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T36	13		T73	1		T212	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T120	1		T30	4		T246	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16989	1			T1	11		T3	107		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T124	1		T31	4		T280	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T117	11		T174	11		T201	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T135	3		T114	4		T23	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1073	1			T12	2		T177	23		T135	21
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T2	13		T35	10		T161	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T154	2		T199	2		T238	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T127	10		T29	2		T236	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T127	2		T121	11		T130	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T12	13		T73	13		T127	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T33	12		T25	1		T126	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T200	12		T145	4		T131	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T37	12		T13	1		T136	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T117	10		T119	10		T28	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T36	10		T221	5		T138	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T3	6		T34	9		T35	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T36	12		T143	4		T120	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T12	13		T73	10		T13	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T126	6		T138	9		T269	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T33	8		T160	18		T121	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T36	7		T194	1		T196	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T120	7		T30	1		T288	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T13	2		T27	7		T114	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T31	3		T289	9		T244	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	527	1			T3	5		T38	7		T39	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T138	1		T132	1		T290	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T252	9		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T3	1		T117	1		T27	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T124	1		T23	10		T31	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1612	1			T8	16		T9	13		T11	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T2	14		T125	1		T35	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T135	1		T137	1		T154	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T139	11		T173	1		T198	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T34	1		T74	10		T118	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T12	1		T73	1		T170	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T33	14		T72	1		T123	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T170	15		T200	1		T131	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T10	14		T37	13		T13	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T124	1		T119	11		T225	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T5	1		T6	1		T7	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	325	1			T3	12		T33	7		T35	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T36	21		T74	10		T123	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T12	1		T125	1		T34	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T5	1		T123	1		T126	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	309	1			T33	10		T13	4		T120	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16529	1			T1	11		T3	101		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T36	7		T138	9		T269	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T138	13		T132	11		T288	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T252	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T117	11		T174	11		T201	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T23	9		T31	3		T226	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1048	1			T12	2		T177	23		T135	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T2	13		T35	10		T161	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T135	9		T154	2		T208	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T139	8		T198	9		T150	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T127	2		T121	11		T130	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T12	13		T73	13		T127	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T33	12		T25	1		T121	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T200	12		T131	13		T216	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T37	12		T13	1		T136	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T119	10		T145	4		T258	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T36	10		T138	9		T219	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T3	6		T35	10		T13	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T36	12		T143	4		T120	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T12	13		T34	9		T73	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T126	6		T30	8		T200	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T33	8		T13	1		T120	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T13	2		T27	7		T114	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T117	12		T27	2		T29	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T135	4		T114	5		T23	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1421	1			T8	1		T9	1		T11	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T2	14		T125	1		T35	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T137	1		T154	3		T159	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T170	1		T127	11		T29	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T34	1		T74	1		T118	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T12	14		T73	14		T170	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T33	13		T72	1		T123	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T200	13		T145	5		T131	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T6	1		T7	1		T10	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T124	1		T117	11		T119	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T5	1		T36	11		T123	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T3	11		T33	1		T125	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T36	13		T74	1		T143	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T12	14		T73	11		T13	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T5	1		T123	1		T126	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	357	1			T33	9		T160	20		T121	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T36	8		T73	1		T212	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T120	8		T30	3		T246	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17125	1			T1	11		T3	107		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T124	1		T31	5		T280	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T27	2		T174	11		T237	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T114	8		T23	7		T220	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1277	1			T8	15		T9	12		T75	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T2	13		T35	14		T136	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T154	4		T199	12		T238	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T170	10		T127	5		T29	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T74	9		T118	11		T127	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T170	14		T114	12		T141	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T33	13		T25	1		T122	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T145	10		T131	13		T216	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T10	13		T37	12		T13	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T119	10		T28	3		T225	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T36	10		T170	11		T221	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T3	7		T33	6		T34	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T36	20		T74	9		T143	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T13	3		T147	9		T241	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T119	4		T237	10		T163	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T33	9		T160	19		T199	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T36	12		T212	2		T128	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T30	2		T246	12		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T220	9		T151	3		T224	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T31	2		T141	13		T244	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	522	1			T3	5		T38	7		T39	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T138	14		T132	12		T290	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T252	9		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T3	1		T117	12		T27	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T124	1		T23	12		T31	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1399	1			T8	1		T9	1		T11	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T2	14		T125	1		T35	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T135	10		T137	1		T154	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T139	9		T173	1		T198	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T34	1		T74	1		T118	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T12	14		T73	14		T170	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T33	13		T72	1		T123	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T170	1		T200	13		T131	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T10	1		T37	13		T13	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T124	1		T119	11		T225	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T5	1		T6	1		T7	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	306	1			T3	11		T33	1		T35	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T36	13		T74	1		T123	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T12	14		T125	1		T34	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T5	1		T123	1		T126	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	325	1			T33	9		T13	2		T120	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16663	1			T1	11		T3	101		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T36	12		T119	4		T128	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T290	7		T197	15		T272	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T252	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T27	2		T174	11		T237	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T23	7		T31	2		T141	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1261	1			T8	15		T9	12		T75	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T2	13		T35	14		T136	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T154	4		T208	11		T199	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T139	10		T198	11		T176	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T74	9		T118	11		T127	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T170	10		T127	5		T114	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T33	13		T25	1		T122	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T170	14		T131	13		T216	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T10	13		T37	12		T13	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T119	10		T225	10		T145	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T36	10		T225	3		T31	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T3	7		T33	6		T13	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T36	20		T74	9		T143	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T34	8		T195	4		T147	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T212	2		T30	9		T204	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T33	9		T13	3		T160	19

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22357

1

T1

11

T2

14

T3

118

auto[1]

auto[0]

4236

1

T2

13

T3

7

T8

15