Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26593

1

T1

11

T2

27

T3

125

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22719

1

T1

11

T3

107

T4

20

auto[ADC_CTRL_FILTER_COND_OUT]

3874

1

T2

27

T3

18

T5

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20257

1

T1

11

T3

107

T4

20

auto[1]

6336

1

T2

27

T3

18

T6

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22300

1

T1

11

T2

14

T3

119

auto[1]

4293

1

T2

13

T3

6

T12

28

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	346	1			T127	16		T269	8		T254	1
values[0]	49	1			T280	17		T178	3		T227	1
values[1]	669	1			T2	27		T5	1		T6	1
values[2]	689	1			T7	1		T12	14		T33	26
values[3]	655	1			T33	18		T125	1		T34	1
values[4]	692	1			T34	18		T35	36		T123	1
values[5]	900	1			T3	15		T5	1		T124	1
values[6]	806	1			T3	4		T12	3		T124	1
values[7]	750	1			T36	41		T13	5		T126	7
values[8]	853	1			T10	14		T73	11		T117	11
values[9]	3105	1			T8	16		T9	13		T11	2
minimum	17079	1			T1	11		T3	106		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	705	1			T2	27		T6	1		T12	28
values[1]	636	1			T7	1		T33	26		T125	2
values[2]	743	1			T33	18		T34	19		T35	11
values[3]	640	1			T3	15		T35	25		T123	1
values[4]	804	1			T5	1		T124	1		T33	7
values[5]	980	1			T3	4		T12	3		T124	1
values[6]	3065	1			T8	16		T9	13		T11	2
values[7]	706	1			T10	14		T72	1		T117	11
values[8]	862	1			T36	33		T123	1		T127	16
values[9]	160	1			T13	3		T121	11		T269	8
minimum	17292	1			T1	11		T3	106		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22357

1

T1

11

T2

14

T3

118

auto[1]

4236

1

T2

13

T3

7

T8

15

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T12	2		T135	1		T120	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T2	14		T6	1		T74	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T125	2		T37	13		T161	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T7	1		T33	14		T123	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T33	10		T161	1		T117	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T34	10		T35	1		T73	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T25	4		T26	7		T203	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T3	10		T35	15		T123	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T5	1		T33	7		T135	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T124	1		T127	8		T160	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T3	1		T12	1		T170	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	333	1			T3	2		T124	1		T136	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1641	1			T8	16		T9	13		T11	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T36	24		T73	1		T26	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T212	3		T154	5		T199	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T10	14		T72	1		T117	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T36	21		T123	1		T114	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T127	6		T221	1		T225	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T121	1		T269	1		T174	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T13	2		T163	17		T256	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17016	1			T1	11		T3	106		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T5	1		T138	1		T128	25
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T12	26		T135	9		T120	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T2	13		T219	11		T214	24
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T37	12		T161	6		T238	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T33	12		T136	9		T23	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T33	8		T161	3		T117	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T34	9		T35	10		T73	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T25	1		T26	2		T203	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T3	5		T35	10		T121	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T135	3		T143	4		T28	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T127	2		T160	11		T218	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T12	2		T114	4		T221	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T3	1		T136	7		T126	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1058	1			T73	10		T13	1		T177	23
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T36	17		T200	2		T145	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T154	2		T199	2		T201	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T117	10		T135	12		T30	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T36	12		T114	18		T160	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T127	10		T221	1		T174	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T121	10		T269	7		T252	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T13	1		T256	2		T291	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T13	2		T27	7		T120	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T138	9		T132	6		T292	10

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T269	1		T254	1		T171	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T127	6		T174	10		T262	20
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T280	11		T178	1		T227	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T12	1		T74	10		T135	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T2	14		T5	1		T6	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T12	1		T125	1		T27	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T7	1		T33	14		T123	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T33	10		T125	1		T37	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T34	1		T73	1		T13	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T25	4		T161	1		T26	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T34	9		T35	16		T123	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T5	1		T135	1		T143	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T3	10		T124	1		T127	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T3	1		T12	1		T33	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T3	2		T124	1		T73	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T13	4		T170	12		T120	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T36	24		T126	1		T26	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T73	1		T118	12		T212	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T10	14		T117	1		T135	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1590	1			T8	16		T9	13		T11	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T72	1		T13	2		T221	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16945	1			T1	11		T3	106		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T269	7		T171	2		T293	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T127	10		T174	11		T256	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T280	6		T178	2		T294	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T12	13		T135	9		T120	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T2	13		T138	9		T214	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T12	13		T120	7		T238	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T33	12		T136	9		T23	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T33	8		T37	12		T161	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T73	13		T13	2		T27	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T25	1		T161	3		T26	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T34	9		T35	20		T119	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T135	3		T143	4		T28	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T3	5		T127	2		T160	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T12	2		T114	4		T29	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T3	1		T136	7		T130	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T13	1		T120	9		T221	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T36	17		T126	6		T200	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T73	10		T154	2		T199	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T117	10		T135	12		T30	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1063	1			T36	12		T177	23		T202	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T13	1		T221	1		T208	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T13	2		T27	7		T114	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T12	28		T135	10		T120	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T2	14		T6	1		T74	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T125	2		T37	13		T161	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T7	1		T33	13		T123	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T33	9		T161	4		T117	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T34	11		T35	11		T73	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T25	4		T26	5		T203	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T3	8		T35	11		T123	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T5	1		T33	1		T135	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T124	1		T127	3		T160	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T3	1		T12	3		T170	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T3	3		T124	1		T136	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1400	1			T8	1		T9	1		T11	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T36	19		T73	1		T26	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T212	1		T154	3		T199	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T10	1		T72	1		T117	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T36	13		T123	1		T114	19
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T127	11		T221	2		T225	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T121	11		T269	8		T174	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T13	2		T163	1		T256	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17146	1			T1	11		T3	106		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T5	1		T138	10		T128	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T208	8		T140	5		T261	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T2	13		T74	9		T170	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T37	12		T27	2		T238	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T33	13		T136	9		T195	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T33	9		T199	11		T225	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T34	8		T13	4		T27	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T25	1		T26	4		T203	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T3	7		T35	14		T122	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T33	6		T143	13		T28	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T127	7		T160	10		T218	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T170	11		T114	8		T221	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T136	2		T118	7		T222	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1299	1			T8	15		T9	12		T75	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T36	22		T26	1		T170	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T212	2		T154	4		T199	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T10	13		T208	11		T216	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T36	20		T114	12		T160	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T127	5		T225	12		T174	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T252	6		T213	5		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T13	1		T163	16		T295	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T74	9		T237	10		T280	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T128	23		T290	7		T296	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T269	8		T254	1		T171	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T127	11		T174	12		T262	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T280	7		T178	3		T227	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T12	14		T74	1		T135	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T2	14		T5	1		T6	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T12	14		T125	1		T27	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T7	1		T33	13		T123	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T33	9		T125	1		T37	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T34	1		T73	14		T13	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T25	4		T161	4		T26	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T34	10		T35	22		T123	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T5	1		T135	4		T143	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T3	8		T124	1		T127	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T3	1		T12	3		T33	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T3	3		T124	1		T73	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T13	2		T170	1		T120	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T36	19		T126	7		T26	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T73	11		T118	1		T212	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T10	1		T117	11		T135	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1404	1			T8	1		T9	1		T11	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T72	1		T13	2		T221	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17079	1			T1	11		T3	106		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T293	5		T163	4		T209	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T127	5		T174	9		T262	19
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T280	10		T294	13		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T74	9		T208	8		T140	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T2	13		T74	9		T128	23
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T27	2		T238	11		T198	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T33	13		T136	9		T170	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T33	9		T37	12		T199	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T13	4		T27	1		T119	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T25	1		T26	4		T145	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T34	8		T35	14		T119	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T143	13		T28	3		T30	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T3	7		T127	7		T160	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T33	6		T114	8		T29	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T136	2		T118	7		T229	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T13	3		T170	11		T221	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T36	22		T26	1		T170	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T118	11		T212	2		T154	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T10	13		T219	7		T216	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1249	1			T8	15		T9	12		T36	20
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T13	1		T208	11		T225	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22357

1

T1

11

T2

14

T3

118

auto[1]

auto[0]

4236

1

T2

13

T3

7

T8

15