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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.75 99.07 96.67 100.00 100.00 98.83 98.33 91.37


Total test records in report: 920
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T785 /workspace/coverage/default/36.adc_ctrl_poweron_counter.3250467274 Jul 19 07:17:11 PM PDT 24 Jul 19 07:17:14 PM PDT 24 3265095151 ps
T786 /workspace/coverage/default/8.adc_ctrl_alert_test.435565085 Jul 19 07:09:04 PM PDT 24 Jul 19 07:09:15 PM PDT 24 332386815 ps
T787 /workspace/coverage/default/1.adc_ctrl_lowpower_counter.2959147633 Jul 19 07:05:52 PM PDT 24 Jul 19 07:06:09 PM PDT 24 39180663049 ps
T788 /workspace/coverage/default/37.adc_ctrl_alert_test.1171319936 Jul 19 07:17:24 PM PDT 24 Jul 19 07:17:28 PM PDT 24 444033399 ps
T789 /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.1636063208 Jul 19 07:12:29 PM PDT 24 Jul 19 07:16:36 PM PDT 24 195138294270 ps
T790 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.1028327935 Jul 19 05:56:21 PM PDT 24 Jul 19 05:56:23 PM PDT 24 362597511 ps
T791 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.262057017 Jul 19 05:56:21 PM PDT 24 Jul 19 05:56:24 PM PDT 24 448081629 ps
T49 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.3409420438 Jul 19 05:55:41 PM PDT 24 Jul 19 05:56:04 PM PDT 24 8016612929 ps
T792 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.1039979566 Jul 19 05:56:21 PM PDT 24 Jul 19 05:56:23 PM PDT 24 570231511 ps
T793 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.2225513370 Jul 19 05:56:06 PM PDT 24 Jul 19 05:56:09 PM PDT 24 440393474 ps
T794 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.1404275204 Jul 19 05:56:24 PM PDT 24 Jul 19 05:56:27 PM PDT 24 334575897 ps
T50 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.3930303815 Jul 19 05:56:15 PM PDT 24 Jul 19 05:56:23 PM PDT 24 8087795723 ps
T111 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.626759672 Jul 19 05:56:05 PM PDT 24 Jul 19 05:56:08 PM PDT 24 517046344 ps
T51 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.2520525209 Jul 19 05:55:56 PM PDT 24 Jul 19 05:56:09 PM PDT 24 8171624278 ps
T65 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.39644422 Jul 19 05:55:36 PM PDT 24 Jul 19 05:55:45 PM PDT 24 8250154726 ps
T57 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.2214451000 Jul 19 05:56:06 PM PDT 24 Jul 19 05:56:10 PM PDT 24 392618345 ps
T46 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.399075644 Jul 19 05:56:19 PM PDT 24 Jul 19 05:56:29 PM PDT 24 3938085939 ps
T795 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.2663452513 Jul 19 05:56:24 PM PDT 24 Jul 19 05:56:27 PM PDT 24 474181347 ps
T58 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.633840327 Jul 19 05:55:58 PM PDT 24 Jul 19 05:56:00 PM PDT 24 843684915 ps
T98 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.1412161259 Jul 19 05:55:52 PM PDT 24 Jul 19 05:55:54 PM PDT 24 845057475 ps
T59 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.3338571369 Jul 19 05:55:50 PM PDT 24 Jul 19 05:55:55 PM PDT 24 626811387 ps
T47 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.521101216 Jul 19 05:55:43 PM PDT 24 Jul 19 05:55:51 PM PDT 24 2038663867 ps
T79 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.2354669856 Jul 19 05:55:57 PM PDT 24 Jul 19 05:55:59 PM PDT 24 436369227 ps
T796 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.963142686 Jul 19 05:56:23 PM PDT 24 Jul 19 05:56:26 PM PDT 24 319649006 ps
T112 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.1767830825 Jul 19 05:55:51 PM PDT 24 Jul 19 05:55:53 PM PDT 24 379157942 ps
T797 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.3027027578 Jul 19 05:55:43 PM PDT 24 Jul 19 05:55:45 PM PDT 24 418825234 ps
T48 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.1567963082 Jul 19 05:55:52 PM PDT 24 Jul 19 05:56:10 PM PDT 24 26229036309 ps
T99 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.2211829422 Jul 19 05:55:42 PM PDT 24 Jul 19 05:55:45 PM PDT 24 566112449 ps
T100 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.2995279326 Jul 19 05:56:06 PM PDT 24 Jul 19 05:56:09 PM PDT 24 354220670 ps
T64 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.292514255 Jul 19 05:56:13 PM PDT 24 Jul 19 05:56:15 PM PDT 24 440885191 ps
T80 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.3945671750 Jul 19 05:55:42 PM PDT 24 Jul 19 05:55:56 PM PDT 24 9190078387 ps
T108 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.3721726132 Jul 19 05:56:05 PM PDT 24 Jul 19 05:56:15 PM PDT 24 1814743044 ps
T113 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.2267906029 Jul 19 05:55:43 PM PDT 24 Jul 19 05:56:05 PM PDT 24 52190625738 ps
T101 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.2547123769 Jul 19 05:55:51 PM PDT 24 Jul 19 05:55:53 PM PDT 24 402938461 ps
T63 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.3402128832 Jul 19 05:56:19 PM PDT 24 Jul 19 05:56:23 PM PDT 24 2456475262 ps
T90 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.2954588070 Jul 19 05:55:43 PM PDT 24 Jul 19 05:55:46 PM PDT 24 491911839 ps
T66 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.1117668508 Jul 19 05:56:06 PM PDT 24 Jul 19 05:56:10 PM PDT 24 5032092137 ps
T102 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.314749894 Jul 19 05:55:42 PM PDT 24 Jul 19 05:55:45 PM PDT 24 582333383 ps
T798 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.3437215755 Jul 19 05:55:41 PM PDT 24 Jul 19 05:55:43 PM PDT 24 324351906 ps
T799 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.4144916455 Jul 19 05:55:41 PM PDT 24 Jul 19 05:55:43 PM PDT 24 883315744 ps
T800 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.1154888192 Jul 19 05:56:23 PM PDT 24 Jul 19 05:56:27 PM PDT 24 508938669 ps
T801 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.1763525525 Jul 19 05:55:48 PM PDT 24 Jul 19 05:55:49 PM PDT 24 349915389 ps
T802 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.1389819474 Jul 19 05:56:25 PM PDT 24 Jul 19 05:56:28 PM PDT 24 499507435 ps
T803 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.1498653811 Jul 19 05:56:16 PM PDT 24 Jul 19 05:56:18 PM PDT 24 364398135 ps
T804 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.3952603200 Jul 19 05:55:41 PM PDT 24 Jul 19 05:56:00 PM PDT 24 27085024331 ps
T805 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.2384016342 Jul 19 05:55:34 PM PDT 24 Jul 19 05:55:36 PM PDT 24 400949695 ps
T806 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.1320654354 Jul 19 05:56:22 PM PDT 24 Jul 19 05:56:25 PM PDT 24 281388495 ps
T103 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.3199871281 Jul 19 05:55:35 PM PDT 24 Jul 19 05:55:37 PM PDT 24 374990553 ps
T104 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.748485939 Jul 19 05:55:43 PM PDT 24 Jul 19 05:55:48 PM PDT 24 792956228 ps
T807 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.862917303 Jul 19 05:56:23 PM PDT 24 Jul 19 05:56:28 PM PDT 24 384472352 ps
T109 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.564077169 Jul 19 05:55:43 PM PDT 24 Jul 19 05:55:56 PM PDT 24 4482773501 ps
T808 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.620042109 Jul 19 05:56:24 PM PDT 24 Jul 19 05:56:28 PM PDT 24 450879620 ps
T105 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.1136253208 Jul 19 05:56:14 PM PDT 24 Jul 19 05:56:17 PM PDT 24 353576892 ps
T809 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.2538344218 Jul 19 05:56:01 PM PDT 24 Jul 19 05:56:07 PM PDT 24 8718212335 ps
T810 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.1819625965 Jul 19 05:55:56 PM PDT 24 Jul 19 05:55:59 PM PDT 24 371054434 ps
T811 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.2760955648 Jul 19 05:55:42 PM PDT 24 Jul 19 05:55:45 PM PDT 24 469727075 ps
T812 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.1093625153 Jul 19 05:56:15 PM PDT 24 Jul 19 05:56:22 PM PDT 24 3797520681 ps
T813 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.1435838912 Jul 19 05:55:42 PM PDT 24 Jul 19 05:56:12 PM PDT 24 52924812400 ps
T814 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.2646830114 Jul 19 05:55:59 PM PDT 24 Jul 19 05:56:02 PM PDT 24 1616203163 ps
T815 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.2156766077 Jul 19 05:56:24 PM PDT 24 Jul 19 05:56:28 PM PDT 24 586980241 ps
T816 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.4082350265 Jul 19 05:55:50 PM PDT 24 Jul 19 05:56:03 PM PDT 24 4505748597 ps
T817 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.2734876782 Jul 19 05:56:22 PM PDT 24 Jul 19 05:56:25 PM PDT 24 423960941 ps
T818 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.378425578 Jul 19 05:55:41 PM PDT 24 Jul 19 05:55:42 PM PDT 24 546110477 ps
T819 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.2127963337 Jul 19 05:55:52 PM PDT 24 Jul 19 05:55:54 PM PDT 24 521477397 ps
T110 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.512962225 Jul 19 05:56:14 PM PDT 24 Jul 19 05:56:18 PM PDT 24 1870055996 ps
T325 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.2045344104 Jul 19 05:56:25 PM PDT 24 Jul 19 05:56:35 PM PDT 24 8044605519 ps
T820 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.92329599 Jul 19 05:55:56 PM PDT 24 Jul 19 05:55:59 PM PDT 24 290872556 ps
T821 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.37226369 Jul 19 05:56:07 PM PDT 24 Jul 19 05:56:09 PM PDT 24 441923182 ps
T822 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.2511487484 Jul 19 05:56:15 PM PDT 24 Jul 19 05:56:18 PM PDT 24 644098824 ps
T823 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.3213489323 Jul 19 05:56:23 PM PDT 24 Jul 19 05:56:27 PM PDT 24 363765781 ps
T824 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.1993960689 Jul 19 05:55:50 PM PDT 24 Jul 19 05:55:52 PM PDT 24 608219438 ps
T825 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.645016809 Jul 19 05:56:22 PM PDT 24 Jul 19 05:56:25 PM PDT 24 525394623 ps
T826 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.765777919 Jul 19 05:55:41 PM PDT 24 Jul 19 05:55:45 PM PDT 24 408702911 ps
T827 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.2459502972 Jul 19 05:55:42 PM PDT 24 Jul 19 05:55:46 PM PDT 24 652231996 ps
T828 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.1871869394 Jul 19 05:56:26 PM PDT 24 Jul 19 05:56:29 PM PDT 24 416444956 ps
T106 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.549327092 Jul 19 05:56:14 PM PDT 24 Jul 19 05:56:17 PM PDT 24 302329223 ps
T829 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.2311180430 Jul 19 05:55:53 PM PDT 24 Jul 19 05:55:56 PM PDT 24 536819852 ps
T830 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.1242495094 Jul 19 05:56:13 PM PDT 24 Jul 19 05:56:15 PM PDT 24 422773185 ps
T831 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.2990693663 Jul 19 05:56:14 PM PDT 24 Jul 19 05:56:17 PM PDT 24 408325735 ps
T832 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.4098342716 Jul 19 05:55:51 PM PDT 24 Jul 19 05:55:53 PM PDT 24 380308439 ps
T833 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.2838195697 Jul 19 05:56:04 PM PDT 24 Jul 19 05:56:07 PM PDT 24 397620721 ps
T107 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.395981800 Jul 19 05:55:42 PM PDT 24 Jul 19 05:55:45 PM PDT 24 578066075 ps
T834 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.3220295292 Jul 19 05:56:23 PM PDT 24 Jul 19 05:56:27 PM PDT 24 424710445 ps
T835 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.1505847272 Jul 19 05:56:25 PM PDT 24 Jul 19 05:56:28 PM PDT 24 325508120 ps
T836 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.1568342420 Jul 19 05:56:04 PM PDT 24 Jul 19 05:56:12 PM PDT 24 4309689183 ps
T837 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.2603667578 Jul 19 05:56:15 PM PDT 24 Jul 19 05:56:18 PM PDT 24 562446739 ps
T838 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.3211892206 Jul 19 05:56:24 PM PDT 24 Jul 19 05:56:28 PM PDT 24 543192431 ps
T839 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.3315747593 Jul 19 05:55:59 PM PDT 24 Jul 19 05:56:02 PM PDT 24 2392317163 ps
T840 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.1952117481 Jul 19 05:55:43 PM PDT 24 Jul 19 05:55:46 PM PDT 24 526149473 ps
T841 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.353891357 Jul 19 05:56:04 PM PDT 24 Jul 19 05:56:06 PM PDT 24 500081621 ps
T842 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.375736219 Jul 19 05:56:14 PM PDT 24 Jul 19 05:56:22 PM PDT 24 2679366926 ps
T843 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.63884126 Jul 19 05:56:15 PM PDT 24 Jul 19 05:56:18 PM PDT 24 952732310 ps
T844 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.537945927 Jul 19 05:56:05 PM PDT 24 Jul 19 05:56:10 PM PDT 24 674581320 ps
T845 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.4209146693 Jul 19 05:56:05 PM PDT 24 Jul 19 05:56:07 PM PDT 24 422480460 ps
T846 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.1120652591 Jul 19 05:56:22 PM PDT 24 Jul 19 05:56:26 PM PDT 24 476400769 ps
T847 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.2314818498 Jul 19 05:55:58 PM PDT 24 Jul 19 05:56:00 PM PDT 24 433888638 ps
T848 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.4232356709 Jul 19 05:56:17 PM PDT 24 Jul 19 05:56:24 PM PDT 24 2348023862 ps
T849 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.2667335473 Jul 19 05:56:06 PM PDT 24 Jul 19 05:56:09 PM PDT 24 347459094 ps
T850 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.871309996 Jul 19 05:55:35 PM PDT 24 Jul 19 05:59:02 PM PDT 24 51857835052 ps
T851 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.1886615610 Jul 19 05:56:13 PM PDT 24 Jul 19 05:56:15 PM PDT 24 418421839 ps
T852 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.2964196171 Jul 19 05:55:56 PM PDT 24 Jul 19 05:55:59 PM PDT 24 672364191 ps
T853 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.2105297726 Jul 19 05:56:20 PM PDT 24 Jul 19 05:56:22 PM PDT 24 319877220 ps
T854 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.1239446625 Jul 19 05:56:17 PM PDT 24 Jul 19 05:56:29 PM PDT 24 8273420412 ps
T855 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.2760509555 Jul 19 05:55:49 PM PDT 24 Jul 19 05:55:53 PM PDT 24 566181069 ps
T856 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.3220088753 Jul 19 05:56:21 PM PDT 24 Jul 19 05:56:24 PM PDT 24 419893176 ps
T857 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.1088601002 Jul 19 05:55:41 PM PDT 24 Jul 19 05:55:52 PM PDT 24 4436544462 ps
T858 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.3040405102 Jul 19 05:55:41 PM PDT 24 Jul 19 05:55:44 PM PDT 24 4781807394 ps
T859 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.3755872320 Jul 19 05:55:44 PM PDT 24 Jul 19 05:55:49 PM PDT 24 1210075762 ps
T860 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.1452609909 Jul 19 05:55:44 PM PDT 24 Jul 19 05:55:46 PM PDT 24 803660738 ps
T861 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.3622673 Jul 19 05:55:43 PM PDT 24 Jul 19 05:55:47 PM PDT 24 604859086 ps
T862 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.1523090597 Jul 19 05:56:05 PM PDT 24 Jul 19 05:56:14 PM PDT 24 5198285318 ps
T863 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.3119960124 Jul 19 05:56:22 PM PDT 24 Jul 19 05:56:26 PM PDT 24 470489349 ps
T864 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.1624889825 Jul 19 05:56:07 PM PDT 24 Jul 19 05:56:09 PM PDT 24 461829027 ps
T865 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.2373293855 Jul 19 05:55:56 PM PDT 24 Jul 19 05:56:03 PM PDT 24 2910548019 ps
T866 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.3925305849 Jul 19 05:56:15 PM PDT 24 Jul 19 05:56:17 PM PDT 24 352730483 ps
T867 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.3379069966 Jul 19 05:55:33 PM PDT 24 Jul 19 05:55:35 PM PDT 24 795733353 ps
T868 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.986754916 Jul 19 05:56:23 PM PDT 24 Jul 19 05:56:29 PM PDT 24 382435712 ps
T67 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.1222285631 Jul 19 05:56:13 PM PDT 24 Jul 19 05:56:22 PM PDT 24 8644669831 ps
T869 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.1044264846 Jul 19 05:56:24 PM PDT 24 Jul 19 05:56:27 PM PDT 24 507370095 ps
T870 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.368501220 Jul 19 05:56:13 PM PDT 24 Jul 19 05:56:16 PM PDT 24 586551631 ps
T871 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.815694404 Jul 19 05:55:49 PM PDT 24 Jul 19 05:55:50 PM PDT 24 436239780 ps
T872 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.2035436567 Jul 19 05:55:42 PM PDT 24 Jul 19 05:55:46 PM PDT 24 726711000 ps
T873 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.2059532118 Jul 19 05:55:57 PM PDT 24 Jul 19 05:56:00 PM PDT 24 414510658 ps
T874 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.1009761932 Jul 19 05:56:05 PM PDT 24 Jul 19 05:56:09 PM PDT 24 851163770 ps
T875 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.1415699260 Jul 19 05:56:04 PM PDT 24 Jul 19 05:56:06 PM PDT 24 652544207 ps
T876 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.2589232389 Jul 19 05:56:22 PM PDT 24 Jul 19 05:56:25 PM PDT 24 319503954 ps
T877 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.397308438 Jul 19 05:55:44 PM PDT 24 Jul 19 05:55:48 PM PDT 24 1252538362 ps
T878 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.247746118 Jul 19 05:56:06 PM PDT 24 Jul 19 05:56:09 PM PDT 24 301335592 ps
T879 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.1992162643 Jul 19 05:56:12 PM PDT 24 Jul 19 05:56:14 PM PDT 24 476720102 ps
T880 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.947637855 Jul 19 05:56:05 PM PDT 24 Jul 19 05:56:08 PM PDT 24 513462912 ps
T881 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.2865685073 Jul 19 05:56:13 PM PDT 24 Jul 19 05:56:16 PM PDT 24 372289265 ps
T882 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.1310989077 Jul 19 05:55:53 PM PDT 24 Jul 19 05:55:55 PM PDT 24 578384270 ps
T883 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.3471512822 Jul 19 05:56:05 PM PDT 24 Jul 19 05:56:11 PM PDT 24 4406548723 ps
T884 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.2357571763 Jul 19 05:56:14 PM PDT 24 Jul 19 05:56:17 PM PDT 24 459433840 ps
T885 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.177794915 Jul 19 05:56:23 PM PDT 24 Jul 19 05:56:27 PM PDT 24 357970968 ps
T886 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.3017764435 Jul 19 05:55:33 PM PDT 24 Jul 19 05:55:36 PM PDT 24 1300307000 ps
T887 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.3433766120 Jul 19 05:56:24 PM PDT 24 Jul 19 05:56:28 PM PDT 24 361768666 ps
T888 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.487815311 Jul 19 05:55:42 PM PDT 24 Jul 19 05:55:46 PM PDT 24 328380763 ps
T889 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.4176270339 Jul 19 05:56:05 PM PDT 24 Jul 19 05:56:12 PM PDT 24 7586361839 ps
T890 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.2109374293 Jul 19 05:56:14 PM PDT 24 Jul 19 05:56:16 PM PDT 24 395315845 ps
T891 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.386948187 Jul 19 05:55:42 PM PDT 24 Jul 19 05:55:45 PM PDT 24 4315675079 ps
T892 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.3030695965 Jul 19 05:56:14 PM PDT 24 Jul 19 05:56:16 PM PDT 24 381381698 ps
T893 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.2130983834 Jul 19 05:56:21 PM PDT 24 Jul 19 05:56:23 PM PDT 24 410196730 ps
T894 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.3061354621 Jul 19 05:56:22 PM PDT 24 Jul 19 05:56:24 PM PDT 24 324093332 ps
T895 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.2203735524 Jul 19 05:56:23 PM PDT 24 Jul 19 05:56:36 PM PDT 24 4952113942 ps
T896 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.2024369783 Jul 19 05:56:13 PM PDT 24 Jul 19 05:56:20 PM PDT 24 2521433663 ps
T897 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.3454887590 Jul 19 05:55:56 PM PDT 24 Jul 19 05:56:01 PM PDT 24 2265765842 ps
T898 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.3217438828 Jul 19 05:56:13 PM PDT 24 Jul 19 05:56:16 PM PDT 24 454286431 ps
T899 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.204494119 Jul 19 05:56:21 PM PDT 24 Jul 19 05:56:24 PM PDT 24 339316397 ps
T900 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.4264781027 Jul 19 05:55:52 PM PDT 24 Jul 19 05:56:04 PM PDT 24 4619675324 ps
T901 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.2459324947 Jul 19 05:55:50 PM PDT 24 Jul 19 05:55:59 PM PDT 24 2486263490 ps
T902 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.2542639916 Jul 19 05:56:24 PM PDT 24 Jul 19 05:56:28 PM PDT 24 397238156 ps
T903 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.2630316433 Jul 19 05:55:51 PM PDT 24 Jul 19 05:56:04 PM PDT 24 4437947356 ps
T904 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.4251660579 Jul 19 05:55:57 PM PDT 24 Jul 19 05:56:00 PM PDT 24 432468855 ps
T905 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.531712497 Jul 19 05:56:06 PM PDT 24 Jul 19 05:56:09 PM PDT 24 674728747 ps
T906 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.833378871 Jul 19 05:56:04 PM PDT 24 Jul 19 05:56:18 PM PDT 24 2672011374 ps
T907 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.911917002 Jul 19 05:55:51 PM PDT 24 Jul 19 05:55:53 PM PDT 24 337265554 ps
T908 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.1580447991 Jul 19 05:55:57 PM PDT 24 Jul 19 05:55:59 PM PDT 24 2960824196 ps
T909 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.814205703 Jul 19 05:56:19 PM PDT 24 Jul 19 05:56:27 PM PDT 24 8357206426 ps
T910 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.1915996583 Jul 19 05:56:06 PM PDT 24 Jul 19 05:56:08 PM PDT 24 528803278 ps
T911 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.3893205521 Jul 19 05:55:55 PM PDT 24 Jul 19 05:56:08 PM PDT 24 4273113914 ps
T912 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.2339880875 Jul 19 05:56:22 PM PDT 24 Jul 19 05:56:26 PM PDT 24 564924446 ps
T913 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.221632202 Jul 19 05:56:09 PM PDT 24 Jul 19 05:56:11 PM PDT 24 717767744 ps
T914 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.2045988209 Jul 19 05:55:57 PM PDT 24 Jul 19 05:56:01 PM PDT 24 2098011624 ps
T915 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.2681873227 Jul 19 05:56:06 PM PDT 24 Jul 19 05:56:09 PM PDT 24 461122443 ps
T916 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.2503381581 Jul 19 05:55:33 PM PDT 24 Jul 19 05:55:38 PM PDT 24 535109929 ps
T917 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.2388787170 Jul 19 05:55:49 PM PDT 24 Jul 19 05:55:54 PM PDT 24 980242892 ps
T918 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.1005049108 Jul 19 05:56:05 PM PDT 24 Jul 19 05:56:13 PM PDT 24 4211151894 ps
T919 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.1966463537 Jul 19 05:56:14 PM PDT 24 Jul 19 05:56:17 PM PDT 24 314596942 ps
T920 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.2588891598 Jul 19 05:56:22 PM PDT 24 Jul 19 05:56:26 PM PDT 24 466349059 ps

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.3857528501
Short name T3
Test name
Test status
Simulation time 347031264157 ps
CPU time 144.9 seconds
Started Jul 19 07:06:00 PM PDT 24
Finished Jul 19 07:08:25 PM PDT 24
Peak memory 218088 kb
Host smart-bd894a67-5286-4b82-a3d8-39b78ff8451d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857528501 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.3857528501
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.920382464
Short name T30
Test name
Test status
Simulation time 1653664603778 ps
CPU time 1344.12 seconds
Started Jul 19 07:14:51 PM PDT 24
Finished Jul 19 07:37:17 PM PDT 24
Peak memory 210432 kb
Host smart-12ac7822-dead-4bc6-8665-02dac094be03
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920382464 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.920382464
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.31516784
Short name T33
Test name
Test status
Simulation time 560859662060 ps
CPU time 300.67 seconds
Started Jul 19 07:13:13 PM PDT 24
Finished Jul 19 07:18:17 PM PDT 24
Peak memory 201716 kb
Host smart-bcfe7f18-119b-4bbe-aadd-5fbdd9b49178
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31516784 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gatin
g.31516784
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.2272392559
Short name T29
Test name
Test status
Simulation time 283006023549 ps
CPU time 257.85 seconds
Started Jul 19 07:11:14 PM PDT 24
Finished Jul 19 07:15:49 PM PDT 24
Peak memory 210404 kb
Host smart-1bff495f-8596-4159-990b-11a64f4054e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272392559 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.2272392559
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.2659913338
Short name T219
Test name
Test status
Simulation time 510038520931 ps
CPU time 290.92 seconds
Started Jul 19 07:07:23 PM PDT 24
Finished Jul 19 07:12:18 PM PDT 24
Peak memory 201832 kb
Host smart-c0e5bc39-009d-4e4b-ba67-9ca4f23f7ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659913338 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.2659913338
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.347833267
Short name T12
Test name
Test status
Simulation time 496280654658 ps
CPU time 1187.03 seconds
Started Jul 19 07:16:48 PM PDT 24
Finished Jul 19 07:36:39 PM PDT 24
Peak memory 201728 kb
Host smart-5e0b42bc-df7f-485f-a5cf-1f8cbbeff9b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347833267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.347833267
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.2454741158
Short name T201
Test name
Test status
Simulation time 515053446769 ps
CPU time 1204.51 seconds
Started Jul 19 07:13:26 PM PDT 24
Finished Jul 19 07:33:33 PM PDT 24
Peak memory 201824 kb
Host smart-14175302-5696-485f-a6bd-ad8f1d15130a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454741158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.2454741158
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.888320466
Short name T225
Test name
Test status
Simulation time 543529731510 ps
CPU time 613.79 seconds
Started Jul 19 07:12:26 PM PDT 24
Finished Jul 19 07:22:44 PM PDT 24
Peak memory 201888 kb
Host smart-9aa995db-b9d9-4f3f-98aa-a28c27779393
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888320466 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_
wakeup.888320466
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.564719760
Short name T138
Test name
Test status
Simulation time 488613800107 ps
CPU time 259.66 seconds
Started Jul 19 07:10:16 PM PDT 24
Finished Jul 19 07:14:45 PM PDT 24
Peak memory 201768 kb
Host smart-1af1d3d0-39bb-43f3-bf71-09b44796aae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564719760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.564719760
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.2214451000
Short name T57
Test name
Test status
Simulation time 392618345 ps
CPU time 2.84 seconds
Started Jul 19 05:56:06 PM PDT 24
Finished Jul 19 05:56:10 PM PDT 24
Peak memory 209964 kb
Host smart-2114b234-a4ba-4a21-95b6-5b61a24fe070
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214451000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.2214451000
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.4082797079
Short name T36
Test name
Test status
Simulation time 547708640739 ps
CPU time 1271.69 seconds
Started Jul 19 07:17:26 PM PDT 24
Finished Jul 19 07:38:40 PM PDT 24
Peak memory 201772 kb
Host smart-7d181188-e531-47c8-a404-12d1376676ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082797079 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.4082797079
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.378489654
Short name T54
Test name
Test status
Simulation time 8003081680 ps
CPU time 20.97 seconds
Started Jul 19 07:06:46 PM PDT 24
Finished Jul 19 07:07:08 PM PDT 24
Peak memory 218364 kb
Host smart-2371b68b-9f2f-4da5-a71c-efa4ade6c909
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378489654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.378489654
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.3602994363
Short name T26
Test name
Test status
Simulation time 156410652503 ps
CPU time 104.53 seconds
Started Jul 19 07:16:24 PM PDT 24
Finished Jul 19 07:18:17 PM PDT 24
Peak memory 210076 kb
Host smart-d50a874c-fafd-470f-bf07-48bd1b6e71bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602994363 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.3602994363
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.263827153
Short name T13
Test name
Test status
Simulation time 255428794215 ps
CPU time 309.88 seconds
Started Jul 19 07:06:47 PM PDT 24
Finished Jul 19 07:11:58 PM PDT 24
Peak memory 217932 kb
Host smart-48eaac6b-840d-483d-bf81-9f3eca75dc4c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263827153 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.263827153
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.1531238812
Short name T127
Test name
Test status
Simulation time 490034116466 ps
CPU time 147.78 seconds
Started Jul 19 07:08:36 PM PDT 24
Finished Jul 19 07:11:05 PM PDT 24
Peak memory 201732 kb
Host smart-c9a6d344-7b7b-4ad1-a380-b6c2467be8fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531238812 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.1531238812
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.1091397532
Short name T198
Test name
Test status
Simulation time 522580415260 ps
CPU time 873.26 seconds
Started Jul 19 07:06:58 PM PDT 24
Finished Jul 19 07:21:34 PM PDT 24
Peak memory 201788 kb
Host smart-0d9b4b72-d574-45a9-b170-165234c51dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091397532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.1091397532
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.2211829422
Short name T99
Test name
Test status
Simulation time 566112449 ps
CPU time 1.47 seconds
Started Jul 19 05:55:42 PM PDT 24
Finished Jul 19 05:55:45 PM PDT 24
Peak memory 201428 kb
Host smart-24d352ef-ebc3-4409-bbf7-d1b063b07c98
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211829422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.2211829422
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.549040112
Short name T114
Test name
Test status
Simulation time 333361275196 ps
CPU time 787.56 seconds
Started Jul 19 07:11:13 PM PDT 24
Finished Jul 19 07:24:37 PM PDT 24
Peak memory 201748 kb
Host smart-be3337b8-2c0f-4d42-9f71-1ab17a04866b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549040112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all.
549040112
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.3165694702
Short name T8
Test name
Test status
Simulation time 207153546109 ps
CPU time 147.1 seconds
Started Jul 19 07:15:03 PM PDT 24
Finished Jul 19 07:17:34 PM PDT 24
Peak memory 201740 kb
Host smart-64ec3eb7-a6e5-40ed-a862-0b09a00fcf09
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165694702 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.adc_ctrl_filters_wakeup_fixed.3165694702
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.1566866764
Short name T119
Test name
Test status
Simulation time 449588826834 ps
CPU time 124.38 seconds
Started Jul 19 07:08:02 PM PDT 24
Finished Jul 19 07:10:08 PM PDT 24
Peak memory 201864 kb
Host smart-4f1861ab-2efb-4456-8385-c2fdb5b18827
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566866764 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gati
ng.1566866764
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.907952887
Short name T140
Test name
Test status
Simulation time 334425577457 ps
CPU time 139.81 seconds
Started Jul 19 07:14:09 PM PDT 24
Finished Jul 19 07:16:32 PM PDT 24
Peak memory 201752 kb
Host smart-019c3a33-69e0-4d67-93b8-0629dda30d86
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907952887 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gati
ng.907952887
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.1384224820
Short name T131
Test name
Test status
Simulation time 497165449361 ps
CPU time 329.43 seconds
Started Jul 19 07:04:44 PM PDT 24
Finished Jul 19 07:10:16 PM PDT 24
Peak memory 201800 kb
Host smart-c7bce708-9466-4754-8dc7-76c3a8b7a9b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384224820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.1384224820
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.2335933291
Short name T151
Test name
Test status
Simulation time 511461608327 ps
CPU time 302.38 seconds
Started Jul 19 07:14:24 PM PDT 24
Finished Jul 19 07:19:30 PM PDT 24
Peak memory 201748 kb
Host smart-3459d0a0-8025-449f-ad9e-f1978ea989ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335933291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.2335933291
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.1310221109
Short name T195
Test name
Test status
Simulation time 493923011881 ps
CPU time 1248.2 seconds
Started Jul 19 07:15:39 PM PDT 24
Finished Jul 19 07:36:30 PM PDT 24
Peak memory 201760 kb
Host smart-27d07025-6afd-4423-a1e3-65c6730eee4c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310221109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters
_wakeup.1310221109
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.2129565221
Short name T136
Test name
Test status
Simulation time 320976035495 ps
CPU time 215.63 seconds
Started Jul 19 07:12:51 PM PDT 24
Finished Jul 19 07:16:31 PM PDT 24
Peak memory 201752 kb
Host smart-6396d5b7-bdac-4793-8b9c-6f9adb4dae9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129565221 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.2129565221
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.2227000742
Short name T252
Test name
Test status
Simulation time 564047753199 ps
CPU time 1331.74 seconds
Started Jul 19 07:12:19 PM PDT 24
Finished Jul 19 07:34:34 PM PDT 24
Peak memory 201716 kb
Host smart-b756bd2f-e576-4c09-b695-6721ef2d43e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227000742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.2227000742
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.1854081184
Short name T346
Test name
Test status
Simulation time 484860674 ps
CPU time 1.28 seconds
Started Jul 19 07:10:12 PM PDT 24
Finished Jul 19 07:10:22 PM PDT 24
Peak memory 201676 kb
Host smart-f8a2403d-1977-491e-b5d3-d1c678b91ee7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854081184 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.1854081184
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.2102060757
Short name T227
Test name
Test status
Simulation time 486347058905 ps
CPU time 542.55 seconds
Started Jul 19 07:13:39 PM PDT 24
Finished Jul 19 07:22:43 PM PDT 24
Peak memory 201716 kb
Host smart-7b40b7b4-31cd-4bd8-86be-7fd25e7ec323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102060757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.2102060757
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.2520525209
Short name T51
Test name
Test status
Simulation time 8171624278 ps
CPU time 11.82 seconds
Started Jul 19 05:55:56 PM PDT 24
Finished Jul 19 05:56:09 PM PDT 24
Peak memory 201816 kb
Host smart-28eb8a4f-31a6-451b-8734-6612f6f316fb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520525209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_in
tg_err.2520525209
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.3077044581
Short name T145
Test name
Test status
Simulation time 528968183040 ps
CPU time 314.85 seconds
Started Jul 19 07:16:06 PM PDT 24
Finished Jul 19 07:21:29 PM PDT 24
Peak memory 201720 kb
Host smart-b031658e-1353-4734-920f-b7f188840b4f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077044581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gat
ing.3077044581
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.825821953
Short name T317
Test name
Test status
Simulation time 531220218168 ps
CPU time 326.92 seconds
Started Jul 19 07:16:47 PM PDT 24
Finished Jul 19 07:22:19 PM PDT 24
Peak memory 201784 kb
Host smart-77a8127a-ac26-4387-9755-99c19335c64b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825821953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.825821953
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.267709630
Short name T159
Test name
Test status
Simulation time 326753676248 ps
CPU time 810.01 seconds
Started Jul 19 07:09:33 PM PDT 24
Finished Jul 19 07:23:14 PM PDT 24
Peak memory 201764 kb
Host smart-8c6fc798-956e-4abb-8285-4f708308023c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267709630 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.267709630
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.2801737737
Short name T249
Test name
Test status
Simulation time 491044901254 ps
CPU time 571.74 seconds
Started Jul 19 07:16:06 PM PDT 24
Finished Jul 19 07:25:46 PM PDT 24
Peak memory 201764 kb
Host smart-e1177007-c7a3-4ff7-a836-839fc4f3f164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801737737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.2801737737
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.2862925474
Short name T237
Test name
Test status
Simulation time 628398712221 ps
CPU time 375.87 seconds
Started Jul 19 07:19:15 PM PDT 24
Finished Jul 19 07:25:32 PM PDT 24
Peak memory 201884 kb
Host smart-19519f00-a92b-4300-9d8e-ff2666bd3aac
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862925474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters
_wakeup.2862925474
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.45136049
Short name T35
Test name
Test status
Simulation time 354413984905 ps
CPU time 868.78 seconds
Started Jul 19 07:14:36 PM PDT 24
Finished Jul 19 07:29:08 PM PDT 24
Peak memory 201876 kb
Host smart-c1bc36db-6e0e-4a8c-b7ad-de9c7a1f756a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45136049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all.45136049
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.4234973354
Short name T194
Test name
Test status
Simulation time 353906765862 ps
CPU time 759.4 seconds
Started Jul 19 07:17:00 PM PDT 24
Finished Jul 19 07:29:42 PM PDT 24
Peak memory 201760 kb
Host smart-f81a673f-4879-4087-ae7b-a797b7e00827
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234973354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gat
ing.4234973354
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.3240963153
Short name T160
Test name
Test status
Simulation time 341566934208 ps
CPU time 149.73 seconds
Started Jul 19 07:18:59 PM PDT 24
Finished Jul 19 07:21:31 PM PDT 24
Peak memory 201788 kb
Host smart-c0c1452b-7cce-44f6-9eb1-70790ad5526b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240963153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.3240963153
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.4263506554
Short name T279
Test name
Test status
Simulation time 550116276628 ps
CPU time 850.22 seconds
Started Jul 19 07:17:13 PM PDT 24
Finished Jul 19 07:31:25 PM PDT 24
Peak memory 201796 kb
Host smart-292b6276-554b-4761-91b2-897f1409ac43
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263506554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gat
ing.4263506554
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.3519963447
Short name T272
Test name
Test status
Simulation time 562274728303 ps
CPU time 670.36 seconds
Started Jul 19 07:14:12 PM PDT 24
Finished Jul 19 07:25:25 PM PDT 24
Peak memory 201716 kb
Host smart-5ff53197-d364-4dca-856b-ece617a8aa31
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519963447 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters
_wakeup.3519963447
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.3510301756
Short name T266
Test name
Test status
Simulation time 723881660577 ps
CPU time 1771.17 seconds
Started Jul 19 07:18:33 PM PDT 24
Finished Jul 19 07:48:09 PM PDT 24
Peak memory 201800 kb
Host smart-08f6dd45-d09f-4a33-85cd-fcde08826d9b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510301756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all
.3510301756
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.3785047409
Short name T255
Test name
Test status
Simulation time 329466252187 ps
CPU time 750.09 seconds
Started Jul 19 07:09:14 PM PDT 24
Finished Jul 19 07:21:59 PM PDT 24
Peak memory 201880 kb
Host smart-dd598387-4422-46e0-a866-af77f8297d09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785047409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.3785047409
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.510861077
Short name T299
Test name
Test status
Simulation time 178265477158 ps
CPU time 444.33 seconds
Started Jul 19 07:04:46 PM PDT 24
Finished Jul 19 07:12:12 PM PDT 24
Peak memory 201808 kb
Host smart-9703b724-d369-4c23-acdd-ca0f83a0dbc6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510861077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_w
akeup.510861077
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.1719683034
Short name T128
Test name
Test status
Simulation time 349605939913 ps
CPU time 397.35 seconds
Started Jul 19 07:12:52 PM PDT 24
Finished Jul 19 07:19:33 PM PDT 24
Peak memory 201760 kb
Host smart-bcdd6918-ed17-4267-bf8c-9630b0889c63
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719683034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters
_wakeup.1719683034
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.2642758813
Short name T15
Test name
Test status
Simulation time 633470127044 ps
CPU time 891.33 seconds
Started Jul 19 07:18:01 PM PDT 24
Finished Jul 19 07:32:59 PM PDT 24
Peak memory 217816 kb
Host smart-96489ce0-58f7-42d5-a25f-d3389cda56e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642758813 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.2642758813
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.906494319
Short name T135
Test name
Test status
Simulation time 498102365358 ps
CPU time 1197.67 seconds
Started Jul 19 07:08:46 PM PDT 24
Finished Jul 19 07:28:48 PM PDT 24
Peak memory 201756 kb
Host smart-bd030323-d658-4722-9ad2-5b8257fcc328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906494319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.906494319
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.445365170
Short name T350
Test name
Test status
Simulation time 163970277110 ps
CPU time 388.14 seconds
Started Jul 19 07:15:05 PM PDT 24
Finished Jul 19 07:21:36 PM PDT 24
Peak memory 201688 kb
Host smart-a2b86ced-c3f9-4102-b3f5-6528f80897de
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=445365170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrup
t_fixed.445365170
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.3141278052
Short name T285
Test name
Test status
Simulation time 346641521356 ps
CPU time 548.6 seconds
Started Jul 19 07:16:34 PM PDT 24
Finished Jul 19 07:25:51 PM PDT 24
Peak memory 201760 kb
Host smart-2af52807-0b92-437c-bdfd-3b3e15e410e0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141278052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gat
ing.3141278052
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.2266520100
Short name T28
Test name
Test status
Simulation time 90271387770 ps
CPU time 201.52 seconds
Started Jul 19 07:16:33 PM PDT 24
Finished Jul 19 07:20:02 PM PDT 24
Peak memory 202204 kb
Host smart-540cf736-29c9-4bbc-937a-eb626e27342c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266520100 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.2266520100
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.2350936577
Short name T196
Test name
Test status
Simulation time 399801446919 ps
CPU time 248.92 seconds
Started Jul 19 07:07:33 PM PDT 24
Finished Jul 19 07:11:46 PM PDT 24
Peak memory 201752 kb
Host smart-ce15460c-ee34-4e3a-a6ee-9b8104348682
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350936577 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.
2350936577
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.1222364891
Short name T220
Test name
Test status
Simulation time 326418028198 ps
CPU time 568.11 seconds
Started Jul 19 07:19:17 PM PDT 24
Finished Jul 19 07:28:47 PM PDT 24
Peak memory 201756 kb
Host smart-b99dfbb8-36aa-4afe-841c-3e74e1cf3784
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222364891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gat
ing.1222364891
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.392510944
Short name T226
Test name
Test status
Simulation time 161332282640 ps
CPU time 192.52 seconds
Started Jul 19 07:11:13 PM PDT 24
Finished Jul 19 07:14:42 PM PDT 24
Peak memory 201756 kb
Host smart-5fa7bab3-fb38-4c30-a5a6-738f2e6f03c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392510944 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.392510944
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.910630566
Short name T244
Test name
Test status
Simulation time 168218601786 ps
CPU time 73.09 seconds
Started Jul 19 07:16:23 PM PDT 24
Finished Jul 19 07:17:44 PM PDT 24
Peak memory 201756 kb
Host smart-7231b819-c63a-4d00-bb96-4fe1dc0d8f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910630566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.910630566
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.190311446
Short name T213
Test name
Test status
Simulation time 527388934256 ps
CPU time 654.28 seconds
Started Jul 19 07:16:23 PM PDT 24
Finished Jul 19 07:27:25 PM PDT 24
Peak memory 201740 kb
Host smart-ec2cdb63-0c79-45ef-bd30-bd4c2dbc3e45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190311446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all.
190311446
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.3101924079
Short name T271
Test name
Test status
Simulation time 495832495727 ps
CPU time 451 seconds
Started Jul 19 07:17:14 PM PDT 24
Finished Jul 19 07:24:47 PM PDT 24
Peak memory 201732 kb
Host smart-15e52082-048d-4bc3-aa81-142d25958da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101924079 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.3101924079
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.610136174
Short name T214
Test name
Test status
Simulation time 505199352288 ps
CPU time 305.58 seconds
Started Jul 19 07:08:12 PM PDT 24
Finished Jul 19 07:13:18 PM PDT 24
Peak memory 201872 kb
Host smart-25dcec58-7b0f-4a47-a27f-4a991f1bd717
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610136174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.610136174
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.871309996
Short name T850
Test name
Test status
Simulation time 51857835052 ps
CPU time 205.6 seconds
Started Jul 19 05:55:35 PM PDT 24
Finished Jul 19 05:59:02 PM PDT 24
Peak memory 201732 kb
Host smart-381cc052-8d53-44d9-87a8-9253b519b847
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871309996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_b
ash.871309996
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.3830730598
Short name T295
Test name
Test status
Simulation time 338294859249 ps
CPU time 196.48 seconds
Started Jul 19 07:05:51 PM PDT 24
Finished Jul 19 07:09:08 PM PDT 24
Peak memory 201792 kb
Host smart-2a62043c-fcdd-402c-876e-9ebdc11c0422
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830730598 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_
wakeup.3830730598
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.857396007
Short name T117
Test name
Test status
Simulation time 322187259374 ps
CPU time 744.12 seconds
Started Jul 19 07:14:11 PM PDT 24
Finished Jul 19 07:26:38 PM PDT 24
Peak memory 201728 kb
Host smart-fb7b7f37-1433-4cad-a74f-ca2aadf9742c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857396007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.857396007
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.1944584137
Short name T182
Test name
Test status
Simulation time 74282695851 ps
CPU time 298.33 seconds
Started Jul 19 07:16:22 PM PDT 24
Finished Jul 19 07:21:27 PM PDT 24
Peak memory 202092 kb
Host smart-4b866488-9805-4cfb-95b3-3cc43a8334a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944584137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.1944584137
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.3157367071
Short name T298
Test name
Test status
Simulation time 342276378738 ps
CPU time 766.73 seconds
Started Jul 19 07:17:40 PM PDT 24
Finished Jul 19 07:30:29 PM PDT 24
Peak memory 201824 kb
Host smart-2e530bc9-c3a0-4fc9-afdb-7e51c0480a1e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157367071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters
_wakeup.3157367071
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.907911819
Short name T262
Test name
Test status
Simulation time 372310120409 ps
CPU time 440.6 seconds
Started Jul 19 07:17:53 PM PDT 24
Finished Jul 19 07:25:21 PM PDT 24
Peak memory 201792 kb
Host smart-82c3a780-f96c-43b8-9634-a2ea5077d288
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907911819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_
wakeup.907911819
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.871271790
Short name T253
Test name
Test status
Simulation time 492873135357 ps
CPU time 209.97 seconds
Started Jul 19 07:18:21 PM PDT 24
Finished Jul 19 07:21:55 PM PDT 24
Peak memory 201804 kb
Host smart-67b212f3-0efc-4b7a-977d-fd636a225119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871271790 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.871271790
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.4208816622
Short name T265
Test name
Test status
Simulation time 364991332758 ps
CPU time 222.75 seconds
Started Jul 19 07:05:57 PM PDT 24
Finished Jul 19 07:09:41 PM PDT 24
Peak memory 201888 kb
Host smart-cfad66d3-93e3-4c06-8761-60f017682b8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208816622 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.
4208816622
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.3367375629
Short name T294
Test name
Test status
Simulation time 369657229774 ps
CPU time 927.62 seconds
Started Jul 19 07:13:26 PM PDT 24
Finished Jul 19 07:28:57 PM PDT 24
Peak memory 201744 kb
Host smart-252fe2e5-4bea-458c-81b9-89de5e9ed318
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367375629 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all
.3367375629
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.3738585637
Short name T235
Test name
Test status
Simulation time 540658456611 ps
CPU time 1200.15 seconds
Started Jul 19 07:14:23 PM PDT 24
Finished Jul 19 07:34:27 PM PDT 24
Peak memory 201740 kb
Host smart-cc507ce5-d316-42e9-abc4-70fd6621cc90
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738585637 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gat
ing.3738585637
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.770781893
Short name T228
Test name
Test status
Simulation time 483390014527 ps
CPU time 293.74 seconds
Started Jul 19 07:15:12 PM PDT 24
Finished Jul 19 07:20:08 PM PDT 24
Peak memory 201824 kb
Host smart-982161a0-e530-4ac6-ba1e-4756c401f9ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770781893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.770781893
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.1676659970
Short name T83
Test name
Test status
Simulation time 135947228083 ps
CPU time 439.93 seconds
Started Jul 19 07:06:59 PM PDT 24
Finished Jul 19 07:14:21 PM PDT 24
Peak memory 211724 kb
Host smart-c499e28d-fcb2-4ca1-9401-e359d0ec64b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676659970 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.1676659970
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.39644422
Short name T65
Test name
Test status
Simulation time 8250154726 ps
CPU time 8.44 seconds
Started Jul 19 05:55:36 PM PDT 24
Finished Jul 19 05:55:45 PM PDT 24
Peak memory 201728 kb
Host smart-1e5df415-62d6-4f42-b6ba-d244f14d3418
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39644422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_intg
_err.39644422
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.3040405102
Short name T858
Test name
Test status
Simulation time 4781807394 ps
CPU time 2.51 seconds
Started Jul 19 05:55:41 PM PDT 24
Finished Jul 19 05:55:44 PM PDT 24
Peak memory 201964 kb
Host smart-9536b06f-12b4-4176-a046-2056da137fa0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040405102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_in
tg_err.3040405102
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.115123741
Short name T698
Test name
Test status
Simulation time 186760735110 ps
CPU time 99.83 seconds
Started Jul 19 07:05:21 PM PDT 24
Finished Jul 19 07:07:04 PM PDT 24
Peak memory 217756 kb
Host smart-018094e7-9faa-41f6-8c9e-86ab14bf416a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115123741 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.115123741
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.3288297262
Short name T240
Test name
Test status
Simulation time 176363114010 ps
CPU time 406.72 seconds
Started Jul 19 07:09:36 PM PDT 24
Finished Jul 19 07:16:33 PM PDT 24
Peak memory 201756 kb
Host smart-67769dda-af0e-43cd-862f-25a25c7da2bc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288297262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters
_wakeup.3288297262
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.3114527276
Short name T311
Test name
Test status
Simulation time 571787912107 ps
CPU time 390.43 seconds
Started Jul 19 07:09:58 PM PDT 24
Finished Jul 19 07:16:31 PM PDT 24
Peak memory 201800 kb
Host smart-b1e1f94d-2f79-4fcf-9690-af7e9718c051
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114527276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gat
ing.3114527276
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.3248091830
Short name T287
Test name
Test status
Simulation time 159559785924 ps
CPU time 388.16 seconds
Started Jul 19 07:10:11 PM PDT 24
Finished Jul 19 07:16:47 PM PDT 24
Peak memory 201712 kb
Host smart-c36182c8-9339-4bbd-8e01-12ffe8e073bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248091830 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.3248091830
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.2134696853
Short name T319
Test name
Test status
Simulation time 180635471037 ps
CPU time 104.22 seconds
Started Jul 19 07:09:58 PM PDT 24
Finished Jul 19 07:11:44 PM PDT 24
Peak memory 201756 kb
Host smart-76a825e6-8a01-4e3a-a3f6-1f3a3ad1a0e6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134696853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters
_wakeup.2134696853
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.2356351509
Short name T191
Test name
Test status
Simulation time 76028100000 ps
CPU time 397.11 seconds
Started Jul 19 07:11:15 PM PDT 24
Finished Jul 19 07:18:09 PM PDT 24
Peak memory 202104 kb
Host smart-88e6a88b-2d61-42fd-bb37-af328006a12b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356351509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.2356351509
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.1807571624
Short name T175
Test name
Test status
Simulation time 332650616453 ps
CPU time 408.21 seconds
Started Jul 19 07:11:21 PM PDT 24
Finished Jul 19 07:18:23 PM PDT 24
Peak memory 201812 kb
Host smart-be584dab-c58c-44e7-807f-8b9789e7ed97
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807571624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gat
ing.1807571624
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.2337114068
Short name T188
Test name
Test status
Simulation time 110805966263 ps
CPU time 462.15 seconds
Started Jul 19 07:11:22 PM PDT 24
Finished Jul 19 07:19:18 PM PDT 24
Peak memory 202076 kb
Host smart-9a5e3e44-ef26-4a70-96a7-77de94b8df38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337114068 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.2337114068
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.3919170274
Short name T684
Test name
Test status
Simulation time 406055787447 ps
CPU time 1073.76 seconds
Started Jul 19 07:11:42 PM PDT 24
Finished Jul 19 07:29:41 PM PDT 24
Peak memory 202120 kb
Host smart-ab996067-9829-40c5-90c5-b4a8dd008fe0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919170274 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all
.3919170274
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.1881532079
Short name T97
Test name
Test status
Simulation time 266606123210 ps
CPU time 414.35 seconds
Started Jul 19 07:12:28 PM PDT 24
Finished Jul 19 07:19:27 PM PDT 24
Peak memory 210460 kb
Host smart-5f5ba4b8-eab0-4d23-922e-04a0f79bea47
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881532079 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.1881532079
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.3584885629
Short name T209
Test name
Test status
Simulation time 488044365331 ps
CPU time 1057.59 seconds
Started Jul 19 07:14:36 PM PDT 24
Finished Jul 19 07:32:17 PM PDT 24
Peak memory 201816 kb
Host smart-162bb122-7e11-482e-9f67-0bbc270a3f3a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584885629 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters
_wakeup.3584885629
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.2858553809
Short name T34
Test name
Test status
Simulation time 584335490377 ps
CPU time 1047.89 seconds
Started Jul 19 07:15:39 PM PDT 24
Finished Jul 19 07:33:09 PM PDT 24
Peak memory 202096 kb
Host smart-4ecfa88b-0271-4fbd-bf40-cd8fde81c5c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858553809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all
.2858553809
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.4279160804
Short name T274
Test name
Test status
Simulation time 353379558173 ps
CPU time 197.21 seconds
Started Jul 19 07:16:22 PM PDT 24
Finished Jul 19 07:19:46 PM PDT 24
Peak memory 201768 kb
Host smart-54010989-7bef-48c1-a3e3-08e1ce6f28bc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279160804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gat
ing.4279160804
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.868912472
Short name T167
Test name
Test status
Simulation time 527364413889 ps
CPU time 171.4 seconds
Started Jul 19 07:16:59 PM PDT 24
Finished Jul 19 07:19:54 PM PDT 24
Peak memory 201756 kb
Host smart-b924713b-41dc-4037-85b2-63c3cfa1bc64
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868912472 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_
wakeup.868912472
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.403975664
Short name T251
Test name
Test status
Simulation time 333836508603 ps
CPU time 168.17 seconds
Started Jul 19 07:17:38 PM PDT 24
Finished Jul 19 07:20:29 PM PDT 24
Peak memory 201952 kb
Host smart-ef90ee28-95d1-4f35-97c2-0b91f545578f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403975664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.403975664
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.2474774268
Short name T20
Test name
Test status
Simulation time 1238380333164 ps
CPU time 426.43 seconds
Started Jul 19 07:07:33 PM PDT 24
Finished Jul 19 07:14:43 PM PDT 24
Peak memory 217888 kb
Host smart-c2e566d5-b680-4f52-b86b-b58c0a968875
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474774268 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.2474774268
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.1171298174
Short name T186
Test name
Test status
Simulation time 130663889464 ps
CPU time 306.13 seconds
Started Jul 19 07:17:49 PM PDT 24
Finished Jul 19 07:23:01 PM PDT 24
Peak memory 210440 kb
Host smart-8e159a59-9530-4d53-bba9-8545fa76633e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171298174 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.1171298174
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.2799387534
Short name T187
Test name
Test status
Simulation time 124428576254 ps
CPU time 410.08 seconds
Started Jul 19 07:17:58 PM PDT 24
Finished Jul 19 07:24:55 PM PDT 24
Peak memory 202104 kb
Host smart-7140113a-3a5f-4a95-8a08-7fa7110d2556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799387534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.2799387534
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.4279298880
Short name T261
Test name
Test status
Simulation time 321577809231 ps
CPU time 738.6 seconds
Started Jul 19 07:19:15 PM PDT 24
Finished Jul 19 07:31:34 PM PDT 24
Peak memory 201724 kb
Host smart-9e2739f3-508b-4f75-9167-3204e95f8c44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279298880 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.4279298880
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.3543065653
Short name T234
Test name
Test status
Simulation time 194890718826 ps
CPU time 85.92 seconds
Started Jul 19 07:09:05 PM PDT 24
Finished Jul 19 07:10:40 PM PDT 24
Peak memory 210448 kb
Host smart-ec38ef16-0edf-49ed-ad8c-72fcbf6db8cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543065653 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.3543065653
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.3379069966
Short name T867
Test name
Test status
Simulation time 795733353 ps
CPU time 1.9 seconds
Started Jul 19 05:55:33 PM PDT 24
Finished Jul 19 05:55:35 PM PDT 24
Peak memory 201720 kb
Host smart-744bca42-5536-42e8-b989-da6d847c50e2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379069966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alia
sing.3379069966
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.3017764435
Short name T886
Test name
Test status
Simulation time 1300307000 ps
CPU time 2 seconds
Started Jul 19 05:55:33 PM PDT 24
Finished Jul 19 05:55:36 PM PDT 24
Peak memory 201468 kb
Host smart-d39f1d61-fd18-4f2a-b7c3-366d3d83f2ff
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017764435 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_r
eset.3017764435
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.1952117481
Short name T840
Test name
Test status
Simulation time 526149473 ps
CPU time 1.2 seconds
Started Jul 19 05:55:43 PM PDT 24
Finished Jul 19 05:55:46 PM PDT 24
Peak memory 201672 kb
Host smart-47dcc43f-2b72-402d-b5a5-4621d093413d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952117481 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.1952117481
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.3199871281
Short name T103
Test name
Test status
Simulation time 374990553 ps
CPU time 1.72 seconds
Started Jul 19 05:55:35 PM PDT 24
Finished Jul 19 05:55:37 PM PDT 24
Peak memory 201420 kb
Host smart-4d291931-154c-47e2-9e4c-eadeb3cfb3be
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199871281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.3199871281
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.2384016342
Short name T805
Test name
Test status
Simulation time 400949695 ps
CPU time 1.12 seconds
Started Jul 19 05:55:34 PM PDT 24
Finished Jul 19 05:55:36 PM PDT 24
Peak memory 201436 kb
Host smart-54abdcc8-45d3-464e-a3a6-b27815a7efd1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384016342 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.2384016342
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.521101216
Short name T47
Test name
Test status
Simulation time 2038663867 ps
CPU time 7.47 seconds
Started Jul 19 05:55:43 PM PDT 24
Finished Jul 19 05:55:51 PM PDT 24
Peak memory 201512 kb
Host smart-1c50954d-a345-44cc-8ef2-1866b3e17563
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521101216 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ct
rl_same_csr_outstanding.521101216
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.2503381581
Short name T916
Test name
Test status
Simulation time 535109929 ps
CPU time 3.46 seconds
Started Jul 19 05:55:33 PM PDT 24
Finished Jul 19 05:55:38 PM PDT 24
Peak memory 201820 kb
Host smart-84a0f104-5c3e-4453-9723-9df54cd1f86a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503381581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.2503381581
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.748485939
Short name T104
Test name
Test status
Simulation time 792956228 ps
CPU time 3.29 seconds
Started Jul 19 05:55:43 PM PDT 24
Finished Jul 19 05:55:48 PM PDT 24
Peak memory 201628 kb
Host smart-110221ef-f1b6-414b-9be0-b748211d9b7e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748485939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alias
ing.748485939
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.3952603200
Short name T804
Test name
Test status
Simulation time 27085024331 ps
CPU time 18.59 seconds
Started Jul 19 05:55:41 PM PDT 24
Finished Jul 19 05:56:00 PM PDT 24
Peak memory 201736 kb
Host smart-1a1c0015-cb7f-4b6b-801a-8e364f678426
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952603200 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_
bash.3952603200
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.3755872320
Short name T859
Test name
Test status
Simulation time 1210075762 ps
CPU time 3.62 seconds
Started Jul 19 05:55:44 PM PDT 24
Finished Jul 19 05:55:49 PM PDT 24
Peak memory 201568 kb
Host smart-54a60100-66b3-4265-827b-c3349b3e3ee0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755872320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_r
eset.3755872320
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.2954588070
Short name T90
Test name
Test status
Simulation time 491911839 ps
CPU time 1.96 seconds
Started Jul 19 05:55:43 PM PDT 24
Finished Jul 19 05:55:46 PM PDT 24
Peak memory 201536 kb
Host smart-61adcb8a-88e8-4baf-a1ca-b7ffee805ae1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954588070 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.2954588070
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.3027027578
Short name T797
Test name
Test status
Simulation time 418825234 ps
CPU time 0.88 seconds
Started Jul 19 05:55:43 PM PDT 24
Finished Jul 19 05:55:45 PM PDT 24
Peak memory 201348 kb
Host smart-f21bac81-32bb-492c-bc62-3610ef4e0e2a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027027578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.3027027578
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.1088601002
Short name T857
Test name
Test status
Simulation time 4436544462 ps
CPU time 9.52 seconds
Started Jul 19 05:55:41 PM PDT 24
Finished Jul 19 05:55:52 PM PDT 24
Peak memory 201780 kb
Host smart-ff4d606b-de17-4917-b547-af181b35e180
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088601002 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_c
trl_same_csr_outstanding.1088601002
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.3622673
Short name T861
Test name
Test status
Simulation time 604859086 ps
CPU time 3.05 seconds
Started Jul 19 05:55:43 PM PDT 24
Finished Jul 19 05:55:47 PM PDT 24
Peak memory 201732 kb
Host smart-86226611-0711-468f-9364-185768a83409
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.3622673
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.353891357
Short name T841
Test name
Test status
Simulation time 500081621 ps
CPU time 1.26 seconds
Started Jul 19 05:56:04 PM PDT 24
Finished Jul 19 05:56:06 PM PDT 24
Peak memory 201612 kb
Host smart-e481eae6-70ac-4004-a98f-a3039cdc3f48
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353891357 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.353891357
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.2681873227
Short name T915
Test name
Test status
Simulation time 461122443 ps
CPU time 1.34 seconds
Started Jul 19 05:56:06 PM PDT 24
Finished Jul 19 05:56:09 PM PDT 24
Peak memory 201436 kb
Host smart-63ce862e-1f8c-4780-9af1-c40641e6fc8c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681873227 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.2681873227
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.247746118
Short name T878
Test name
Test status
Simulation time 301335592 ps
CPU time 1.16 seconds
Started Jul 19 05:56:06 PM PDT 24
Finished Jul 19 05:56:09 PM PDT 24
Peak memory 201436 kb
Host smart-12e41172-fcac-4fff-8332-f355aa394e7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247746118 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.247746118
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.3471512822
Short name T883
Test name
Test status
Simulation time 4406548723 ps
CPU time 3.52 seconds
Started Jul 19 05:56:05 PM PDT 24
Finished Jul 19 05:56:11 PM PDT 24
Peak memory 201796 kb
Host smart-264541c5-84e2-4082-b697-67c68a62ae6d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471512822 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_
ctrl_same_csr_outstanding.3471512822
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.633840327
Short name T58
Test name
Test status
Simulation time 843684915 ps
CPU time 2.2 seconds
Started Jul 19 05:55:58 PM PDT 24
Finished Jul 19 05:56:00 PM PDT 24
Peak memory 218056 kb
Host smart-7af70f93-b68f-4ae8-b067-cf1d85a59649
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633840327 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.633840327
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.1005049108
Short name T918
Test name
Test status
Simulation time 4211151894 ps
CPU time 6.82 seconds
Started Jul 19 05:56:05 PM PDT 24
Finished Jul 19 05:56:13 PM PDT 24
Peak memory 201764 kb
Host smart-8da6612e-c977-41ba-9135-c7c6a0ff3169
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005049108 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_i
ntg_err.1005049108
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.2838195697
Short name T833
Test name
Test status
Simulation time 397620721 ps
CPU time 1.94 seconds
Started Jul 19 05:56:04 PM PDT 24
Finished Jul 19 05:56:07 PM PDT 24
Peak memory 201560 kb
Host smart-aa4fca93-f418-4354-b366-44f63be6343b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838195697 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.2838195697
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.1415699260
Short name T875
Test name
Test status
Simulation time 652544207 ps
CPU time 0.9 seconds
Started Jul 19 05:56:04 PM PDT 24
Finished Jul 19 05:56:06 PM PDT 24
Peak memory 201432 kb
Host smart-96259c93-62d6-4808-b8d9-681d1a57786e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415699260 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.1415699260
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.37226369
Short name T821
Test name
Test status
Simulation time 441923182 ps
CPU time 0.87 seconds
Started Jul 19 05:56:07 PM PDT 24
Finished Jul 19 05:56:09 PM PDT 24
Peak memory 201436 kb
Host smart-f247750c-680d-4678-8cfb-23335f44d06a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37226369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.37226369
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.1523090597
Short name T862
Test name
Test status
Simulation time 5198285318 ps
CPU time 7.22 seconds
Started Jul 19 05:56:05 PM PDT 24
Finished Jul 19 05:56:14 PM PDT 24
Peak memory 201840 kb
Host smart-825c6464-d894-4ae6-83ff-b2481f736bd7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523090597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_
ctrl_same_csr_outstanding.1523090597
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.537945927
Short name T844
Test name
Test status
Simulation time 674581320 ps
CPU time 3.06 seconds
Started Jul 19 05:56:05 PM PDT 24
Finished Jul 19 05:56:10 PM PDT 24
Peak memory 218072 kb
Host smart-78d71184-3e8a-4c5e-b007-4894fd365778
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537945927 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.537945927
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.4176270339
Short name T889
Test name
Test status
Simulation time 7586361839 ps
CPU time 6.69 seconds
Started Jul 19 05:56:05 PM PDT 24
Finished Jul 19 05:56:12 PM PDT 24
Peak memory 201800 kb
Host smart-77788625-d7f6-496f-8ad8-4c9e0d06d3e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176270339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_i
ntg_err.4176270339
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.221632202
Short name T913
Test name
Test status
Simulation time 717767744 ps
CPU time 1.41 seconds
Started Jul 19 05:56:09 PM PDT 24
Finished Jul 19 05:56:11 PM PDT 24
Peak memory 201740 kb
Host smart-858e6bff-ec4d-43ac-8670-1c9acee3deb3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221632202 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.221632202
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.2995279326
Short name T100
Test name
Test status
Simulation time 354220670 ps
CPU time 1.6 seconds
Started Jul 19 05:56:06 PM PDT 24
Finished Jul 19 05:56:09 PM PDT 24
Peak memory 201440 kb
Host smart-88f54c70-fdbf-4dc9-aa28-97e02cdd58ab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995279326 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.2995279326
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.2225513370
Short name T793
Test name
Test status
Simulation time 440393474 ps
CPU time 0.9 seconds
Started Jul 19 05:56:06 PM PDT 24
Finished Jul 19 05:56:09 PM PDT 24
Peak memory 201608 kb
Host smart-c93d1d01-6289-4c17-b350-6d57fa25e139
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225513370 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.2225513370
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.833378871
Short name T906
Test name
Test status
Simulation time 2672011374 ps
CPU time 12.53 seconds
Started Jul 19 05:56:04 PM PDT 24
Finished Jul 19 05:56:18 PM PDT 24
Peak memory 201608 kb
Host smart-5aa2dc53-37ef-4593-8dd6-9f52d0675b4f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833378871 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_c
trl_same_csr_outstanding.833378871
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.1117668508
Short name T66
Test name
Test status
Simulation time 5032092137 ps
CPU time 2.41 seconds
Started Jul 19 05:56:06 PM PDT 24
Finished Jul 19 05:56:10 PM PDT 24
Peak memory 201708 kb
Host smart-529f9178-c588-4b5e-8acf-4042874f07b7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117668508 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_i
ntg_err.1117668508
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.4209146693
Short name T845
Test name
Test status
Simulation time 422480460 ps
CPU time 1.07 seconds
Started Jul 19 05:56:05 PM PDT 24
Finished Jul 19 05:56:07 PM PDT 24
Peak memory 201560 kb
Host smart-a5d33740-a557-492a-b5e6-5a25c8c9fc43
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209146693 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.4209146693
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.1624889825
Short name T864
Test name
Test status
Simulation time 461829027 ps
CPU time 0.92 seconds
Started Jul 19 05:56:07 PM PDT 24
Finished Jul 19 05:56:09 PM PDT 24
Peak memory 201412 kb
Host smart-3dc7b006-3eb9-48e6-8894-98d57d14286f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624889825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.1624889825
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.1915996583
Short name T910
Test name
Test status
Simulation time 528803278 ps
CPU time 0.72 seconds
Started Jul 19 05:56:06 PM PDT 24
Finished Jul 19 05:56:08 PM PDT 24
Peak memory 201428 kb
Host smart-3d56e513-03e1-4e6f-bb43-5bb14b8c57dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915996583 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.1915996583
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.3721726132
Short name T108
Test name
Test status
Simulation time 1814743044 ps
CPU time 7.88 seconds
Started Jul 19 05:56:05 PM PDT 24
Finished Jul 19 05:56:15 PM PDT 24
Peak memory 201536 kb
Host smart-f74e8b86-02fa-4680-b640-141eaae944da
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721726132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_
ctrl_same_csr_outstanding.3721726132
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.1009761932
Short name T874
Test name
Test status
Simulation time 851163770 ps
CPU time 2.75 seconds
Started Jul 19 05:56:05 PM PDT 24
Finished Jul 19 05:56:09 PM PDT 24
Peak memory 218152 kb
Host smart-ed90a7af-3831-4e28-8018-adabda2cc9e7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009761932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.1009761932
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.1568342420
Short name T836
Test name
Test status
Simulation time 4309689183 ps
CPU time 6.86 seconds
Started Jul 19 05:56:04 PM PDT 24
Finished Jul 19 05:56:12 PM PDT 24
Peak memory 201796 kb
Host smart-51332dc0-74b5-41ea-89e4-4c25d32a1028
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568342420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_i
ntg_err.1568342420
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.1498653811
Short name T803
Test name
Test status
Simulation time 364398135 ps
CPU time 1.21 seconds
Started Jul 19 05:56:16 PM PDT 24
Finished Jul 19 05:56:18 PM PDT 24
Peak memory 201588 kb
Host smart-6d69326e-0acc-4bc8-b5de-8510b8272d9e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498653811 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.1498653811
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.1136253208
Short name T105
Test name
Test status
Simulation time 353576892 ps
CPU time 1.63 seconds
Started Jul 19 05:56:14 PM PDT 24
Finished Jul 19 05:56:17 PM PDT 24
Peak memory 201436 kb
Host smart-7acc4f22-33ba-4043-b719-4942150517c2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136253208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.1136253208
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.2357571763
Short name T884
Test name
Test status
Simulation time 459433840 ps
CPU time 1.73 seconds
Started Jul 19 05:56:14 PM PDT 24
Finished Jul 19 05:56:17 PM PDT 24
Peak memory 201468 kb
Host smart-0af112d8-8778-4bc5-acee-cd83cb1deeba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357571763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.2357571763
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.4232356709
Short name T848
Test name
Test status
Simulation time 2348023862 ps
CPU time 5.54 seconds
Started Jul 19 05:56:17 PM PDT 24
Finished Jul 19 05:56:24 PM PDT 24
Peak memory 201576 kb
Host smart-513fce3f-f68d-4c62-ab34-5f98922a72d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232356709 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_
ctrl_same_csr_outstanding.4232356709
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.292514255
Short name T64
Test name
Test status
Simulation time 440885191 ps
CPU time 1.53 seconds
Started Jul 19 05:56:13 PM PDT 24
Finished Jul 19 05:56:15 PM PDT 24
Peak memory 201808 kb
Host smart-521aac26-e937-4234-b81c-e1b93df20d90
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292514255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.292514255
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.1222285631
Short name T67
Test name
Test status
Simulation time 8644669831 ps
CPU time 7.57 seconds
Started Jul 19 05:56:13 PM PDT 24
Finished Jul 19 05:56:22 PM PDT 24
Peak memory 201844 kb
Host smart-02dc38ac-2cf5-4f9d-b020-d8ae2f3e5977
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222285631 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_i
ntg_err.1222285631
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.2990693663
Short name T831
Test name
Test status
Simulation time 408325735 ps
CPU time 1.78 seconds
Started Jul 19 05:56:14 PM PDT 24
Finished Jul 19 05:56:17 PM PDT 24
Peak memory 201544 kb
Host smart-dda4a3bb-0f9c-426d-809a-39cf26e96dc6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990693663 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.2990693663
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.368501220
Short name T870
Test name
Test status
Simulation time 586551631 ps
CPU time 1.15 seconds
Started Jul 19 05:56:13 PM PDT 24
Finished Jul 19 05:56:16 PM PDT 24
Peak memory 201444 kb
Host smart-965aae4b-c4c7-4da1-86aa-176cf139199c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368501220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.368501220
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.2109374293
Short name T890
Test name
Test status
Simulation time 395315845 ps
CPU time 1.47 seconds
Started Jul 19 05:56:14 PM PDT 24
Finished Jul 19 05:56:16 PM PDT 24
Peak memory 201432 kb
Host smart-c3331ec5-96d6-422d-99ea-c282d49b7905
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109374293 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.2109374293
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.512962225
Short name T110
Test name
Test status
Simulation time 1870055996 ps
CPU time 2.36 seconds
Started Jul 19 05:56:14 PM PDT 24
Finished Jul 19 05:56:18 PM PDT 24
Peak memory 201552 kb
Host smart-88f162b7-0c46-4991-83bf-055714fd42cc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512962225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_c
trl_same_csr_outstanding.512962225
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.1886615610
Short name T851
Test name
Test status
Simulation time 418421839 ps
CPU time 1.42 seconds
Started Jul 19 05:56:13 PM PDT 24
Finished Jul 19 05:56:15 PM PDT 24
Peak memory 201800 kb
Host smart-872f7df9-047d-4b19-a159-bf23e75eae3b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886615610 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.1886615610
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.814205703
Short name T909
Test name
Test status
Simulation time 8357206426 ps
CPU time 7.36 seconds
Started Jul 19 05:56:19 PM PDT 24
Finished Jul 19 05:56:27 PM PDT 24
Peak memory 201812 kb
Host smart-90a7903e-7c81-4cf5-b3b4-dbac2c9a2947
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814205703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_in
tg_err.814205703
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.2511487484
Short name T822
Test name
Test status
Simulation time 644098824 ps
CPU time 1.73 seconds
Started Jul 19 05:56:15 PM PDT 24
Finished Jul 19 05:56:18 PM PDT 24
Peak memory 201584 kb
Host smart-24b16f07-b3cf-423d-a0bc-802660a94fe1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511487484 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.2511487484
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.1992162643
Short name T879
Test name
Test status
Simulation time 476720102 ps
CPU time 1.25 seconds
Started Jul 19 05:56:12 PM PDT 24
Finished Jul 19 05:56:14 PM PDT 24
Peak memory 201436 kb
Host smart-1a5979c4-70f0-4620-bbcc-ef7e25b92234
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992162643 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.1992162643
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.3925305849
Short name T866
Test name
Test status
Simulation time 352730483 ps
CPU time 0.82 seconds
Started Jul 19 05:56:15 PM PDT 24
Finished Jul 19 05:56:17 PM PDT 24
Peak memory 201480 kb
Host smart-d1f899c6-21ad-49be-af50-aa81871adac8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925305849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.3925305849
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.399075644
Short name T46
Test name
Test status
Simulation time 3938085939 ps
CPU time 9.45 seconds
Started Jul 19 05:56:19 PM PDT 24
Finished Jul 19 05:56:29 PM PDT 24
Peak memory 201756 kb
Host smart-395e13fb-c2c5-4648-bcd7-596a13c9de41
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399075644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_c
trl_same_csr_outstanding.399075644
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.63884126
Short name T843
Test name
Test status
Simulation time 952732310 ps
CPU time 2.01 seconds
Started Jul 19 05:56:15 PM PDT 24
Finished Jul 19 05:56:18 PM PDT 24
Peak memory 218128 kb
Host smart-220fead1-7efe-4717-97d1-b25121236b7f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63884126 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.63884126
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.1239446625
Short name T854
Test name
Test status
Simulation time 8273420412 ps
CPU time 11.33 seconds
Started Jul 19 05:56:17 PM PDT 24
Finished Jul 19 05:56:29 PM PDT 24
Peak memory 201848 kb
Host smart-dd1f9eb6-8695-4495-96dd-cff85fe762ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239446625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_i
ntg_err.1239446625
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.2603667578
Short name T837
Test name
Test status
Simulation time 562446739 ps
CPU time 1.31 seconds
Started Jul 19 05:56:15 PM PDT 24
Finished Jul 19 05:56:18 PM PDT 24
Peak memory 201632 kb
Host smart-b501d3f2-9f3b-41cf-bb66-416918913186
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603667578 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.2603667578
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.2865685073
Short name T881
Test name
Test status
Simulation time 372289265 ps
CPU time 0.88 seconds
Started Jul 19 05:56:13 PM PDT 24
Finished Jul 19 05:56:16 PM PDT 24
Peak memory 201480 kb
Host smart-fc5db002-752a-474b-97b0-b687b0f4e5dc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865685073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.2865685073
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.3030695965
Short name T892
Test name
Test status
Simulation time 381381698 ps
CPU time 0.74 seconds
Started Jul 19 05:56:14 PM PDT 24
Finished Jul 19 05:56:16 PM PDT 24
Peak memory 201436 kb
Host smart-891b9876-c027-439d-a148-22986f46ab8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030695965 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.3030695965
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.375736219
Short name T842
Test name
Test status
Simulation time 2679366926 ps
CPU time 5.88 seconds
Started Jul 19 05:56:14 PM PDT 24
Finished Jul 19 05:56:22 PM PDT 24
Peak memory 201564 kb
Host smart-d79fed35-cb72-4953-917f-88e063f1c155
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375736219 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_c
trl_same_csr_outstanding.375736219
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.3402128832
Short name T63
Test name
Test status
Simulation time 2456475262 ps
CPU time 2.78 seconds
Started Jul 19 05:56:19 PM PDT 24
Finished Jul 19 05:56:23 PM PDT 24
Peak memory 210076 kb
Host smart-e7bd77e4-0ee5-4a83-8627-b8758d77656e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402128832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.3402128832
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.1093625153
Short name T812
Test name
Test status
Simulation time 3797520681 ps
CPU time 5.98 seconds
Started Jul 19 05:56:15 PM PDT 24
Finished Jul 19 05:56:22 PM PDT 24
Peak memory 201744 kb
Host smart-5b03dae9-b27f-413b-99be-4d5af3866383
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093625153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_i
ntg_err.1093625153
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.1242495094
Short name T830
Test name
Test status
Simulation time 422773185 ps
CPU time 1.86 seconds
Started Jul 19 05:56:13 PM PDT 24
Finished Jul 19 05:56:15 PM PDT 24
Peak memory 201664 kb
Host smart-a498257e-7828-43dc-9e97-5d6c9e7116ba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242495094 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.1242495094
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.549327092
Short name T106
Test name
Test status
Simulation time 302329223 ps
CPU time 1.46 seconds
Started Jul 19 05:56:14 PM PDT 24
Finished Jul 19 05:56:17 PM PDT 24
Peak memory 201464 kb
Host smart-c31fe8e5-5ef6-471e-b778-7c4532e29e51
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549327092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.549327092
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.3217438828
Short name T898
Test name
Test status
Simulation time 454286431 ps
CPU time 1.64 seconds
Started Jul 19 05:56:13 PM PDT 24
Finished Jul 19 05:56:16 PM PDT 24
Peak memory 201440 kb
Host smart-fb9beea2-d6af-4341-b9c0-ec9fe4a30b64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217438828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.3217438828
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.2024369783
Short name T896
Test name
Test status
Simulation time 2521433663 ps
CPU time 6.1 seconds
Started Jul 19 05:56:13 PM PDT 24
Finished Jul 19 05:56:20 PM PDT 24
Peak memory 201520 kb
Host smart-51df08f7-848f-4463-aa4e-c9cf78830cc5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024369783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_
ctrl_same_csr_outstanding.2024369783
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.1966463537
Short name T919
Test name
Test status
Simulation time 314596942 ps
CPU time 2.46 seconds
Started Jul 19 05:56:14 PM PDT 24
Finished Jul 19 05:56:17 PM PDT 24
Peak memory 210008 kb
Host smart-9d6a16cd-5cf8-4092-9e95-7b82afa23450
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966463537 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.1966463537
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.3930303815
Short name T50
Test name
Test status
Simulation time 8087795723 ps
CPU time 7.29 seconds
Started Jul 19 05:56:15 PM PDT 24
Finished Jul 19 05:56:23 PM PDT 24
Peak memory 201840 kb
Host smart-d8743ab7-9917-4987-9671-d927d708bd29
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930303815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_i
ntg_err.3930303815
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.2588891598
Short name T920
Test name
Test status
Simulation time 466349059 ps
CPU time 1.08 seconds
Started Jul 19 05:56:22 PM PDT 24
Finished Jul 19 05:56:26 PM PDT 24
Peak memory 201736 kb
Host smart-7b3da6f4-d107-4bb1-a30d-382b50513051
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588891598 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.2588891598
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.3433766120
Short name T887
Test name
Test status
Simulation time 361768666 ps
CPU time 1.2 seconds
Started Jul 19 05:56:24 PM PDT 24
Finished Jul 19 05:56:28 PM PDT 24
Peak memory 200756 kb
Host smart-039544c8-5156-4577-9597-7d6b4426b386
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433766120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.3433766120
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.2105297726
Short name T853
Test name
Test status
Simulation time 319877220 ps
CPU time 1.45 seconds
Started Jul 19 05:56:20 PM PDT 24
Finished Jul 19 05:56:22 PM PDT 24
Peak memory 201400 kb
Host smart-73406d7e-1799-4eeb-823b-01387c8dc000
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105297726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.2105297726
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.2203735524
Short name T895
Test name
Test status
Simulation time 4952113942 ps
CPU time 11.03 seconds
Started Jul 19 05:56:23 PM PDT 24
Finished Jul 19 05:56:36 PM PDT 24
Peak memory 201756 kb
Host smart-24c4ca6e-7a71-45db-9224-9ee76260261e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203735524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_
ctrl_same_csr_outstanding.2203735524
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.986754916
Short name T868
Test name
Test status
Simulation time 382435712 ps
CPU time 2.82 seconds
Started Jul 19 05:56:23 PM PDT 24
Finished Jul 19 05:56:29 PM PDT 24
Peak memory 201836 kb
Host smart-b12632d9-ba8d-490e-bea9-a26b1fc4b2c4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986754916 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.986754916
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.2045344104
Short name T325
Test name
Test status
Simulation time 8044605519 ps
CPU time 7.07 seconds
Started Jul 19 05:56:25 PM PDT 24
Finished Jul 19 05:56:35 PM PDT 24
Peak memory 201808 kb
Host smart-09322a0b-fe8e-4d7d-a118-b6b4f04c98a7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045344104 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_i
ntg_err.2045344104
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.2035436567
Short name T872
Test name
Test status
Simulation time 726711000 ps
CPU time 3.12 seconds
Started Jul 19 05:55:42 PM PDT 24
Finished Jul 19 05:55:46 PM PDT 24
Peak memory 201652 kb
Host smart-dc3e921c-c450-48a7-8e76-70ec86e34fad
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035436567 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alia
sing.2035436567
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.2267906029
Short name T113
Test name
Test status
Simulation time 52190625738 ps
CPU time 20.89 seconds
Started Jul 19 05:55:43 PM PDT 24
Finished Jul 19 05:56:05 PM PDT 24
Peak memory 201820 kb
Host smart-eee13d8b-7730-4ff0-ab9a-3081d6b5807a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267906029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_
bash.2267906029
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.1452609909
Short name T860
Test name
Test status
Simulation time 803660738 ps
CPU time 1.21 seconds
Started Jul 19 05:55:44 PM PDT 24
Finished Jul 19 05:55:46 PM PDT 24
Peak memory 201492 kb
Host smart-b630915b-3d4c-4955-8172-5e7fb51b6b6c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452609909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_r
eset.1452609909
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.2760955648
Short name T811
Test name
Test status
Simulation time 469727075 ps
CPU time 1.98 seconds
Started Jul 19 05:55:42 PM PDT 24
Finished Jul 19 05:55:45 PM PDT 24
Peak memory 201592 kb
Host smart-7c1489d7-c98f-4107-b72d-6f374b17ae0d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760955648 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.2760955648
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.314749894
Short name T102
Test name
Test status
Simulation time 582333383 ps
CPU time 1.14 seconds
Started Jul 19 05:55:42 PM PDT 24
Finished Jul 19 05:55:45 PM PDT 24
Peak memory 201448 kb
Host smart-3a246c1f-ebc7-46ac-9cae-c6575405d19a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314749894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.314749894
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.378425578
Short name T818
Test name
Test status
Simulation time 546110477 ps
CPU time 0.96 seconds
Started Jul 19 05:55:41 PM PDT 24
Finished Jul 19 05:55:42 PM PDT 24
Peak memory 201408 kb
Host smart-e16181ad-4871-48fa-9563-79c14a65c887
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378425578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.378425578
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.386948187
Short name T891
Test name
Test status
Simulation time 4315675079 ps
CPU time 2.12 seconds
Started Jul 19 05:55:42 PM PDT 24
Finished Jul 19 05:55:45 PM PDT 24
Peak memory 201768 kb
Host smart-7d85c306-4b41-46dc-986d-b20e9eb11cc1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386948187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ct
rl_same_csr_outstanding.386948187
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.765777919
Short name T826
Test name
Test status
Simulation time 408702911 ps
CPU time 3.37 seconds
Started Jul 19 05:55:41 PM PDT 24
Finished Jul 19 05:55:45 PM PDT 24
Peak memory 201832 kb
Host smart-5c0d7856-5138-428c-9c91-d91f48fe7007
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765777919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.765777919
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.3945671750
Short name T80
Test name
Test status
Simulation time 9190078387 ps
CPU time 13.56 seconds
Started Jul 19 05:55:42 PM PDT 24
Finished Jul 19 05:55:56 PM PDT 24
Peak memory 201776 kb
Host smart-e29d9255-f76c-4476-9330-e97ee653a6cd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945671750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_in
tg_err.3945671750
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.2589232389
Short name T876
Test name
Test status
Simulation time 319503954 ps
CPU time 0.78 seconds
Started Jul 19 05:56:22 PM PDT 24
Finished Jul 19 05:56:25 PM PDT 24
Peak memory 201336 kb
Host smart-ba76f114-8bf4-46d3-8860-51669a2736be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589232389 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.2589232389
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.2663452513
Short name T795
Test name
Test status
Simulation time 474181347 ps
CPU time 1.18 seconds
Started Jul 19 05:56:24 PM PDT 24
Finished Jul 19 05:56:27 PM PDT 24
Peak memory 201436 kb
Host smart-18e285c0-e7bd-4cb9-be52-da4902c3714a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663452513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.2663452513
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.1505847272
Short name T835
Test name
Test status
Simulation time 325508120 ps
CPU time 1.32 seconds
Started Jul 19 05:56:25 PM PDT 24
Finished Jul 19 05:56:28 PM PDT 24
Peak memory 201460 kb
Host smart-9cb140c1-3f2f-48a0-9117-5ce9ad0ab99d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505847272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.1505847272
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.3220088753
Short name T856
Test name
Test status
Simulation time 419893176 ps
CPU time 1.58 seconds
Started Jul 19 05:56:21 PM PDT 24
Finished Jul 19 05:56:24 PM PDT 24
Peak memory 201392 kb
Host smart-a49744b9-edb0-4a87-968f-4eaa1ff7b501
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220088753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.3220088753
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.204494119
Short name T899
Test name
Test status
Simulation time 339316397 ps
CPU time 0.88 seconds
Started Jul 19 05:56:21 PM PDT 24
Finished Jul 19 05:56:24 PM PDT 24
Peak memory 201436 kb
Host smart-5abf2fee-5203-45f7-9205-877893b758be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204494119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.204494119
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.645016809
Short name T825
Test name
Test status
Simulation time 525394623 ps
CPU time 0.77 seconds
Started Jul 19 05:56:22 PM PDT 24
Finished Jul 19 05:56:25 PM PDT 24
Peak memory 201440 kb
Host smart-2fac12a2-d8e1-454d-b639-8b042b4355a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645016809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.645016809
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.1039979566
Short name T792
Test name
Test status
Simulation time 570231511 ps
CPU time 0.96 seconds
Started Jul 19 05:56:21 PM PDT 24
Finished Jul 19 05:56:23 PM PDT 24
Peak memory 201408 kb
Host smart-8ef44aea-58df-48fa-8a4f-11a854c59494
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039979566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.1039979566
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.2542639916
Short name T902
Test name
Test status
Simulation time 397238156 ps
CPU time 0.85 seconds
Started Jul 19 05:56:24 PM PDT 24
Finished Jul 19 05:56:28 PM PDT 24
Peak memory 200760 kb
Host smart-962cbc19-c596-4f94-aa20-27fc13fa4556
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542639916 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.2542639916
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.1320654354
Short name T806
Test name
Test status
Simulation time 281388495 ps
CPU time 1.3 seconds
Started Jul 19 05:56:22 PM PDT 24
Finished Jul 19 05:56:25 PM PDT 24
Peak memory 201476 kb
Host smart-7ec4812c-3139-4e7b-822a-af41e613f9b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320654354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.1320654354
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.2339880875
Short name T912
Test name
Test status
Simulation time 564924446 ps
CPU time 0.93 seconds
Started Jul 19 05:56:22 PM PDT 24
Finished Jul 19 05:56:26 PM PDT 24
Peak memory 201428 kb
Host smart-7a410c28-d543-4fa2-8b90-421195868e5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339880875 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.2339880875
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.397308438
Short name T877
Test name
Test status
Simulation time 1252538362 ps
CPU time 2.4 seconds
Started Jul 19 05:55:44 PM PDT 24
Finished Jul 19 05:55:48 PM PDT 24
Peak memory 201684 kb
Host smart-bfda2599-98c9-4847-a079-78c0a8ca3291
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397308438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alias
ing.397308438
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.1435838912
Short name T813
Test name
Test status
Simulation time 52924812400 ps
CPU time 28.81 seconds
Started Jul 19 05:55:42 PM PDT 24
Finished Jul 19 05:56:12 PM PDT 24
Peak memory 201736 kb
Host smart-411ff907-f81d-42de-b5d8-7e08373de7e3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435838912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_
bash.1435838912
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.4144916455
Short name T799
Test name
Test status
Simulation time 883315744 ps
CPU time 1.21 seconds
Started Jul 19 05:55:41 PM PDT 24
Finished Jul 19 05:55:43 PM PDT 24
Peak memory 201412 kb
Host smart-0066a176-1d47-4477-80cb-764f02d9442e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144916455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_r
eset.4144916455
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.2459502972
Short name T827
Test name
Test status
Simulation time 652231996 ps
CPU time 2.45 seconds
Started Jul 19 05:55:42 PM PDT 24
Finished Jul 19 05:55:46 PM PDT 24
Peak memory 201560 kb
Host smart-b48d41a0-4581-40fd-af72-9af16c7aa8d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459502972 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.2459502972
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.395981800
Short name T107
Test name
Test status
Simulation time 578066075 ps
CPU time 2.13 seconds
Started Jul 19 05:55:42 PM PDT 24
Finished Jul 19 05:55:45 PM PDT 24
Peak memory 201440 kb
Host smart-5a75dbcc-ee03-4ff4-9491-187db0033764
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395981800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.395981800
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.3437215755
Short name T798
Test name
Test status
Simulation time 324351906 ps
CPU time 1.01 seconds
Started Jul 19 05:55:41 PM PDT 24
Finished Jul 19 05:55:43 PM PDT 24
Peak memory 201432 kb
Host smart-548f3a85-a975-4922-802a-4b2b78612941
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437215755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.3437215755
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.564077169
Short name T109
Test name
Test status
Simulation time 4482773501 ps
CPU time 10.76 seconds
Started Jul 19 05:55:43 PM PDT 24
Finished Jul 19 05:55:56 PM PDT 24
Peak memory 201784 kb
Host smart-54446c5b-800b-4208-86cc-90b075487412
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564077169 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ct
rl_same_csr_outstanding.564077169
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.487815311
Short name T888
Test name
Test status
Simulation time 328380763 ps
CPU time 2.31 seconds
Started Jul 19 05:55:42 PM PDT 24
Finished Jul 19 05:55:46 PM PDT 24
Peak memory 201732 kb
Host smart-6e100034-99be-43d0-a3ef-9661c1667784
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487815311 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.487815311
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.3409420438
Short name T49
Test name
Test status
Simulation time 8016612929 ps
CPU time 22.2 seconds
Started Jul 19 05:55:41 PM PDT 24
Finished Jul 19 05:56:04 PM PDT 24
Peak memory 201840 kb
Host smart-18011e4b-f21e-419f-a158-8399f6d2d671
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409420438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_in
tg_err.3409420438
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.2130983834
Short name T893
Test name
Test status
Simulation time 410196730 ps
CPU time 1.07 seconds
Started Jul 19 05:56:21 PM PDT 24
Finished Jul 19 05:56:23 PM PDT 24
Peak memory 201464 kb
Host smart-f9749d7d-3fa9-4db7-849f-0f8bc85a274d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130983834 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.2130983834
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.1404275204
Short name T794
Test name
Test status
Simulation time 334575897 ps
CPU time 0.73 seconds
Started Jul 19 05:56:24 PM PDT 24
Finished Jul 19 05:56:27 PM PDT 24
Peak memory 201408 kb
Host smart-5a333b33-3cbe-4303-8b2a-3e04e4dededb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404275204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.1404275204
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.1154888192
Short name T800
Test name
Test status
Simulation time 508938669 ps
CPU time 0.92 seconds
Started Jul 19 05:56:23 PM PDT 24
Finished Jul 19 05:56:27 PM PDT 24
Peak memory 201452 kb
Host smart-9e3d3afc-2fdd-4dc3-8607-d2c95fc99ead
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154888192 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.1154888192
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.3211892206
Short name T838
Test name
Test status
Simulation time 543192431 ps
CPU time 0.73 seconds
Started Jul 19 05:56:24 PM PDT 24
Finished Jul 19 05:56:28 PM PDT 24
Peak memory 201560 kb
Host smart-3c343481-22fd-48eb-a686-57fe62b8f7d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211892206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.3211892206
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.262057017
Short name T791
Test name
Test status
Simulation time 448081629 ps
CPU time 1.65 seconds
Started Jul 19 05:56:21 PM PDT 24
Finished Jul 19 05:56:24 PM PDT 24
Peak memory 201408 kb
Host smart-73ed502f-bc83-4d19-a0d1-be6a39d59368
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262057017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.262057017
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.3061354621
Short name T894
Test name
Test status
Simulation time 324093332 ps
CPU time 0.95 seconds
Started Jul 19 05:56:22 PM PDT 24
Finished Jul 19 05:56:24 PM PDT 24
Peak memory 201448 kb
Host smart-8dd420d0-16d9-4675-b72b-a3704078e647
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061354621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.3061354621
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.1044264846
Short name T869
Test name
Test status
Simulation time 507370095 ps
CPU time 0.82 seconds
Started Jul 19 05:56:24 PM PDT 24
Finished Jul 19 05:56:27 PM PDT 24
Peak memory 201452 kb
Host smart-33708ffd-0f83-475c-9ab1-957d76be909a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044264846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.1044264846
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.963142686
Short name T796
Test name
Test status
Simulation time 319649006 ps
CPU time 0.79 seconds
Started Jul 19 05:56:23 PM PDT 24
Finished Jul 19 05:56:26 PM PDT 24
Peak memory 201432 kb
Host smart-e902d0ac-9f59-4c17-9d9a-833542eeac7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963142686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.963142686
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.3119960124
Short name T863
Test name
Test status
Simulation time 470489349 ps
CPU time 1.68 seconds
Started Jul 19 05:56:22 PM PDT 24
Finished Jul 19 05:56:26 PM PDT 24
Peak memory 201440 kb
Host smart-57e78566-6c08-4e4b-a9df-76c7d75d5774
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119960124 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.3119960124
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.1120652591
Short name T846
Test name
Test status
Simulation time 476400769 ps
CPU time 1.79 seconds
Started Jul 19 05:56:22 PM PDT 24
Finished Jul 19 05:56:26 PM PDT 24
Peak memory 201420 kb
Host smart-ee1708e0-55ed-4dba-b0ff-93c980a4009e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120652591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.1120652591
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.2388787170
Short name T917
Test name
Test status
Simulation time 980242892 ps
CPU time 3.6 seconds
Started Jul 19 05:55:49 PM PDT 24
Finished Jul 19 05:55:54 PM PDT 24
Peak memory 201652 kb
Host smart-abfb5a8e-9df1-4471-a1f1-db353bc9fe64
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388787170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alia
sing.2388787170
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.1567963082
Short name T48
Test name
Test status
Simulation time 26229036309 ps
CPU time 17.33 seconds
Started Jul 19 05:55:52 PM PDT 24
Finished Jul 19 05:56:10 PM PDT 24
Peak memory 201896 kb
Host smart-26e63fff-d18e-4dd9-b4de-652e9338251b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567963082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_
bash.1567963082
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.1412161259
Short name T98
Test name
Test status
Simulation time 845057475 ps
CPU time 1.69 seconds
Started Jul 19 05:55:52 PM PDT 24
Finished Jul 19 05:55:54 PM PDT 24
Peak memory 201504 kb
Host smart-0e81a458-dfad-4976-8724-9fae8bbdbca7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412161259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_r
eset.1412161259
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.1310989077
Short name T882
Test name
Test status
Simulation time 578384270 ps
CPU time 1.14 seconds
Started Jul 19 05:55:53 PM PDT 24
Finished Jul 19 05:55:55 PM PDT 24
Peak memory 201744 kb
Host smart-93ce48c8-9f4e-409f-9454-7a361f46104f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310989077 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.1310989077
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.2547123769
Short name T101
Test name
Test status
Simulation time 402938461 ps
CPU time 0.84 seconds
Started Jul 19 05:55:51 PM PDT 24
Finished Jul 19 05:55:53 PM PDT 24
Peak memory 201412 kb
Host smart-28669758-e632-4beb-9801-07f94ee49aeb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547123769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.2547123769
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.1763525525
Short name T801
Test name
Test status
Simulation time 349915389 ps
CPU time 0.84 seconds
Started Jul 19 05:55:48 PM PDT 24
Finished Jul 19 05:55:49 PM PDT 24
Peak memory 201444 kb
Host smart-07219072-2e04-4e44-bb87-b56909565091
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763525525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.1763525525
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.1580447991
Short name T908
Test name
Test status
Simulation time 2960824196 ps
CPU time 1.43 seconds
Started Jul 19 05:55:57 PM PDT 24
Finished Jul 19 05:55:59 PM PDT 24
Peak memory 201592 kb
Host smart-de9b0e5f-0a04-4375-8487-f4de4bd0b580
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580447991 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_c
trl_same_csr_outstanding.1580447991
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.2760509555
Short name T855
Test name
Test status
Simulation time 566181069 ps
CPU time 3.08 seconds
Started Jul 19 05:55:49 PM PDT 24
Finished Jul 19 05:55:53 PM PDT 24
Peak memory 201736 kb
Host smart-26472e60-81ed-4958-9503-fac615bb7cc4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760509555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.2760509555
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.4264781027
Short name T900
Test name
Test status
Simulation time 4619675324 ps
CPU time 11.34 seconds
Started Jul 19 05:55:52 PM PDT 24
Finished Jul 19 05:56:04 PM PDT 24
Peak memory 202016 kb
Host smart-b122588b-8c18-4fa1-bb38-0f8c32c3c2c4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264781027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_in
tg_err.4264781027
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.1871869394
Short name T828
Test name
Test status
Simulation time 416444956 ps
CPU time 0.89 seconds
Started Jul 19 05:56:26 PM PDT 24
Finished Jul 19 05:56:29 PM PDT 24
Peak memory 201428 kb
Host smart-c9e2fea6-3ef2-4110-b36b-85ecabd7febf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871869394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.1871869394
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.620042109
Short name T808
Test name
Test status
Simulation time 450879620 ps
CPU time 1.66 seconds
Started Jul 19 05:56:24 PM PDT 24
Finished Jul 19 05:56:28 PM PDT 24
Peak memory 201440 kb
Host smart-70545bd6-3a9a-4214-895f-d83f0a032121
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620042109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.620042109
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.1389819474
Short name T802
Test name
Test status
Simulation time 499507435 ps
CPU time 0.93 seconds
Started Jul 19 05:56:25 PM PDT 24
Finished Jul 19 05:56:28 PM PDT 24
Peak memory 201404 kb
Host smart-390f4069-076a-45ad-b250-bed3f5666ce7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389819474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.1389819474
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.3213489323
Short name T823
Test name
Test status
Simulation time 363765781 ps
CPU time 1.11 seconds
Started Jul 19 05:56:23 PM PDT 24
Finished Jul 19 05:56:27 PM PDT 24
Peak memory 201412 kb
Host smart-91f5c117-c363-4f7a-952f-a04a946603c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213489323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.3213489323
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.1028327935
Short name T790
Test name
Test status
Simulation time 362597511 ps
CPU time 0.75 seconds
Started Jul 19 05:56:21 PM PDT 24
Finished Jul 19 05:56:23 PM PDT 24
Peak memory 201452 kb
Host smart-736b3985-044b-4370-85a3-ccba14b6273e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028327935 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.1028327935
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.2156766077
Short name T815
Test name
Test status
Simulation time 586980241 ps
CPU time 0.8 seconds
Started Jul 19 05:56:24 PM PDT 24
Finished Jul 19 05:56:28 PM PDT 24
Peak memory 201408 kb
Host smart-e3284b79-7f17-49dc-96e8-539ae98762b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156766077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.2156766077
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.862917303
Short name T807
Test name
Test status
Simulation time 384472352 ps
CPU time 1.48 seconds
Started Jul 19 05:56:23 PM PDT 24
Finished Jul 19 05:56:28 PM PDT 24
Peak memory 201456 kb
Host smart-3c79681f-4e18-42f6-b831-4193275765c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862917303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.862917303
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.177794915
Short name T885
Test name
Test status
Simulation time 357970968 ps
CPU time 0.98 seconds
Started Jul 19 05:56:23 PM PDT 24
Finished Jul 19 05:56:27 PM PDT 24
Peak memory 201436 kb
Host smart-dbf01b72-8b57-4de5-8b0c-e30c78f1b7b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177794915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.177794915
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.2734876782
Short name T817
Test name
Test status
Simulation time 423960941 ps
CPU time 1.02 seconds
Started Jul 19 05:56:22 PM PDT 24
Finished Jul 19 05:56:25 PM PDT 24
Peak memory 201428 kb
Host smart-78ef7c86-2591-4665-97f0-eb01875732ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734876782 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.2734876782
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.3220295292
Short name T834
Test name
Test status
Simulation time 424710445 ps
CPU time 1.55 seconds
Started Jul 19 05:56:23 PM PDT 24
Finished Jul 19 05:56:27 PM PDT 24
Peak memory 201416 kb
Host smart-b435f500-8c8a-4dc0-9845-dc239f1fdd83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220295292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.3220295292
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.2354669856
Short name T79
Test name
Test status
Simulation time 436369227 ps
CPU time 1.18 seconds
Started Jul 19 05:55:57 PM PDT 24
Finished Jul 19 05:55:59 PM PDT 24
Peak memory 201588 kb
Host smart-ae870333-bdb6-458b-8cf1-25489d97a7e6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354669856 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.2354669856
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.1767830825
Short name T112
Test name
Test status
Simulation time 379157942 ps
CPU time 1.54 seconds
Started Jul 19 05:55:51 PM PDT 24
Finished Jul 19 05:55:53 PM PDT 24
Peak memory 201412 kb
Host smart-d428be98-7322-4765-a020-372ffc9c15b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767830825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.1767830825
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.911917002
Short name T907
Test name
Test status
Simulation time 337265554 ps
CPU time 1.32 seconds
Started Jul 19 05:55:51 PM PDT 24
Finished Jul 19 05:55:53 PM PDT 24
Peak memory 201432 kb
Host smart-963771ed-313d-4ca6-96cc-01fd4027abdc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911917002 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.911917002
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.2459324947
Short name T901
Test name
Test status
Simulation time 2486263490 ps
CPU time 7.85 seconds
Started Jul 19 05:55:50 PM PDT 24
Finished Jul 19 05:55:59 PM PDT 24
Peak memory 201560 kb
Host smart-d49ec2b8-48fa-4302-893d-0087b5e54eed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459324947 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_c
trl_same_csr_outstanding.2459324947
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.3338571369
Short name T59
Test name
Test status
Simulation time 626811387 ps
CPU time 3.77 seconds
Started Jul 19 05:55:50 PM PDT 24
Finished Jul 19 05:55:55 PM PDT 24
Peak memory 211064 kb
Host smart-ec2074a5-5b11-4692-a8a3-c0e776eb8df5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338571369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.3338571369
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.2630316433
Short name T903
Test name
Test status
Simulation time 4437947356 ps
CPU time 12.49 seconds
Started Jul 19 05:55:51 PM PDT 24
Finished Jul 19 05:56:04 PM PDT 24
Peak memory 201788 kb
Host smart-fbf89474-ab66-45d1-8946-976e68d14324
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630316433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_in
tg_err.2630316433
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.1993960689
Short name T824
Test name
Test status
Simulation time 608219438 ps
CPU time 1.02 seconds
Started Jul 19 05:55:50 PM PDT 24
Finished Jul 19 05:55:52 PM PDT 24
Peak memory 201536 kb
Host smart-a2ead22c-cdb1-4cc5-b52a-1ff97527cb69
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993960689 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.1993960689
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.815694404
Short name T871
Test name
Test status
Simulation time 436239780 ps
CPU time 1.24 seconds
Started Jul 19 05:55:49 PM PDT 24
Finished Jul 19 05:55:50 PM PDT 24
Peak memory 201444 kb
Host smart-7ffcf371-0977-4825-bfd7-73a601b24189
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815694404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.815694404
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.2127963337
Short name T819
Test name
Test status
Simulation time 521477397 ps
CPU time 1.89 seconds
Started Jul 19 05:55:52 PM PDT 24
Finished Jul 19 05:55:54 PM PDT 24
Peak memory 201484 kb
Host smart-85ae0451-a5ae-49e4-a4ab-abea193ebd87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127963337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.2127963337
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.2373293855
Short name T865
Test name
Test status
Simulation time 2910548019 ps
CPU time 6.1 seconds
Started Jul 19 05:55:56 PM PDT 24
Finished Jul 19 05:56:03 PM PDT 24
Peak memory 201592 kb
Host smart-146d832d-c766-485b-96e1-0a039b8941f8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373293855 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_c
trl_same_csr_outstanding.2373293855
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.2311180430
Short name T829
Test name
Test status
Simulation time 536819852 ps
CPU time 2.62 seconds
Started Jul 19 05:55:53 PM PDT 24
Finished Jul 19 05:55:56 PM PDT 24
Peak memory 209928 kb
Host smart-319b0d7d-5ad4-47a3-960c-c7474b4360d5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311180430 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.2311180430
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.4082350265
Short name T816
Test name
Test status
Simulation time 4505748597 ps
CPU time 12.43 seconds
Started Jul 19 05:55:50 PM PDT 24
Finished Jul 19 05:56:03 PM PDT 24
Peak memory 201736 kb
Host smart-0202ac4b-990d-4b09-996e-78ab88c5a8b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082350265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_in
tg_err.4082350265
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.531712497
Short name T905
Test name
Test status
Simulation time 674728747 ps
CPU time 1.78 seconds
Started Jul 19 05:56:06 PM PDT 24
Finished Jul 19 05:56:09 PM PDT 24
Peak memory 201560 kb
Host smart-723eea29-23ab-44f1-9031-27167165fc44
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531712497 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.531712497
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.2667335473
Short name T849
Test name
Test status
Simulation time 347459094 ps
CPU time 1.49 seconds
Started Jul 19 05:56:06 PM PDT 24
Finished Jul 19 05:56:09 PM PDT 24
Peak memory 201436 kb
Host smart-49feec59-ff50-40cb-8215-e9f37a8bd788
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667335473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.2667335473
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.2059532118
Short name T873
Test name
Test status
Simulation time 414510658 ps
CPU time 1.7 seconds
Started Jul 19 05:55:57 PM PDT 24
Finished Jul 19 05:56:00 PM PDT 24
Peak memory 201480 kb
Host smart-fdfbf203-a646-4955-a61d-3c9d8a89ebd3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059532118 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.2059532118
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.3315747593
Short name T839
Test name
Test status
Simulation time 2392317163 ps
CPU time 2.27 seconds
Started Jul 19 05:55:59 PM PDT 24
Finished Jul 19 05:56:02 PM PDT 24
Peak memory 201592 kb
Host smart-b5c2cf4c-54bc-4e6e-bbc2-86ee5623e364
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315747593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_c
trl_same_csr_outstanding.3315747593
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.4098342716
Short name T832
Test name
Test status
Simulation time 380308439 ps
CPU time 1.91 seconds
Started Jul 19 05:55:51 PM PDT 24
Finished Jul 19 05:55:53 PM PDT 24
Peak memory 218108 kb
Host smart-bf05740c-3ac6-464e-b232-07372adfbc06
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098342716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.4098342716
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.1819625965
Short name T810
Test name
Test status
Simulation time 371054434 ps
CPU time 1.68 seconds
Started Jul 19 05:55:56 PM PDT 24
Finished Jul 19 05:55:59 PM PDT 24
Peak memory 201560 kb
Host smart-4a864b38-5e85-4798-9f91-16d267ad3d0e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819625965 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.1819625965
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.626759672
Short name T111
Test name
Test status
Simulation time 517046344 ps
CPU time 0.91 seconds
Started Jul 19 05:56:05 PM PDT 24
Finished Jul 19 05:56:08 PM PDT 24
Peak memory 201436 kb
Host smart-48447b8f-940e-49bc-93f1-623ac84421c1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626759672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.626759672
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.92329599
Short name T820
Test name
Test status
Simulation time 290872556 ps
CPU time 1.24 seconds
Started Jul 19 05:55:56 PM PDT 24
Finished Jul 19 05:55:59 PM PDT 24
Peak memory 201484 kb
Host smart-99919ea4-e3de-4d52-bfa9-e41708085466
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92329599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.92329599
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.3454887590
Short name T897
Test name
Test status
Simulation time 2265765842 ps
CPU time 3.34 seconds
Started Jul 19 05:55:56 PM PDT 24
Finished Jul 19 05:56:01 PM PDT 24
Peak memory 201568 kb
Host smart-64ff9ca2-4d95-4d03-85cc-f2dfbe27b595
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454887590 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_c
trl_same_csr_outstanding.3454887590
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.2646830114
Short name T814
Test name
Test status
Simulation time 1616203163 ps
CPU time 2.34 seconds
Started Jul 19 05:55:59 PM PDT 24
Finished Jul 19 05:56:02 PM PDT 24
Peak memory 201836 kb
Host smart-8ae4bd5e-bc97-4405-96f3-50cf8da67182
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646830114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.2646830114
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.3893205521
Short name T911
Test name
Test status
Simulation time 4273113914 ps
CPU time 11.73 seconds
Started Jul 19 05:55:55 PM PDT 24
Finished Jul 19 05:56:08 PM PDT 24
Peak memory 201868 kb
Host smart-f7d78a3d-fe00-4229-b8cb-3d0d1bb7951f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893205521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_in
tg_err.3893205521
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.4251660579
Short name T904
Test name
Test status
Simulation time 432468855 ps
CPU time 1.95 seconds
Started Jul 19 05:55:57 PM PDT 24
Finished Jul 19 05:56:00 PM PDT 24
Peak memory 201564 kb
Host smart-bebcaedd-5341-4869-ba45-83213223f739
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251660579 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.4251660579
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.947637855
Short name T880
Test name
Test status
Simulation time 513462912 ps
CPU time 1.83 seconds
Started Jul 19 05:56:05 PM PDT 24
Finished Jul 19 05:56:08 PM PDT 24
Peak memory 201436 kb
Host smart-0c2594fd-6e1d-4f82-b1a2-7b04022d8f44
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947637855 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.947637855
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.2314818498
Short name T847
Test name
Test status
Simulation time 433888638 ps
CPU time 0.93 seconds
Started Jul 19 05:55:58 PM PDT 24
Finished Jul 19 05:56:00 PM PDT 24
Peak memory 201648 kb
Host smart-3a43e548-3d37-4f83-82d3-32158bc62893
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314818498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.2314818498
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.2045988209
Short name T914
Test name
Test status
Simulation time 2098011624 ps
CPU time 2.93 seconds
Started Jul 19 05:55:57 PM PDT 24
Finished Jul 19 05:56:01 PM PDT 24
Peak memory 201496 kb
Host smart-79085f35-0785-45b9-bf0d-0650e26b5055
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045988209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_c
trl_same_csr_outstanding.2045988209
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.2964196171
Short name T852
Test name
Test status
Simulation time 672364191 ps
CPU time 1.88 seconds
Started Jul 19 05:55:56 PM PDT 24
Finished Jul 19 05:55:59 PM PDT 24
Peak memory 201848 kb
Host smart-e9a3a104-00e1-4f1a-8445-b396a0b3b579
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964196171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.2964196171
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.2538344218
Short name T809
Test name
Test status
Simulation time 8718212335 ps
CPU time 5.55 seconds
Started Jul 19 05:56:01 PM PDT 24
Finished Jul 19 05:56:07 PM PDT 24
Peak memory 201784 kb
Host smart-c86e08dd-d892-4321-818e-dc8dd1165b16
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538344218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_in
tg_err.2538344218
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.1385877398
Short name T636
Test name
Test status
Simulation time 330053141 ps
CPU time 1.48 seconds
Started Jul 19 07:05:27 PM PDT 24
Finished Jul 19 07:05:30 PM PDT 24
Peak memory 201528 kb
Host smart-6ca94933-c2a8-4680-94d1-e934d49780ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385877398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.1385877398
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.3123707790
Short name T204
Test name
Test status
Simulation time 190702764903 ps
CPU time 92.79 seconds
Started Jul 19 07:04:42 PM PDT 24
Finished Jul 19 07:06:19 PM PDT 24
Peak memory 201800 kb
Host smart-cb0aebc8-5f31-478a-884e-f3a0b5ec0809
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123707790 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gati
ng.3123707790
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.1711442757
Short name T288
Test name
Test status
Simulation time 333116211978 ps
CPU time 766.11 seconds
Started Jul 19 07:04:35 PM PDT 24
Finished Jul 19 07:17:26 PM PDT 24
Peak memory 201760 kb
Host smart-97ecb138-6b8e-4b17-92ad-9aa99fc1d825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711442757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.1711442757
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.4285748831
Short name T605
Test name
Test status
Simulation time 498034450539 ps
CPU time 109.91 seconds
Started Jul 19 07:04:51 PM PDT 24
Finished Jul 19 07:06:42 PM PDT 24
Peak memory 201748 kb
Host smart-5e476ab9-1b1e-4412-8a55-55b4ab8b1aa7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285748831 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrup
t_fixed.4285748831
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.1692244524
Short name T146
Test name
Test status
Simulation time 328460332429 ps
CPU time 80.78 seconds
Started Jul 19 07:04:30 PM PDT 24
Finished Jul 19 07:05:58 PM PDT 24
Peak memory 201688 kb
Host smart-b98e5b29-5c92-4357-9d99-e88afb3ad346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692244524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.1692244524
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.2847562641
Short name T371
Test name
Test status
Simulation time 322540526256 ps
CPU time 338.07 seconds
Started Jul 19 07:04:34 PM PDT 24
Finished Jul 19 07:10:18 PM PDT 24
Peak memory 201840 kb
Host smart-9f84696c-94fa-4436-9790-33bc9f955857
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847562641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixe
d.2847562641
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.62352281
Short name T715
Test name
Test status
Simulation time 422453449298 ps
CPU time 223.13 seconds
Started Jul 19 07:04:45 PM PDT 24
Finished Jul 19 07:08:31 PM PDT 24
Peak memory 201776 kb
Host smart-74422c71-9fbe-4b96-9231-7f9da5466f00
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62352281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.ad
c_ctrl_filters_wakeup_fixed.62352281
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.3617745317
Short name T706
Test name
Test status
Simulation time 86860699170 ps
CPU time 291.77 seconds
Started Jul 19 07:05:07 PM PDT 24
Finished Jul 19 07:10:00 PM PDT 24
Peak memory 202124 kb
Host smart-5a9a619d-d9b9-4140-b867-2775578c0fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617745317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.3617745317
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.2833949166
Short name T638
Test name
Test status
Simulation time 25814262222 ps
CPU time 6.56 seconds
Started Jul 19 07:04:50 PM PDT 24
Finished Jul 19 07:04:58 PM PDT 24
Peak memory 201740 kb
Host smart-7031781a-5fa6-4be6-a4d4-4cafb74be8c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833949166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.2833949166
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.758398797
Short name T342
Test name
Test status
Simulation time 4883314358 ps
CPU time 12.66 seconds
Started Jul 19 07:04:55 PM PDT 24
Finished Jul 19 07:05:09 PM PDT 24
Peak memory 201612 kb
Host smart-866f1fed-3222-48b9-ac06-0f14c7a2d5da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758398797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.758398797
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.1738137729
Short name T56
Test name
Test status
Simulation time 8269416986 ps
CPU time 5.6 seconds
Started Jul 19 07:05:26 PM PDT 24
Finished Jul 19 07:05:34 PM PDT 24
Peak memory 218324 kb
Host smart-199d211c-abcd-4360-b17f-e8da00b4b080
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738137729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.1738137729
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.1505049674
Short name T504
Test name
Test status
Simulation time 5706343697 ps
CPU time 4.47 seconds
Started Jul 19 07:04:18 PM PDT 24
Finished Jul 19 07:04:29 PM PDT 24
Peak memory 201672 kb
Host smart-fed6cb4a-29d8-4f3f-9325-57ce727d67e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505049674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.1505049674
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.1169602706
Short name T180
Test name
Test status
Simulation time 411383027197 ps
CPU time 919.86 seconds
Started Jul 19 07:05:18 PM PDT 24
Finished Jul 19 07:20:39 PM PDT 24
Peak memory 210376 kb
Host smart-cf50a27f-612f-4c97-a798-b3fd62f3d0f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169602706 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.
1169602706
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.4151429520
Short name T680
Test name
Test status
Simulation time 506190699 ps
CPU time 0.98 seconds
Started Jul 19 07:06:04 PM PDT 24
Finished Jul 19 07:06:06 PM PDT 24
Peak memory 201568 kb
Host smart-7c2f252e-2488-44c9-a272-36f8a20080cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151429520 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.4151429520
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.2518461984
Short name T755
Test name
Test status
Simulation time 194251092962 ps
CPU time 414.15 seconds
Started Jul 19 07:05:43 PM PDT 24
Finished Jul 19 07:12:38 PM PDT 24
Peak memory 201760 kb
Host smart-21708d7f-3258-4fae-8bd5-18432ed5b8fd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518461984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gati
ng.2518461984
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.2755018940
Short name T243
Test name
Test status
Simulation time 181930053080 ps
CPU time 417.47 seconds
Started Jul 19 07:05:52 PM PDT 24
Finished Jul 19 07:12:50 PM PDT 24
Peak memory 201836 kb
Host smart-479c9854-fd7f-48ce-82a2-d8894dd2ef6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755018940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.2755018940
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.891301815
Short name T644
Test name
Test status
Simulation time 497274839926 ps
CPU time 1074.97 seconds
Started Jul 19 07:05:34 PM PDT 24
Finished Jul 19 07:23:31 PM PDT 24
Peak memory 201724 kb
Host smart-994ea42a-4a7f-4d41-bc65-599c1fa98563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891301815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.891301815
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.343119157
Short name T360
Test name
Test status
Simulation time 499340885684 ps
CPU time 1306.63 seconds
Started Jul 19 07:06:55 PM PDT 24
Finished Jul 19 07:28:44 PM PDT 24
Peak memory 201696 kb
Host smart-5a2eeda7-c637-41e9-a682-eea242003628
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=343119157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt
_fixed.343119157
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.2239801290
Short name T472
Test name
Test status
Simulation time 163528489432 ps
CPU time 95.22 seconds
Started Jul 19 07:05:31 PM PDT 24
Finished Jul 19 07:07:07 PM PDT 24
Peak memory 201744 kb
Host smart-a56b2b19-2ecd-4c12-8441-25ada72f1796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239801290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.2239801290
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.288730103
Short name T645
Test name
Test status
Simulation time 327334114194 ps
CPU time 300.86 seconds
Started Jul 19 07:05:29 PM PDT 24
Finished Jul 19 07:10:31 PM PDT 24
Peak memory 201716 kb
Host smart-23368790-bb6b-4803-bb38-30ac08889919
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=288730103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixed
.288730103
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.233317140
Short name T546
Test name
Test status
Simulation time 202801795865 ps
CPU time 512.87 seconds
Started Jul 19 07:05:46 PM PDT 24
Finished Jul 19 07:14:19 PM PDT 24
Peak memory 201728 kb
Host smart-82a38d50-4ef2-42a4-b399-aee724ce90a2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233317140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.a
dc_ctrl_filters_wakeup_fixed.233317140
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.3595633166
Short name T598
Test name
Test status
Simulation time 82766511536 ps
CPU time 487.74 seconds
Started Jul 19 07:05:55 PM PDT 24
Finished Jul 19 07:14:03 PM PDT 24
Peak memory 202168 kb
Host smart-02496e04-2d50-44b5-a94d-2708047b4917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595633166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.3595633166
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.2959147633
Short name T787
Test name
Test status
Simulation time 39180663049 ps
CPU time 16.01 seconds
Started Jul 19 07:05:52 PM PDT 24
Finished Jul 19 07:06:09 PM PDT 24
Peak memory 201744 kb
Host smart-65318220-5433-4999-adda-e41fc20593cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959147633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.2959147633
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.1153066503
Short name T362
Test name
Test status
Simulation time 2900665816 ps
CPU time 7.07 seconds
Started Jul 19 07:05:51 PM PDT 24
Finished Jul 19 07:05:59 PM PDT 24
Peak memory 201620 kb
Host smart-16a2e620-34b9-4af9-84c8-09c3b5952c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153066503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.1153066503
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.1822797754
Short name T55
Test name
Test status
Simulation time 4345955063 ps
CPU time 3.78 seconds
Started Jul 19 07:05:57 PM PDT 24
Finished Jul 19 07:06:02 PM PDT 24
Peak memory 217200 kb
Host smart-2ce57d3e-e250-4c98-857f-c03e6ffacda1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822797754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.1822797754
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.1417991414
Short name T456
Test name
Test status
Simulation time 5641599513 ps
CPU time 13.46 seconds
Started Jul 19 07:05:27 PM PDT 24
Finished Jul 19 07:05:42 PM PDT 24
Peak memory 201584 kb
Host smart-c1af8f1d-08b7-4e63-9960-7743e3a73faf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417991414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.1417991414
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.3583728351
Short name T444
Test name
Test status
Simulation time 365410892 ps
CPU time 0.81 seconds
Started Jul 19 07:09:54 PM PDT 24
Finished Jul 19 07:09:58 PM PDT 24
Peak memory 201520 kb
Host smart-a910fdcd-f7ef-4dbf-9986-f915179aec28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583728351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.3583728351
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.2120939616
Short name T264
Test name
Test status
Simulation time 339680812603 ps
CPU time 209.83 seconds
Started Jul 19 07:09:34 PM PDT 24
Finished Jul 19 07:13:15 PM PDT 24
Peak memory 201728 kb
Host smart-7747e800-cfad-41ec-aefd-35d48168a0d3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120939616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gat
ing.2120939616
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.261252207
Short name T471
Test name
Test status
Simulation time 170636584005 ps
CPU time 229.02 seconds
Started Jul 19 07:09:41 PM PDT 24
Finished Jul 19 07:13:38 PM PDT 24
Peak memory 201748 kb
Host smart-152b25ee-cdef-4099-9a13-4a4acf1fa53b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261252207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.261252207
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.3066875030
Short name T132
Test name
Test status
Simulation time 325830305406 ps
CPU time 361.87 seconds
Started Jul 19 07:09:33 PM PDT 24
Finished Jul 19 07:15:46 PM PDT 24
Peak memory 201748 kb
Host smart-de298add-1b3e-4f37-9d62-b11c2eb91189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066875030 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.3066875030
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.389360607
Short name T417
Test name
Test status
Simulation time 172330490697 ps
CPU time 377.46 seconds
Started Jul 19 07:09:32 PM PDT 24
Finished Jul 19 07:16:01 PM PDT 24
Peak memory 201732 kb
Host smart-53e72c4a-6587-49a5-b5aa-68299c549211
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=389360607 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrup
t_fixed.389360607
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.3756245488
Short name T162
Test name
Test status
Simulation time 329787033278 ps
CPU time 213.1 seconds
Started Jul 19 07:09:35 PM PDT 24
Finished Jul 19 07:13:19 PM PDT 24
Peak memory 201760 kb
Host smart-1fe8c906-cda9-484e-b7c6-5408fc1baa21
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756245488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fix
ed.3756245488
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.4287313646
Short name T558
Test name
Test status
Simulation time 609928292457 ps
CPU time 1414.83 seconds
Started Jul 19 07:09:32 PM PDT 24
Finished Jul 19 07:33:19 PM PDT 24
Peak memory 201744 kb
Host smart-55f95d88-5106-491e-978f-8e21a8f2e6e2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287313646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.adc_ctrl_filters_wakeup_fixed.4287313646
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.1799318770
Short name T183
Test name
Test status
Simulation time 139048474903 ps
CPU time 394.38 seconds
Started Jul 19 07:09:41 PM PDT 24
Finished Jul 19 07:16:24 PM PDT 24
Peak memory 202160 kb
Host smart-b0123b7c-deb9-4c24-946c-e4affdbcf40b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799318770 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.1799318770
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.3445995393
Short name T415
Test name
Test status
Simulation time 36861446374 ps
CPU time 42.16 seconds
Started Jul 19 07:09:41 PM PDT 24
Finished Jul 19 07:10:31 PM PDT 24
Peak memory 201612 kb
Host smart-3ab14f91-bf46-44ff-9120-87184936d76e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445995393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.3445995393
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.1127497449
Short name T438
Test name
Test status
Simulation time 3175277688 ps
CPU time 9.5 seconds
Started Jul 19 07:10:06 PM PDT 24
Finished Jul 19 07:10:18 PM PDT 24
Peak memory 201616 kb
Host smart-262851fc-0f9a-49d9-8921-30c3b02d5ce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127497449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.1127497449
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.622019416
Short name T447
Test name
Test status
Simulation time 5567762314 ps
CPU time 15.08 seconds
Started Jul 19 07:09:34 PM PDT 24
Finished Jul 19 07:10:00 PM PDT 24
Peak memory 201624 kb
Host smart-9e0de1a9-aaed-41be-b31f-6ba03b1f88b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622019416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.622019416
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.3414601633
Short name T760
Test name
Test status
Simulation time 186504111793 ps
CPU time 453.64 seconds
Started Jul 19 07:09:52 PM PDT 24
Finished Jul 19 07:17:27 PM PDT 24
Peak memory 201808 kb
Host smart-c1ea9529-e255-4f83-b0d2-2fe3a82b1e25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414601633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all
.3414601633
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.3129882602
Short name T91
Test name
Test status
Simulation time 103098190093 ps
CPU time 61.62 seconds
Started Jul 19 07:09:40 PM PDT 24
Finished Jul 19 07:10:50 PM PDT 24
Peak memory 210060 kb
Host smart-9de2757a-f13c-49a3-94c3-62e012b80e4a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129882602 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.3129882602
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.3085258718
Short name T588
Test name
Test status
Simulation time 163060493884 ps
CPU time 352.09 seconds
Started Jul 19 07:09:57 PM PDT 24
Finished Jul 19 07:15:51 PM PDT 24
Peak memory 201796 kb
Host smart-1bb469bf-ae67-40f2-b467-109669534174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085258718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.3085258718
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.2944223736
Short name T387
Test name
Test status
Simulation time 327288857533 ps
CPU time 781.95 seconds
Started Jul 19 07:10:01 PM PDT 24
Finished Jul 19 07:23:04 PM PDT 24
Peak memory 201688 kb
Host smart-7deef142-4585-4979-92b3-67048a7bc6ba
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944223736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interru
pt_fixed.2944223736
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.1001912805
Short name T783
Test name
Test status
Simulation time 484412486148 ps
CPU time 766.11 seconds
Started Jul 19 07:09:56 PM PDT 24
Finished Jul 19 07:22:45 PM PDT 24
Peak memory 201780 kb
Host smart-c5edde5c-bfb6-4b61-90ff-3334fc78b3d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001912805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.1001912805
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.2406327750
Short name T134
Test name
Test status
Simulation time 326233430920 ps
CPU time 207.31 seconds
Started Jul 19 07:09:57 PM PDT 24
Finished Jul 19 07:13:27 PM PDT 24
Peak memory 201780 kb
Host smart-33a1683c-2f95-430b-9148-9fd7557d1176
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406327750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fix
ed.2406327750
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.3494324824
Short name T624
Test name
Test status
Simulation time 625471450778 ps
CPU time 1511.44 seconds
Started Jul 19 07:09:56 PM PDT 24
Finished Jul 19 07:35:11 PM PDT 24
Peak memory 201736 kb
Host smart-047fd22d-ffc4-45d6-a64e-a280918364a6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494324824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.adc_ctrl_filters_wakeup_fixed.3494324824
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.4032260711
Short name T411
Test name
Test status
Simulation time 67159968802 ps
CPU time 231.62 seconds
Started Jul 19 07:10:07 PM PDT 24
Finished Jul 19 07:14:01 PM PDT 24
Peak memory 202152 kb
Host smart-78e355e9-c3dd-4740-9b82-80f71c643a14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032260711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.4032260711
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.2431690942
Short name T697
Test name
Test status
Simulation time 42211786945 ps
CPU time 49 seconds
Started Jul 19 07:10:08 PM PDT 24
Finished Jul 19 07:11:01 PM PDT 24
Peak memory 201596 kb
Host smart-e7d7af31-ac76-4f8e-b746-5956032f6726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431690942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.2431690942
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.1933390519
Short name T329
Test name
Test status
Simulation time 4370592742 ps
CPU time 1.37 seconds
Started Jul 19 07:10:08 PM PDT 24
Finished Jul 19 07:10:15 PM PDT 24
Peak memory 201588 kb
Host smart-02d97749-f95f-4f7c-ba83-11f36ec3b824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933390519 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.1933390519
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.1803573021
Short name T379
Test name
Test status
Simulation time 5730250865 ps
CPU time 14.34 seconds
Started Jul 19 07:09:53 PM PDT 24
Finished Jul 19 07:10:08 PM PDT 24
Peak memory 201620 kb
Host smart-75e9bb14-1606-49f6-935a-e2a7db7fd744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803573021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.1803573021
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.3151236369
Short name T502
Test name
Test status
Simulation time 192847777740 ps
CPU time 121.7 seconds
Started Jul 19 07:10:14 PM PDT 24
Finished Jul 19 07:12:25 PM PDT 24
Peak memory 201732 kb
Host smart-be502684-abf7-4916-83d3-04c083f0e84b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151236369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all
.3151236369
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.3502516711
Short name T32
Test name
Test status
Simulation time 211949102353 ps
CPU time 235.22 seconds
Started Jul 19 07:10:08 PM PDT 24
Finished Jul 19 07:14:07 PM PDT 24
Peak memory 217972 kb
Host smart-ff81687c-fc9d-4c5b-a04a-06220e93ea37
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502516711 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.3502516711
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.1018706543
Short name T784
Test name
Test status
Simulation time 330852101 ps
CPU time 0.85 seconds
Started Jul 19 07:11:13 PM PDT 24
Finished Jul 19 07:11:30 PM PDT 24
Peak memory 201556 kb
Host smart-7a15b5ed-5a2e-49e4-9443-486cc6928fa0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018706543 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.1018706543
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.280446709
Short name T495
Test name
Test status
Simulation time 165867473306 ps
CPU time 96.97 seconds
Started Jul 19 07:10:27 PM PDT 24
Finished Jul 19 07:12:08 PM PDT 24
Peak memory 201744 kb
Host smart-a6b366fb-3c01-49bc-b76d-f899e607b380
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280446709 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gati
ng.280446709
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.656577020
Short name T270
Test name
Test status
Simulation time 167145335640 ps
CPU time 56.52 seconds
Started Jul 19 07:10:24 PM PDT 24
Finished Jul 19 07:11:26 PM PDT 24
Peak memory 201752 kb
Host smart-e39473f9-9c1e-47d9-a74c-fa27b5fbf1f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656577020 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.656577020
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.3932217840
Short name T693
Test name
Test status
Simulation time 165636065021 ps
CPU time 406.51 seconds
Started Jul 19 07:10:25 PM PDT 24
Finished Jul 19 07:17:16 PM PDT 24
Peak memory 201716 kb
Host smart-890c8369-111c-4e1e-a4dc-b9912d0ae661
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932217840 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interru
pt_fixed.3932217840
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.1741038546
Short name T567
Test name
Test status
Simulation time 162726151069 ps
CPU time 179.44 seconds
Started Jul 19 07:10:14 PM PDT 24
Finished Jul 19 07:13:23 PM PDT 24
Peak memory 201756 kb
Host smart-63948dc1-10bd-43dc-9811-2aaa4e211b73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741038546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.1741038546
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.1090008052
Short name T142
Test name
Test status
Simulation time 487661306785 ps
CPU time 281.6 seconds
Started Jul 19 07:10:16 PM PDT 24
Finished Jul 19 07:15:06 PM PDT 24
Peak memory 201704 kb
Host smart-80fc8cb1-40c8-4235-8412-48db6ef6c129
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090008052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fix
ed.1090008052
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.1110093475
Short name T541
Test name
Test status
Simulation time 439466863492 ps
CPU time 124.98 seconds
Started Jul 19 07:10:32 PM PDT 24
Finished Jul 19 07:12:39 PM PDT 24
Peak memory 201764 kb
Host smart-4a5a7430-0c77-47ea-bbc2-20315029df52
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110093475 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters
_wakeup.1110093475
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.3983563412
Short name T623
Test name
Test status
Simulation time 590322944657 ps
CPU time 1355.68 seconds
Started Jul 19 07:10:23 PM PDT 24
Finished Jul 19 07:33:05 PM PDT 24
Peak memory 201852 kb
Host smart-5aa4f8f7-ebe1-40a8-a168-e4014729758a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983563412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.adc_ctrl_filters_wakeup_fixed.3983563412
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.316536406
Short name T669
Test name
Test status
Simulation time 91204916648 ps
CPU time 354.61 seconds
Started Jul 19 07:11:12 PM PDT 24
Finished Jul 19 07:17:23 PM PDT 24
Peak memory 202100 kb
Host smart-ae3d4519-4fc7-418e-96d1-4a1e36539111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316536406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.316536406
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.3682306459
Short name T435
Test name
Test status
Simulation time 25328861113 ps
CPU time 37.74 seconds
Started Jul 19 07:11:12 PM PDT 24
Finished Jul 19 07:12:06 PM PDT 24
Peak memory 201588 kb
Host smart-8b735020-934a-46dd-8f31-2abceb727b12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682306459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.3682306459
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.3838199884
Short name T340
Test name
Test status
Simulation time 4075738969 ps
CPU time 3.5 seconds
Started Jul 19 07:11:13 PM PDT 24
Finished Jul 19 07:11:33 PM PDT 24
Peak memory 201584 kb
Host smart-e2f1828b-f7e4-40bf-8250-add843418d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838199884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.3838199884
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.1332604470
Short name T678
Test name
Test status
Simulation time 5536817194 ps
CPU time 3.75 seconds
Started Jul 19 07:10:16 PM PDT 24
Finished Jul 19 07:10:28 PM PDT 24
Peak memory 201628 kb
Host smart-b4cc0ff0-9ecd-47df-a561-9bac947b4fb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332604470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.1332604470
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.1475747659
Short name T217
Test name
Test status
Simulation time 353967965930 ps
CPU time 410.74 seconds
Started Jul 19 07:11:15 PM PDT 24
Finished Jul 19 07:18:22 PM PDT 24
Peak memory 201864 kb
Host smart-3f0199e8-5f2b-43a3-ab3a-73d358d22186
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475747659 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all
.1475747659
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.2371363435
Short name T25
Test name
Test status
Simulation time 101842152182 ps
CPU time 73.07 seconds
Started Jul 19 07:11:14 PM PDT 24
Finished Jul 19 07:12:44 PM PDT 24
Peak memory 202008 kb
Host smart-49e8a527-f723-45c6-9ac2-51c26fa20bdb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371363435 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.2371363435
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.1662236514
Short name T367
Test name
Test status
Simulation time 412825052 ps
CPU time 0.88 seconds
Started Jul 19 07:11:14 PM PDT 24
Finished Jul 19 07:11:32 PM PDT 24
Peak memory 201560 kb
Host smart-9009fad4-8bfb-48b9-9d40-237901ab6aee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662236514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.1662236514
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.1047488400
Short name T517
Test name
Test status
Simulation time 491462788494 ps
CPU time 436.75 seconds
Started Jul 19 07:11:16 PM PDT 24
Finished Jul 19 07:18:49 PM PDT 24
Peak memory 201740 kb
Host smart-b7d94f0b-0764-4f95-a6ac-c8b5b5cbc618
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047488400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gat
ing.1047488400
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.1373597468
Short name T313
Test name
Test status
Simulation time 489355908998 ps
CPU time 568.79 seconds
Started Jul 19 07:11:14 PM PDT 24
Finished Jul 19 07:21:00 PM PDT 24
Peak memory 201880 kb
Host smart-b5f001b4-4fc8-4582-b565-57fbe808e4ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373597468 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.1373597468
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.2962534826
Short name T393
Test name
Test status
Simulation time 496252267445 ps
CPU time 577.51 seconds
Started Jul 19 07:11:19 PM PDT 24
Finished Jul 19 07:21:11 PM PDT 24
Peak memory 201736 kb
Host smart-c2a71d1c-6f66-4878-bfaa-06b7c52c9aec
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962534826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interru
pt_fixed.2962534826
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.1299679771
Short name T125
Test name
Test status
Simulation time 327348820452 ps
CPU time 212.6 seconds
Started Jul 19 07:11:14 PM PDT 24
Finished Jul 19 07:15:03 PM PDT 24
Peak memory 201804 kb
Host smart-fcc12a30-29b3-4f8e-b2b5-2c0245c421c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299679771 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.1299679771
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.2137968089
Short name T661
Test name
Test status
Simulation time 330437366284 ps
CPU time 209.22 seconds
Started Jul 19 07:11:14 PM PDT 24
Finished Jul 19 07:15:00 PM PDT 24
Peak memory 201680 kb
Host smart-eacd4e6b-274b-4b1f-916b-e6911d6ef4c2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137968089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fix
ed.2137968089
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.909768408
Short name T141
Test name
Test status
Simulation time 376455589755 ps
CPU time 440.94 seconds
Started Jul 19 07:11:12 PM PDT 24
Finished Jul 19 07:18:50 PM PDT 24
Peak memory 201820 kb
Host smart-f2e1b1d4-50bc-4489-9b08-a4758f441975
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909768408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_
wakeup.909768408
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.2963107334
Short name T376
Test name
Test status
Simulation time 417309090014 ps
CPU time 939.07 seconds
Started Jul 19 07:11:14 PM PDT 24
Finished Jul 19 07:27:10 PM PDT 24
Peak memory 201776 kb
Host smart-86738f03-c6a2-4743-990d-4501beed229b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963107334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.adc_ctrl_filters_wakeup_fixed.2963107334
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.3245684246
Short name T93
Test name
Test status
Simulation time 42638564172 ps
CPU time 53.6 seconds
Started Jul 19 07:11:15 PM PDT 24
Finished Jul 19 07:12:25 PM PDT 24
Peak memory 201656 kb
Host smart-d77be278-0329-4104-bb2a-fcd2f081810e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245684246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.3245684246
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.115789965
Short name T459
Test name
Test status
Simulation time 3440808143 ps
CPU time 8.93 seconds
Started Jul 19 07:11:15 PM PDT 24
Finished Jul 19 07:11:40 PM PDT 24
Peak memory 201616 kb
Host smart-13704803-69dc-4524-b956-ebad3ab0721c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115789965 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.115789965
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.3325077509
Short name T749
Test name
Test status
Simulation time 5680671354 ps
CPU time 7.16 seconds
Started Jul 19 07:11:15 PM PDT 24
Finished Jul 19 07:11:38 PM PDT 24
Peak memory 201608 kb
Host smart-bb8f0951-3bfd-4036-83ea-3036afaf032d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325077509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.3325077509
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.3324557653
Short name T62
Test name
Test status
Simulation time 447357202 ps
CPU time 1.71 seconds
Started Jul 19 07:11:41 PM PDT 24
Finished Jul 19 07:11:48 PM PDT 24
Peak memory 201560 kb
Host smart-21cdc92d-05ef-4200-82ef-cae04021dbc7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324557653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.3324557653
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.4203668818
Short name T258
Test name
Test status
Simulation time 165297688812 ps
CPU time 422.74 seconds
Started Jul 19 07:11:24 PM PDT 24
Finished Jul 19 07:18:40 PM PDT 24
Peak memory 201748 kb
Host smart-1d0447e1-c149-4459-9760-f352d33e4e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203668818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.4203668818
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.3543910908
Short name T232
Test name
Test status
Simulation time 501313209625 ps
CPU time 297.53 seconds
Started Jul 19 07:11:14 PM PDT 24
Finished Jul 19 07:16:29 PM PDT 24
Peak memory 201708 kb
Host smart-88a5ce6e-4b23-4c3f-9abd-e0e6cd359889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543910908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.3543910908
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.763399664
Short name T395
Test name
Test status
Simulation time 327037810894 ps
CPU time 212.49 seconds
Started Jul 19 07:11:14 PM PDT 24
Finished Jul 19 07:15:03 PM PDT 24
Peak memory 201784 kb
Host smart-d0764514-c482-4123-a566-407885ec02b7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=763399664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrup
t_fixed.763399664
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.3869657140
Short name T300
Test name
Test status
Simulation time 334109347094 ps
CPU time 365.87 seconds
Started Jul 19 07:11:15 PM PDT 24
Finished Jul 19 07:17:37 PM PDT 24
Peak memory 201756 kb
Host smart-5a0fc076-84db-4dda-91fb-47995fcaae43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869657140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.3869657140
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.1043492570
Short name T405
Test name
Test status
Simulation time 321365957930 ps
CPU time 394.55 seconds
Started Jul 19 07:11:12 PM PDT 24
Finished Jul 19 07:18:03 PM PDT 24
Peak memory 201748 kb
Host smart-26a6e174-f47c-4eb1-b11f-b889d9cddece
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043492570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fix
ed.1043492570
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.3798873672
Short name T689
Test name
Test status
Simulation time 528446441350 ps
CPU time 319.14 seconds
Started Jul 19 07:11:13 PM PDT 24
Finished Jul 19 07:16:50 PM PDT 24
Peak memory 201936 kb
Host smart-c5a15d37-6698-4893-b582-63281fbfb1dd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798873672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters
_wakeup.3798873672
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.1192177334
Short name T501
Test name
Test status
Simulation time 578306110768 ps
CPU time 351.23 seconds
Started Jul 19 07:11:22 PM PDT 24
Finished Jul 19 07:17:27 PM PDT 24
Peak memory 201744 kb
Host smart-9a5dfeb2-dd92-4a79-aa5f-52117574f235
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192177334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.adc_ctrl_filters_wakeup_fixed.1192177334
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.2794156661
Short name T672
Test name
Test status
Simulation time 44623845223 ps
CPU time 106.21 seconds
Started Jul 19 07:11:25 PM PDT 24
Finished Jul 19 07:13:24 PM PDT 24
Peak memory 201600 kb
Host smart-7b5b4f7a-6552-4627-9a82-e3d168a2d9be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794156661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.2794156661
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.1417585729
Short name T355
Test name
Test status
Simulation time 4682842742 ps
CPU time 1.44 seconds
Started Jul 19 07:11:23 PM PDT 24
Finished Jul 19 07:11:38 PM PDT 24
Peak memory 201624 kb
Host smart-2d1312ff-1f68-4539-8b1b-a0c9436c2ac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417585729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.1417585729
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.2648467712
Short name T475
Test name
Test status
Simulation time 6166341273 ps
CPU time 4.91 seconds
Started Jul 19 07:11:16 PM PDT 24
Finished Jul 19 07:11:37 PM PDT 24
Peak memory 201604 kb
Host smart-d029eebb-2ae8-412c-ab6a-6d522ff1f250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648467712 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.2648467712
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.911315374
Short name T278
Test name
Test status
Simulation time 1213208514431 ps
CPU time 166.02 seconds
Started Jul 19 07:11:31 PM PDT 24
Finished Jul 19 07:14:28 PM PDT 24
Peak memory 210096 kb
Host smart-3485c7c1-9b71-4c71-a166-3619c9bd3deb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911315374 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.911315374
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.2338654625
Short name T82
Test name
Test status
Simulation time 453038102 ps
CPU time 0.75 seconds
Started Jul 19 07:11:58 PM PDT 24
Finished Jul 19 07:12:02 PM PDT 24
Peak memory 201560 kb
Host smart-1a0b7a81-60b4-451e-a3cb-81fffb4f6a90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338654625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.2338654625
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.4219617160
Short name T221
Test name
Test status
Simulation time 385274142790 ps
CPU time 524.85 seconds
Started Jul 19 07:11:50 PM PDT 24
Finished Jul 19 07:20:40 PM PDT 24
Peak memory 201712 kb
Host smart-9be7ff7c-6e4d-4833-ad56-2c0ff992d0a7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219617160 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gat
ing.4219617160
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.832362515
Short name T557
Test name
Test status
Simulation time 175155884785 ps
CPU time 437.19 seconds
Started Jul 19 07:11:51 PM PDT 24
Finished Jul 19 07:19:13 PM PDT 24
Peak memory 201748 kb
Host smart-de81d1fb-939d-4ad4-ae6b-284743431521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832362515 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.832362515
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.3905003787
Short name T148
Test name
Test status
Simulation time 488231775639 ps
CPU time 275.7 seconds
Started Jul 19 07:11:40 PM PDT 24
Finished Jul 19 07:16:22 PM PDT 24
Peak memory 201736 kb
Host smart-e4db6e6d-75d2-429a-9911-fd07d3d01c77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905003787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.3905003787
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.2015881852
Short name T506
Test name
Test status
Simulation time 320625866851 ps
CPU time 209.1 seconds
Started Jul 19 07:11:42 PM PDT 24
Finished Jul 19 07:15:17 PM PDT 24
Peak memory 201752 kb
Host smart-294a9fc5-4e29-493f-b4b8-032a10beed79
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015881852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interru
pt_fixed.2015881852
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.3436867226
Short name T173
Test name
Test status
Simulation time 491536874147 ps
CPU time 314.08 seconds
Started Jul 19 07:11:40 PM PDT 24
Finished Jul 19 07:17:00 PM PDT 24
Peak memory 201820 kb
Host smart-39e5bcb4-658d-4aa8-b10d-0be4dbc2cf67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436867226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.3436867226
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.186074176
Short name T370
Test name
Test status
Simulation time 488615607129 ps
CPU time 291.5 seconds
Started Jul 19 07:11:42 PM PDT 24
Finished Jul 19 07:16:39 PM PDT 24
Peak memory 201816 kb
Host smart-1a517137-749c-47fb-9147-d2f852876e67
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=186074176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fixe
d.186074176
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.349820659
Short name T197
Test name
Test status
Simulation time 400819961074 ps
CPU time 253.78 seconds
Started Jul 19 07:11:42 PM PDT 24
Finished Jul 19 07:16:01 PM PDT 24
Peak memory 201760 kb
Host smart-6bb3bf5e-c617-46f7-827d-bd2f6646278f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349820659 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_
wakeup.349820659
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.3581023282
Short name T85
Test name
Test status
Simulation time 606509383322 ps
CPU time 1494.8 seconds
Started Jul 19 07:11:49 PM PDT 24
Finished Jul 19 07:36:49 PM PDT 24
Peak memory 201748 kb
Host smart-2effb339-2c48-4fac-b842-4f0485e6dfa2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581023282 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.adc_ctrl_filters_wakeup_fixed.3581023282
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.3841051951
Short name T716
Test name
Test status
Simulation time 125325573742 ps
CPU time 480.24 seconds
Started Jul 19 07:11:50 PM PDT 24
Finished Jul 19 07:19:55 PM PDT 24
Peak memory 202096 kb
Host smart-01b2e3ba-7a2c-4161-87b4-c4bcbcf1b2b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841051951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.3841051951
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.1856847921
Short name T451
Test name
Test status
Simulation time 33545399542 ps
CPU time 80.69 seconds
Started Jul 19 07:11:57 PM PDT 24
Finished Jul 19 07:13:21 PM PDT 24
Peak memory 201616 kb
Host smart-67743d59-15a6-47db-8ddd-25968aacee5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856847921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.1856847921
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.2987262253
Short name T464
Test name
Test status
Simulation time 3371908962 ps
CPU time 4.5 seconds
Started Jul 19 07:11:56 PM PDT 24
Finished Jul 19 07:12:02 PM PDT 24
Peak memory 201608 kb
Host smart-38d8c1b4-7f0d-4de3-b8f8-6b1dd4020e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987262253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.2987262253
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.3024320314
Short name T691
Test name
Test status
Simulation time 5581785727 ps
CPU time 4.23 seconds
Started Jul 19 07:11:41 PM PDT 24
Finished Jul 19 07:11:51 PM PDT 24
Peak memory 201616 kb
Host smart-2479b4b6-b8e8-4588-befe-16580cdf6c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024320314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.3024320314
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.1284981761
Short name T664
Test name
Test status
Simulation time 331176943115 ps
CPU time 817.46 seconds
Started Jul 19 07:11:56 PM PDT 24
Finished Jul 19 07:25:35 PM PDT 24
Peak memory 201732 kb
Host smart-0bd32475-231e-4f8b-83f7-35bcb200dba4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284981761 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all
.1284981761
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.3326942562
Short name T310
Test name
Test status
Simulation time 125960384621 ps
CPU time 70.81 seconds
Started Jul 19 07:11:51 PM PDT 24
Finished Jul 19 07:13:06 PM PDT 24
Peak memory 201904 kb
Host smart-ada3d8ac-4d02-43e0-8b44-c2b41174a3e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326942562 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.3326942562
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.56090998
Short name T665
Test name
Test status
Simulation time 467017976 ps
CPU time 0.92 seconds
Started Jul 19 07:12:19 PM PDT 24
Finished Jul 19 07:12:24 PM PDT 24
Peak memory 201568 kb
Host smart-d0bac9a1-f0db-4551-b3e2-bbfe9f482553
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56090998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.56090998
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.3394602645
Short name T628
Test name
Test status
Simulation time 161327289340 ps
CPU time 4.18 seconds
Started Jul 19 07:12:09 PM PDT 24
Finished Jul 19 07:12:17 PM PDT 24
Peak memory 201764 kb
Host smart-84899749-19be-4c84-a7cc-6a14609a4631
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394602645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gat
ing.3394602645
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.1762256568
Short name T726
Test name
Test status
Simulation time 159454943598 ps
CPU time 200.45 seconds
Started Jul 19 07:12:00 PM PDT 24
Finished Jul 19 07:15:25 PM PDT 24
Peak memory 201784 kb
Host smart-4905cc40-00a2-4878-b5ce-255919c82ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762256568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.1762256568
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.3894544372
Short name T500
Test name
Test status
Simulation time 164667524880 ps
CPU time 101.08 seconds
Started Jul 19 07:12:11 PM PDT 24
Finished Jul 19 07:13:54 PM PDT 24
Peak memory 201724 kb
Host smart-e1b5a55b-a68f-462d-ba30-c27d5128e57c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894544372 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interru
pt_fixed.3894544372
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.2482991193
Short name T401
Test name
Test status
Simulation time 495620314272 ps
CPU time 299.19 seconds
Started Jul 19 07:11:59 PM PDT 24
Finished Jul 19 07:17:02 PM PDT 24
Peak memory 201728 kb
Host smart-b7f585e1-67a9-49b8-8817-01b0d3bde4e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482991193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.2482991193
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.888213896
Short name T352
Test name
Test status
Simulation time 494195573281 ps
CPU time 274.17 seconds
Started Jul 19 07:11:58 PM PDT 24
Finished Jul 19 07:16:37 PM PDT 24
Peak memory 201796 kb
Host smart-73b34e25-35cb-4d39-9d4c-f0e33604ab0a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=888213896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fixe
d.888213896
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.1615561357
Short name T536
Test name
Test status
Simulation time 536342315832 ps
CPU time 1334.73 seconds
Started Jul 19 07:12:10 PM PDT 24
Finished Jul 19 07:34:28 PM PDT 24
Peak memory 201824 kb
Host smart-c306f27b-5821-4ab7-8f3e-ebcd59f8a9be
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615561357 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters
_wakeup.1615561357
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.2251460742
Short name T396
Test name
Test status
Simulation time 197032128358 ps
CPU time 475.22 seconds
Started Jul 19 07:12:07 PM PDT 24
Finished Jul 19 07:20:05 PM PDT 24
Peak memory 201736 kb
Host smart-57633687-d27c-4f7d-aaa8-d7cf296a575c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251460742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16
.adc_ctrl_filters_wakeup_fixed.2251460742
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.2102214647
Short name T614
Test name
Test status
Simulation time 83941328289 ps
CPU time 339.47 seconds
Started Jul 19 07:12:19 PM PDT 24
Finished Jul 19 07:18:02 PM PDT 24
Peak memory 202084 kb
Host smart-8648931e-e236-4323-80ae-c0d5fdc46c5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102214647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.2102214647
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.3585853249
Short name T596
Test name
Test status
Simulation time 41030175928 ps
CPU time 81.93 seconds
Started Jul 19 07:12:18 PM PDT 24
Finished Jul 19 07:13:44 PM PDT 24
Peak memory 201620 kb
Host smart-93c1ac01-f038-435e-b64d-4e47fee562e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585853249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.3585853249
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.890539212
Short name T465
Test name
Test status
Simulation time 4164099996 ps
CPU time 3.61 seconds
Started Jul 19 07:12:20 PM PDT 24
Finished Jul 19 07:12:27 PM PDT 24
Peak memory 201604 kb
Host smart-77070e46-a26d-4735-ba81-fd572ad8134b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890539212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.890539212
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.1381644913
Short name T484
Test name
Test status
Simulation time 5710478343 ps
CPU time 7.69 seconds
Started Jul 19 07:11:58 PM PDT 24
Finished Jul 19 07:12:10 PM PDT 24
Peak memory 201608 kb
Host smart-b7c606df-9bcb-445c-a90b-bb8d6a21a9be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381644913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.1381644913
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.2204727271
Short name T743
Test name
Test status
Simulation time 369646208460 ps
CPU time 238.43 seconds
Started Jul 19 07:12:19 PM PDT 24
Finished Jul 19 07:16:21 PM PDT 24
Peak memory 201696 kb
Host smart-d92fe05e-4470-47a7-a32f-580298e376da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204727271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all
.2204727271
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.773803761
Short name T14
Test name
Test status
Simulation time 468447359758 ps
CPU time 531.97 seconds
Started Jul 19 07:12:19 PM PDT 24
Finished Jul 19 07:21:14 PM PDT 24
Peak memory 217696 kb
Host smart-790c16d4-46ce-4f0f-b8ed-b5236bab39a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773803761 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.773803761
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.2634491171
Short name T344
Test name
Test status
Simulation time 489959824 ps
CPU time 0.7 seconds
Started Jul 19 07:12:28 PM PDT 24
Finished Jul 19 07:12:33 PM PDT 24
Peak memory 201552 kb
Host smart-83afc689-5136-4107-baa2-4221bc071c41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634491171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.2634491171
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.2547079949
Short name T561
Test name
Test status
Simulation time 618691046299 ps
CPU time 1163.18 seconds
Started Jul 19 07:12:29 PM PDT 24
Finished Jul 19 07:31:56 PM PDT 24
Peak memory 201740 kb
Host smart-7303c84c-3191-4922-add7-a376749f56db
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547079949 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gat
ing.2547079949
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.1451069466
Short name T662
Test name
Test status
Simulation time 200371130434 ps
CPU time 444.32 seconds
Started Jul 19 07:12:28 PM PDT 24
Finished Jul 19 07:19:57 PM PDT 24
Peak memory 201748 kb
Host smart-d269aad0-785a-45cc-801e-0a3dd91a824d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451069466 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.1451069466
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.785390763
Short name T126
Test name
Test status
Simulation time 334167236089 ps
CPU time 197.8 seconds
Started Jul 19 07:12:17 PM PDT 24
Finished Jul 19 07:15:38 PM PDT 24
Peak memory 201808 kb
Host smart-981e3c9d-0f8e-46d2-9721-f8cd6a5b8946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785390763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.785390763
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.4054898817
Short name T434
Test name
Test status
Simulation time 327483444353 ps
CPU time 199.67 seconds
Started Jul 19 07:12:19 PM PDT 24
Finished Jul 19 07:15:42 PM PDT 24
Peak memory 201732 kb
Host smart-a5a37b5a-d63e-421a-959d-ab143748209c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054898817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interru
pt_fixed.4054898817
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.233792485
Short name T123
Test name
Test status
Simulation time 484472387422 ps
CPU time 575.01 seconds
Started Jul 19 07:12:19 PM PDT 24
Finished Jul 19 07:21:58 PM PDT 24
Peak memory 201756 kb
Host smart-4a806b1e-dca3-40ca-b83a-1068ea9a6b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233792485 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.233792485
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.3952367135
Short name T548
Test name
Test status
Simulation time 330923357844 ps
CPU time 162.17 seconds
Started Jul 19 07:12:19 PM PDT 24
Finished Jul 19 07:15:06 PM PDT 24
Peak memory 201752 kb
Host smart-ff61e36a-eef0-4e65-922b-c06f33f47e88
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952367135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fix
ed.3952367135
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.1636063208
Short name T789
Test name
Test status
Simulation time 195138294270 ps
CPU time 242.92 seconds
Started Jul 19 07:12:29 PM PDT 24
Finished Jul 19 07:16:36 PM PDT 24
Peak memory 201748 kb
Host smart-cdbfbebb-d478-41f9-af9c-5bbec6e0c93f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636063208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.adc_ctrl_filters_wakeup_fixed.1636063208
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.1488187234
Short name T43
Test name
Test status
Simulation time 69246680260 ps
CPU time 382.05 seconds
Started Jul 19 07:12:28 PM PDT 24
Finished Jul 19 07:18:54 PM PDT 24
Peak memory 202096 kb
Host smart-ec87f50e-0325-4167-a28a-ad3271ba87f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488187234 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.1488187234
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.3642899268
Short name T642
Test name
Test status
Simulation time 44957115905 ps
CPU time 55.31 seconds
Started Jul 19 07:12:27 PM PDT 24
Finished Jul 19 07:13:27 PM PDT 24
Peak memory 201592 kb
Host smart-17271e1e-41e1-45ea-b450-8095d5c40670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642899268 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.3642899268
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.2311681329
Short name T527
Test name
Test status
Simulation time 4575014111 ps
CPU time 10.86 seconds
Started Jul 19 07:12:28 PM PDT 24
Finished Jul 19 07:12:44 PM PDT 24
Peak memory 201592 kb
Host smart-684c9a5c-4f92-4d88-b804-0e3a7564ed2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311681329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.2311681329
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.1960152750
Short name T412
Test name
Test status
Simulation time 6159097877 ps
CPU time 14.97 seconds
Started Jul 19 07:12:18 PM PDT 24
Finished Jul 19 07:12:37 PM PDT 24
Peak memory 201596 kb
Host smart-8c316452-413c-4b00-be25-df58b6756f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960152750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.1960152750
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.448708249
Short name T216
Test name
Test status
Simulation time 334287950293 ps
CPU time 403.85 seconds
Started Jul 19 07:12:28 PM PDT 24
Finished Jul 19 07:19:17 PM PDT 24
Peak memory 201808 kb
Host smart-b68ac6b6-bbe7-41b4-ae0f-e4706836c89f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448708249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all.
448708249
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.1611322225
Short name T619
Test name
Test status
Simulation time 401089318 ps
CPU time 1.12 seconds
Started Jul 19 07:13:02 PM PDT 24
Finished Jul 19 07:13:06 PM PDT 24
Peak memory 201552 kb
Host smart-524e06dc-1724-41fa-9841-196208babdec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611322225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.1611322225
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.1429475651
Short name T130
Test name
Test status
Simulation time 359184179280 ps
CPU time 239.62 seconds
Started Jul 19 07:12:51 PM PDT 24
Finished Jul 19 07:16:55 PM PDT 24
Peak memory 201800 kb
Host smart-b36376ab-e14a-41e9-b9af-dfae211a2491
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429475651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gat
ing.1429475651
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.1031346766
Short name T161
Test name
Test status
Simulation time 330027142523 ps
CPU time 188.48 seconds
Started Jul 19 07:12:37 PM PDT 24
Finished Jul 19 07:15:49 PM PDT 24
Peak memory 201752 kb
Host smart-57e7bc90-16e8-4725-a20d-7d673c1efa4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031346766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.1031346766
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.1387171156
Short name T732
Test name
Test status
Simulation time 326560382651 ps
CPU time 417.82 seconds
Started Jul 19 07:12:38 PM PDT 24
Finished Jul 19 07:19:38 PM PDT 24
Peak memory 201712 kb
Host smart-855a60ab-c95f-4597-bd66-eacb616d8d8c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387171156 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interru
pt_fixed.1387171156
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.218664388
Short name T137
Test name
Test status
Simulation time 328481648837 ps
CPU time 173.95 seconds
Started Jul 19 07:12:38 PM PDT 24
Finished Jul 19 07:15:35 PM PDT 24
Peak memory 201820 kb
Host smart-98304912-2aa2-459f-b3ac-0180e7749ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218664388 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.218664388
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.3404821726
Short name T76
Test name
Test status
Simulation time 163778659875 ps
CPU time 66.28 seconds
Started Jul 19 07:12:38 PM PDT 24
Finished Jul 19 07:13:47 PM PDT 24
Peak memory 201724 kb
Host smart-31de2e58-a443-469c-88b6-0fc2f85bb4ff
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404821726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fix
ed.3404821726
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.3082965912
Short name T765
Test name
Test status
Simulation time 203175728648 ps
CPU time 434 seconds
Started Jul 19 07:12:50 PM PDT 24
Finished Jul 19 07:20:08 PM PDT 24
Peak memory 201728 kb
Host smart-eee278c0-230f-49b5-bb8f-581ac6291075
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082965912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.adc_ctrl_filters_wakeup_fixed.3082965912
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.1715458968
Short name T511
Test name
Test status
Simulation time 124515848692 ps
CPU time 452.08 seconds
Started Jul 19 07:13:02 PM PDT 24
Finished Jul 19 07:20:37 PM PDT 24
Peak memory 202108 kb
Host smart-db84a61b-fda8-4f34-9934-1510145a1c65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715458968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.1715458968
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.1467746987
Short name T455
Test name
Test status
Simulation time 48156972504 ps
CPU time 120.14 seconds
Started Jul 19 07:12:52 PM PDT 24
Finished Jul 19 07:14:56 PM PDT 24
Peak memory 201548 kb
Host smart-97df0362-66a2-4e84-b780-0882c8b49562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467746987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.1467746987
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.3738067037
Short name T781
Test name
Test status
Simulation time 5473040414 ps
CPU time 10.43 seconds
Started Jul 19 07:12:52 PM PDT 24
Finished Jul 19 07:13:07 PM PDT 24
Peak memory 201568 kb
Host smart-8c73a6b3-a228-4b2f-b222-e0a16f11a84f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738067037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.3738067037
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.2187623992
Short name T470
Test name
Test status
Simulation time 6010225020 ps
CPU time 2.97 seconds
Started Jul 19 07:12:27 PM PDT 24
Finished Jul 19 07:12:35 PM PDT 24
Peak memory 201604 kb
Host smart-98eabb7b-b8d0-4e2e-89fd-373c16bf52dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187623992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.2187623992
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.3905962676
Short name T259
Test name
Test status
Simulation time 186639098151 ps
CPU time 107.91 seconds
Started Jul 19 07:13:03 PM PDT 24
Finished Jul 19 07:14:54 PM PDT 24
Peak memory 201748 kb
Host smart-e014622f-02c7-4214-a43c-c0a782a2fbe9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905962676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all
.3905962676
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.11476134
Short name T27
Test name
Test status
Simulation time 166020868948 ps
CPU time 137.78 seconds
Started Jul 19 07:13:03 PM PDT 24
Finished Jul 19 07:15:24 PM PDT 24
Peak memory 218620 kb
Host smart-bec229c3-8447-434f-952d-560a663d2839
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11476134 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.11476134
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.2964459237
Short name T603
Test name
Test status
Simulation time 530279337 ps
CPU time 0.96 seconds
Started Jul 19 07:13:14 PM PDT 24
Finished Jul 19 07:13:19 PM PDT 24
Peak memory 201556 kb
Host smart-0bdc448b-97a1-4f6b-bd86-4254ff09542e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964459237 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.2964459237
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.1073323891
Short name T528
Test name
Test status
Simulation time 533016901964 ps
CPU time 1159.43 seconds
Started Jul 19 07:13:15 PM PDT 24
Finished Jul 19 07:32:38 PM PDT 24
Peak memory 201720 kb
Host smart-3640751d-256d-4ce9-98c0-4a0eeaa9d970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073323891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.1073323891
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.355463111
Short name T267
Test name
Test status
Simulation time 324284232807 ps
CPU time 215.21 seconds
Started Jul 19 07:13:03 PM PDT 24
Finished Jul 19 07:16:41 PM PDT 24
Peak memory 201756 kb
Host smart-ffbf0c52-3fb3-4a95-b235-cbd03b6afd4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355463111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.355463111
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.769072951
Short name T683
Test name
Test status
Simulation time 161461013895 ps
CPU time 184.4 seconds
Started Jul 19 07:13:13 PM PDT 24
Finished Jul 19 07:16:21 PM PDT 24
Peak memory 201736 kb
Host smart-127b6b82-b59c-4547-8441-d5cbcfcc5281
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=769072951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrup
t_fixed.769072951
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.574630561
Short name T579
Test name
Test status
Simulation time 161354886547 ps
CPU time 100.25 seconds
Started Jul 19 07:13:01 PM PDT 24
Finished Jul 19 07:14:45 PM PDT 24
Peak memory 201872 kb
Host smart-09c7b5e3-c834-4a69-a698-336558ee6465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574630561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.574630561
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.246781919
Short name T443
Test name
Test status
Simulation time 159559016131 ps
CPU time 50.49 seconds
Started Jul 19 07:13:02 PM PDT 24
Finished Jul 19 07:13:56 PM PDT 24
Peak memory 201732 kb
Host smart-06256a84-5543-45d7-a237-c5d0b1f42d21
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=246781919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fixe
d.246781919
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.2322891297
Short name T290
Test name
Test status
Simulation time 528165465393 ps
CPU time 1251.74 seconds
Started Jul 19 07:13:15 PM PDT 24
Finished Jul 19 07:34:10 PM PDT 24
Peak memory 201816 kb
Host smart-40225cd8-3beb-4725-b099-96e4ed234d5f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322891297 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters
_wakeup.2322891297
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.3819855793
Short name T727
Test name
Test status
Simulation time 200471684322 ps
CPU time 222.47 seconds
Started Jul 19 07:13:14 PM PDT 24
Finished Jul 19 07:17:00 PM PDT 24
Peak memory 201740 kb
Host smart-ebd7dd9b-c61d-4879-8f09-23a4905953da
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819855793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.adc_ctrl_filters_wakeup_fixed.3819855793
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.812304314
Short name T701
Test name
Test status
Simulation time 70684715357 ps
CPU time 239.57 seconds
Started Jul 19 07:13:13 PM PDT 24
Finished Jul 19 07:17:16 PM PDT 24
Peak memory 202112 kb
Host smart-6d0d76db-011c-4a5a-b57e-4fd6dd214856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812304314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.812304314
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.3948059773
Short name T494
Test name
Test status
Simulation time 46864559390 ps
CPU time 28.5 seconds
Started Jul 19 07:13:13 PM PDT 24
Finished Jul 19 07:13:46 PM PDT 24
Peak memory 201740 kb
Host smart-fe4c10f5-acfc-4684-9208-d946e9eec442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948059773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.3948059773
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.3971489688
Short name T593
Test name
Test status
Simulation time 5448694303 ps
CPU time 12.92 seconds
Started Jul 19 07:13:15 PM PDT 24
Finished Jul 19 07:13:31 PM PDT 24
Peak memory 201604 kb
Host smart-608a81a3-2476-440b-80f3-907b81720b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971489688 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.3971489688
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.250943814
Short name T490
Test name
Test status
Simulation time 5799106212 ps
CPU time 3.85 seconds
Started Jul 19 07:13:02 PM PDT 24
Finished Jul 19 07:13:09 PM PDT 24
Peak memory 201600 kb
Host smart-ee0c83ea-99d9-4e80-8416-4e8cf6c9d359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250943814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.250943814
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.2889560748
Short name T273
Test name
Test status
Simulation time 328093439595 ps
CPU time 759.77 seconds
Started Jul 19 07:13:14 PM PDT 24
Finished Jul 19 07:25:57 PM PDT 24
Peak memory 201744 kb
Host smart-60eb6508-2388-4814-a538-4272b8e6d47e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889560748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all
.2889560748
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.356302456
Short name T53
Test name
Test status
Simulation time 301502803335 ps
CPU time 179.35 seconds
Started Jul 19 07:13:14 PM PDT 24
Finished Jul 19 07:16:17 PM PDT 24
Peak memory 218272 kb
Host smart-00d99bec-b7b2-4b9c-a134-275c87d91514
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356302456 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.356302456
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.3781074823
Short name T580
Test name
Test status
Simulation time 508172273 ps
CPU time 1.85 seconds
Started Jul 19 07:06:45 PM PDT 24
Finished Jul 19 07:06:48 PM PDT 24
Peak memory 201572 kb
Host smart-d3d2234c-73b3-479c-8290-c7212e22d9e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781074823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.3781074823
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.2891427710
Short name T742
Test name
Test status
Simulation time 190558330013 ps
CPU time 471.56 seconds
Started Jul 19 07:06:23 PM PDT 24
Finished Jul 19 07:14:16 PM PDT 24
Peak memory 201752 kb
Host smart-6cbeed02-f4ed-4244-861e-cb641efd6189
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891427710 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gati
ng.2891427710
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.627266120
Short name T767
Test name
Test status
Simulation time 494136174595 ps
CPU time 319.92 seconds
Started Jul 19 07:06:21 PM PDT 24
Finished Jul 19 07:11:42 PM PDT 24
Peak memory 201716 kb
Host smart-55e97146-7310-4df7-8afb-2d2963a59097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627266120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.627266120
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.4199846505
Short name T73
Test name
Test status
Simulation time 487899052690 ps
CPU time 303.51 seconds
Started Jul 19 07:06:17 PM PDT 24
Finished Jul 19 07:11:22 PM PDT 24
Peak memory 201748 kb
Host smart-3506362b-1561-4bac-a8a2-488d8ff3b6b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199846505 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.4199846505
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.980990000
Short name T551
Test name
Test status
Simulation time 493825327017 ps
CPU time 1112.16 seconds
Started Jul 19 07:06:17 PM PDT 24
Finished Jul 19 07:24:51 PM PDT 24
Peak memory 201744 kb
Host smart-9947dc29-8e74-4364-a627-6b729e7f781e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=980990000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt
_fixed.980990000
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.1707510077
Short name T301
Test name
Test status
Simulation time 163021083999 ps
CPU time 410.51 seconds
Started Jul 19 07:06:09 PM PDT 24
Finished Jul 19 07:13:00 PM PDT 24
Peak memory 201764 kb
Host smart-6d3d971d-61ba-44c4-a3a3-6835126e9d5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707510077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.1707510077
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.530513041
Short name T703
Test name
Test status
Simulation time 163842810135 ps
CPU time 212.24 seconds
Started Jul 19 07:06:07 PM PDT 24
Finished Jul 19 07:09:41 PM PDT 24
Peak memory 201800 kb
Host smart-f1c18732-dc94-4ba4-9b68-8b50c214602b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=530513041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixed
.530513041
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.191329919
Short name T766
Test name
Test status
Simulation time 616948368443 ps
CPU time 1553.51 seconds
Started Jul 19 07:06:17 PM PDT 24
Finished Jul 19 07:32:12 PM PDT 24
Peak memory 201756 kb
Host smart-ecf31765-8e91-4f9e-a988-76d20585b49a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191329919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_w
akeup.191329919
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.2160924979
Short name T520
Test name
Test status
Simulation time 201684212343 ps
CPU time 472.96 seconds
Started Jul 19 07:06:13 PM PDT 24
Finished Jul 19 07:14:08 PM PDT 24
Peak memory 201712 kb
Host smart-96d1a37e-26c4-4c68-99e0-8fea0f2b1993
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160924979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
adc_ctrl_filters_wakeup_fixed.2160924979
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.285821706
Short name T181
Test name
Test status
Simulation time 138069698843 ps
CPU time 522.29 seconds
Started Jul 19 07:06:32 PM PDT 24
Finished Jul 19 07:15:16 PM PDT 24
Peak memory 202108 kb
Host smart-7ec2d198-0a7d-4c4f-85a5-16778dd1315c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285821706 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.285821706
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.171100950
Short name T391
Test name
Test status
Simulation time 37344197177 ps
CPU time 83.96 seconds
Started Jul 19 07:06:24 PM PDT 24
Finished Jul 19 07:07:49 PM PDT 24
Peak memory 201616 kb
Host smart-8be937cc-c846-41f2-b5c9-df1f7f19e1a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171100950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.171100950
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.920624125
Short name T448
Test name
Test status
Simulation time 4445128246 ps
CPU time 7.4 seconds
Started Jul 19 07:06:27 PM PDT 24
Finished Jul 19 07:06:35 PM PDT 24
Peak memory 201628 kb
Host smart-147bc7e5-0ac9-4efb-baf7-ecbddbc76433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920624125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.920624125
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.4031617847
Short name T487
Test name
Test status
Simulation time 6022801394 ps
CPU time 11.89 seconds
Started Jul 19 07:06:03 PM PDT 24
Finished Jul 19 07:06:16 PM PDT 24
Peak memory 201612 kb
Host smart-72019ffe-cec4-49ba-b75f-4026d6969ca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031617847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.4031617847
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.1431998280
Short name T283
Test name
Test status
Simulation time 668338599895 ps
CPU time 1579.3 seconds
Started Jul 19 07:06:54 PM PDT 24
Finished Jul 19 07:33:15 PM PDT 24
Peak memory 201740 kb
Host smart-811952c6-e2fa-4fec-93d1-049ff1601fb5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431998280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.
1431998280
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.110202549
Short name T394
Test name
Test status
Simulation time 408642311 ps
CPU time 1.51 seconds
Started Jul 19 07:13:39 PM PDT 24
Finished Jul 19 07:13:42 PM PDT 24
Peak memory 201504 kb
Host smart-dba5c9cd-c759-4ad0-8222-0574ed10cbab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110202549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.110202549
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.3528689901
Short name T218
Test name
Test status
Simulation time 191724123921 ps
CPU time 439.36 seconds
Started Jul 19 07:13:27 PM PDT 24
Finished Jul 19 07:20:49 PM PDT 24
Peak memory 201760 kb
Host smart-04ef8003-fa19-411e-b4c5-341f2d23940f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528689901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gat
ing.3528689901
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.1055780150
Short name T166
Test name
Test status
Simulation time 330830174723 ps
CPU time 163.74 seconds
Started Jul 19 07:13:24 PM PDT 24
Finished Jul 19 07:16:11 PM PDT 24
Peak memory 201768 kb
Host smart-a3bf6abb-617b-400a-b33d-11bf0f642e95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055780150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.1055780150
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.3904987817
Short name T524
Test name
Test status
Simulation time 324869156424 ps
CPU time 781.74 seconds
Started Jul 19 07:13:25 PM PDT 24
Finished Jul 19 07:26:29 PM PDT 24
Peak memory 201724 kb
Host smart-9385aacb-4de8-415a-aab8-fee92422fd8d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904987817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interru
pt_fixed.3904987817
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.3325040972
Short name T560
Test name
Test status
Simulation time 167726453126 ps
CPU time 93.38 seconds
Started Jul 19 07:13:15 PM PDT 24
Finished Jul 19 07:14:52 PM PDT 24
Peak memory 201752 kb
Host smart-22225d71-9601-4ac0-b5d4-65b8b2b8e9a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325040972 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.3325040972
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.1349462187
Short name T372
Test name
Test status
Simulation time 326945476908 ps
CPU time 695.05 seconds
Started Jul 19 07:13:27 PM PDT 24
Finished Jul 19 07:25:05 PM PDT 24
Peak memory 201696 kb
Host smart-96a699f9-904c-49ba-af7d-864a93e4cd68
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349462187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fix
ed.1349462187
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.3475813811
Short name T305
Test name
Test status
Simulation time 185795949851 ps
CPU time 57.57 seconds
Started Jul 19 07:13:26 PM PDT 24
Finished Jul 19 07:14:26 PM PDT 24
Peak memory 201760 kb
Host smart-2836eacf-c99b-433f-9704-10bf4d9d3698
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475813811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters
_wakeup.3475813811
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.687154512
Short name T427
Test name
Test status
Simulation time 627710219422 ps
CPU time 658.01 seconds
Started Jul 19 07:13:27 PM PDT 24
Finished Jul 19 07:24:28 PM PDT 24
Peak memory 201720 kb
Host smart-ac19b5d9-f9d0-4e8a-843d-8f91b1583efa
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687154512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
adc_ctrl_filters_wakeup_fixed.687154512
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.118552493
Short name T326
Test name
Test status
Simulation time 123909786800 ps
CPU time 415.63 seconds
Started Jul 19 07:13:25 PM PDT 24
Finished Jul 19 07:20:23 PM PDT 24
Peak memory 202136 kb
Host smart-9d21ae64-c2c2-4c6a-8e4c-b1d578df87a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118552493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.118552493
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.247219491
Short name T657
Test name
Test status
Simulation time 41200620678 ps
CPU time 89.76 seconds
Started Jul 19 07:13:25 PM PDT 24
Finished Jul 19 07:14:57 PM PDT 24
Peak memory 201744 kb
Host smart-e3ab0bed-4152-4f26-a130-ae565651f898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247219491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.247219491
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.2833258066
Short name T402
Test name
Test status
Simulation time 3346139232 ps
CPU time 2.86 seconds
Started Jul 19 07:13:26 PM PDT 24
Finished Jul 19 07:13:32 PM PDT 24
Peak memory 201596 kb
Host smart-ebf202d2-9112-4c00-a016-2641437bbf38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833258066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.2833258066
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.2183613509
Short name T115
Test name
Test status
Simulation time 5872860879 ps
CPU time 13.94 seconds
Started Jul 19 07:13:14 PM PDT 24
Finished Jul 19 07:13:32 PM PDT 24
Peak memory 201600 kb
Host smart-665a193f-88a7-477c-8522-2320e9cce2f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183613509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.2183613509
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.1307227030
Short name T77
Test name
Test status
Simulation time 262923101268 ps
CPU time 149.27 seconds
Started Jul 19 07:13:25 PM PDT 24
Finished Jul 19 07:15:57 PM PDT 24
Peak memory 210128 kb
Host smart-19c4e923-007c-407d-8c92-4445a301ba53
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307227030 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.1307227030
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.800800535
Short name T463
Test name
Test status
Simulation time 329404237 ps
CPU time 0.85 seconds
Started Jul 19 07:13:46 PM PDT 24
Finished Jul 19 07:13:51 PM PDT 24
Peak memory 201520 kb
Host smart-78f07ec6-fb5b-43e6-8caf-02b35cc01ff6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800800535 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.800800535
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.1151672428
Short name T615
Test name
Test status
Simulation time 340233519830 ps
CPU time 322.99 seconds
Started Jul 19 07:13:35 PM PDT 24
Finished Jul 19 07:19:01 PM PDT 24
Peak memory 201812 kb
Host smart-8384ddee-2150-4138-9254-bf9e0628ef21
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151672428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gat
ing.1151672428
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.814260773
Short name T741
Test name
Test status
Simulation time 342686147982 ps
CPU time 805.39 seconds
Started Jul 19 07:13:36 PM PDT 24
Finished Jul 19 07:27:05 PM PDT 24
Peak memory 201724 kb
Host smart-0a13e842-3c46-4bdb-91a4-0248f1a78d15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814260773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.814260773
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.1708047072
Short name T648
Test name
Test status
Simulation time 166435453714 ps
CPU time 126.59 seconds
Started Jul 19 07:13:37 PM PDT 24
Finished Jul 19 07:15:46 PM PDT 24
Peak memory 201712 kb
Host smart-e2483f13-87f5-46cf-832d-d8487d9d0e14
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708047072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interru
pt_fixed.1708047072
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.1210151492
Short name T268
Test name
Test status
Simulation time 337936539483 ps
CPU time 194.06 seconds
Started Jul 19 07:13:39 PM PDT 24
Finished Jul 19 07:16:55 PM PDT 24
Peak memory 201772 kb
Host smart-1f12c1b7-8e1e-4ed7-bc39-e230de933475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210151492 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.1210151492
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.1685567081
Short name T610
Test name
Test status
Simulation time 170725734553 ps
CPU time 44.83 seconds
Started Jul 19 07:13:37 PM PDT 24
Finished Jul 19 07:14:25 PM PDT 24
Peak memory 201744 kb
Host smart-cd9918e7-5716-4217-97c3-a4f016bbad98
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685567081 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fix
ed.1685567081
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.2187731802
Short name T286
Test name
Test status
Simulation time 394418900656 ps
CPU time 236.21 seconds
Started Jul 19 07:13:35 PM PDT 24
Finished Jul 19 07:17:35 PM PDT 24
Peak memory 201884 kb
Host smart-a864c5e1-b51f-4eda-b066-868629de48a4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187731802 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters
_wakeup.2187731802
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.2638424895
Short name T630
Test name
Test status
Simulation time 598519754978 ps
CPU time 342.34 seconds
Started Jul 19 07:13:35 PM PDT 24
Finished Jul 19 07:19:21 PM PDT 24
Peak memory 201688 kb
Host smart-fd02c936-a3f8-4150-8b32-bf516c20d4aa
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638424895 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.adc_ctrl_filters_wakeup_fixed.2638424895
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.1919139680
Short name T721
Test name
Test status
Simulation time 80866646965 ps
CPU time 274 seconds
Started Jul 19 07:13:45 PM PDT 24
Finished Jul 19 07:18:23 PM PDT 24
Peak memory 202132 kb
Host smart-ca926e27-f4fe-4c2d-a0e0-bc291e2a6ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919139680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.1919139680
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.359326602
Short name T652
Test name
Test status
Simulation time 43018021953 ps
CPU time 102.67 seconds
Started Jul 19 07:13:46 PM PDT 24
Finished Jul 19 07:15:33 PM PDT 24
Peak memory 201604 kb
Host smart-9fddbaea-6357-43fe-b9da-641333c41eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359326602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.359326602
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.3246760219
Short name T429
Test name
Test status
Simulation time 3902390445 ps
CPU time 2.84 seconds
Started Jul 19 07:13:46 PM PDT 24
Finished Jul 19 07:13:53 PM PDT 24
Peak memory 201612 kb
Host smart-b8984f10-8a8c-430c-ac71-7bb0153c3b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246760219 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.3246760219
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.2540210613
Short name T632
Test name
Test status
Simulation time 5764919494 ps
CPU time 4.1 seconds
Started Jul 19 07:13:37 PM PDT 24
Finished Jul 19 07:13:44 PM PDT 24
Peak memory 201544 kb
Host smart-eb8c990c-f833-43a4-a193-81e149e23b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540210613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.2540210613
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.2757441964
Short name T174
Test name
Test status
Simulation time 534304209484 ps
CPU time 332.59 seconds
Started Jul 19 07:13:45 PM PDT 24
Finished Jul 19 07:19:22 PM PDT 24
Peak memory 201744 kb
Host smart-85ff400d-b2a6-4ed2-8f01-e2b70e1e7e9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757441964 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all
.2757441964
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.1256055921
Short name T88
Test name
Test status
Simulation time 153937503492 ps
CPU time 104.62 seconds
Started Jul 19 07:13:46 PM PDT 24
Finished Jul 19 07:15:35 PM PDT 24
Peak memory 210520 kb
Host smart-2f60ef3c-7dae-41ef-a3b7-6f167b0b26ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256055921 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.1256055921
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.1362236867
Short name T759
Test name
Test status
Simulation time 527604627 ps
CPU time 1.24 seconds
Started Jul 19 07:14:11 PM PDT 24
Finished Jul 19 07:14:15 PM PDT 24
Peak memory 201564 kb
Host smart-892a1b14-b1d2-4df1-8076-7f21fa218c87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362236867 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.1362236867
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.133886661
Short name T248
Test name
Test status
Simulation time 159454480618 ps
CPU time 175.22 seconds
Started Jul 19 07:13:57 PM PDT 24
Finished Jul 19 07:16:56 PM PDT 24
Peak memory 201748 kb
Host smart-2e3ac86d-758d-4d26-8d45-5294ecf0de3f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133886661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gati
ng.133886661
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.2254272671
Short name T239
Test name
Test status
Simulation time 341855039429 ps
CPU time 776.7 seconds
Started Jul 19 07:13:57 PM PDT 24
Finished Jul 19 07:26:58 PM PDT 24
Peak memory 201748 kb
Host smart-10c7afae-6ca8-4a4d-8905-5c2330b8db5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254272671 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.2254272671
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.4044140170
Short name T260
Test name
Test status
Simulation time 499241057754 ps
CPU time 566.66 seconds
Started Jul 19 07:13:45 PM PDT 24
Finished Jul 19 07:23:16 PM PDT 24
Peak memory 201760 kb
Host smart-963f595b-cec7-4fb0-8509-bc83a7c5320c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044140170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.4044140170
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.942271986
Short name T389
Test name
Test status
Simulation time 501271002565 ps
CPU time 526.12 seconds
Started Jul 19 07:13:57 PM PDT 24
Finished Jul 19 07:22:48 PM PDT 24
Peak memory 201728 kb
Host smart-2e72e92f-eca3-4656-8f94-810e49defb50
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=942271986 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrup
t_fixed.942271986
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.715308745
Short name T87
Test name
Test status
Simulation time 492609017252 ps
CPU time 591.98 seconds
Started Jul 19 07:13:46 PM PDT 24
Finished Jul 19 07:23:42 PM PDT 24
Peak memory 201820 kb
Host smart-f85eaffa-1f89-4a9b-af4e-d831ea91eb73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715308745 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.715308745
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.2564634873
Short name T699
Test name
Test status
Simulation time 485159858171 ps
CPU time 172.1 seconds
Started Jul 19 07:13:47 PM PDT 24
Finished Jul 19 07:16:42 PM PDT 24
Peak memory 201808 kb
Host smart-991dc906-3d59-4672-9bc9-324317438908
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564634873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fix
ed.2564634873
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.3574282613
Short name T595
Test name
Test status
Simulation time 168952001906 ps
CPU time 46.81 seconds
Started Jul 19 07:13:57 PM PDT 24
Finished Jul 19 07:14:48 PM PDT 24
Peak memory 201776 kb
Host smart-cc10a5d8-fa87-4b5c-8f64-28711925ba12
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574282613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters
_wakeup.3574282613
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.3011722317
Short name T462
Test name
Test status
Simulation time 200387893164 ps
CPU time 245.69 seconds
Started Jul 19 07:13:58 PM PDT 24
Finished Jul 19 07:18:08 PM PDT 24
Peak memory 201740 kb
Host smart-fd2ad4cf-6cef-4373-8349-42f6aac51269
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011722317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.adc_ctrl_filters_wakeup_fixed.3011722317
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.1018084916
Short name T40
Test name
Test status
Simulation time 114982062534 ps
CPU time 437.09 seconds
Started Jul 19 07:14:12 PM PDT 24
Finished Jul 19 07:21:32 PM PDT 24
Peak memory 202108 kb
Host smart-7002980f-cbcb-4b5f-8aa8-5cfe40b4af06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018084916 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.1018084916
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.1600838114
Short name T359
Test name
Test status
Simulation time 33791464905 ps
CPU time 75.19 seconds
Started Jul 19 07:13:59 PM PDT 24
Finished Jul 19 07:15:18 PM PDT 24
Peak memory 201600 kb
Host smart-329640d0-b02e-4d7e-b4fb-ddcc5a1322be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600838114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.1600838114
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.515413878
Short name T538
Test name
Test status
Simulation time 4407643263 ps
CPU time 10.85 seconds
Started Jul 19 07:14:01 PM PDT 24
Finished Jul 19 07:14:14 PM PDT 24
Peak memory 201748 kb
Host smart-c1641dab-ff16-4d77-ad2c-c034a60a528e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515413878 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.515413878
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.2145366419
Short name T719
Test name
Test status
Simulation time 6191653997 ps
CPU time 8.58 seconds
Started Jul 19 07:13:45 PM PDT 24
Finished Jul 19 07:13:58 PM PDT 24
Peak memory 201604 kb
Host smart-937ef3e7-96e4-4709-9270-ef2608fb1d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145366419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.2145366419
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.730440898
Short name T184
Test name
Test status
Simulation time 620040635476 ps
CPU time 1854.84 seconds
Started Jul 19 07:14:13 PM PDT 24
Finished Jul 19 07:45:11 PM PDT 24
Peak memory 201608 kb
Host smart-53fdf258-eea5-4489-a7e9-757fe5e5d497
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730440898 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all.
730440898
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.1430299672
Short name T52
Test name
Test status
Simulation time 65774519157 ps
CPU time 151.02 seconds
Started Jul 19 07:14:09 PM PDT 24
Finished Jul 19 07:16:42 PM PDT 24
Peak memory 210448 kb
Host smart-344dc535-14a3-4979-836d-79b1fe701489
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430299672 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.1430299672
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.1389670998
Short name T454
Test name
Test status
Simulation time 399612980 ps
CPU time 0.84 seconds
Started Jul 19 07:14:11 PM PDT 24
Finished Jul 19 07:14:14 PM PDT 24
Peak memory 201548 kb
Host smart-3800b4d2-63d6-4017-bac7-7f1fab85fca3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389670998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.1389670998
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.133604697
Short name T208
Test name
Test status
Simulation time 350640897988 ps
CPU time 201.33 seconds
Started Jul 19 07:14:10 PM PDT 24
Finished Jul 19 07:17:34 PM PDT 24
Peak memory 201716 kb
Host smart-06a7819f-6a8a-45f4-8fd0-7bb9e4a814bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133604697 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.133604697
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.1735211612
Short name T441
Test name
Test status
Simulation time 325477956068 ps
CPU time 694.89 seconds
Started Jul 19 07:14:11 PM PDT 24
Finished Jul 19 07:25:48 PM PDT 24
Peak memory 201728 kb
Host smart-a73976c5-72e3-4cf1-bdee-cbded67aa82d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735211612 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interru
pt_fixed.1735211612
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.457913413
Short name T424
Test name
Test status
Simulation time 337254411520 ps
CPU time 381.29 seconds
Started Jul 19 07:14:11 PM PDT 24
Finished Jul 19 07:20:35 PM PDT 24
Peak memory 201732 kb
Host smart-ddda29f6-ae1e-4d88-bc4e-e84f46633a5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457913413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.457913413
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.1515264490
Short name T674
Test name
Test status
Simulation time 325895509131 ps
CPU time 776.42 seconds
Started Jul 19 07:14:11 PM PDT 24
Finished Jul 19 07:27:11 PM PDT 24
Peak memory 201716 kb
Host smart-14a9a549-a011-4e2c-b979-2cb6d50c975f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515264490 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fix
ed.1515264490
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.942994006
Short name T330
Test name
Test status
Simulation time 204136583774 ps
CPU time 122.84 seconds
Started Jul 19 07:14:14 PM PDT 24
Finished Jul 19 07:16:19 PM PDT 24
Peak memory 201756 kb
Host smart-58318ae6-a3f8-4a3b-8e0f-3635ffa12b52
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942994006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
adc_ctrl_filters_wakeup_fixed.942994006
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.3653065845
Short name T436
Test name
Test status
Simulation time 76015269574 ps
CPU time 440.95 seconds
Started Jul 19 07:14:11 PM PDT 24
Finished Jul 19 07:21:35 PM PDT 24
Peak memory 202116 kb
Host smart-1997c530-599d-4be9-b66d-630f25a06312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653065845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.3653065845
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.1583855943
Short name T647
Test name
Test status
Simulation time 27712683506 ps
CPU time 18.03 seconds
Started Jul 19 07:14:10 PM PDT 24
Finished Jul 19 07:14:31 PM PDT 24
Peak memory 201612 kb
Host smart-bbf26921-f303-405f-aa91-ea24fc4cd3ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583855943 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.1583855943
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.3845749440
Short name T724
Test name
Test status
Simulation time 4017037327 ps
CPU time 2.18 seconds
Started Jul 19 07:14:13 PM PDT 24
Finished Jul 19 07:14:18 PM PDT 24
Peak memory 201140 kb
Host smart-a2ee1dd9-588a-4c52-947b-6e80a4d9c5b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845749440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.3845749440
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.3982911719
Short name T414
Test name
Test status
Simulation time 5864450293 ps
CPU time 1.81 seconds
Started Jul 19 07:14:10 PM PDT 24
Finished Jul 19 07:14:15 PM PDT 24
Peak memory 201608 kb
Host smart-806fdfa1-cdd8-4c48-a47e-50a268930785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982911719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.3982911719
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.3949860587
Short name T292
Test name
Test status
Simulation time 259491688978 ps
CPU time 418.79 seconds
Started Jul 19 07:14:10 PM PDT 24
Finished Jul 19 07:21:12 PM PDT 24
Peak memory 212340 kb
Host smart-098e6286-3821-4177-a74d-c5177b8eea69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949860587 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all
.3949860587
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.184931921
Short name T583
Test name
Test status
Simulation time 28933478201 ps
CPU time 62.01 seconds
Started Jul 19 07:14:20 PM PDT 24
Finished Jul 19 07:15:23 PM PDT 24
Peak memory 217996 kb
Host smart-65f9b628-dc6d-4b89-ad51-fe4163ace8c0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184931921 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.184931921
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.1142737046
Short name T649
Test name
Test status
Simulation time 561683581 ps
CPU time 0.93 seconds
Started Jul 19 07:14:35 PM PDT 24
Finished Jul 19 07:14:39 PM PDT 24
Peak memory 201560 kb
Host smart-138d071d-1039-4879-af41-65bfebf22325
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142737046 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.1142737046
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.1430173653
Short name T171
Test name
Test status
Simulation time 331484457178 ps
CPU time 134.29 seconds
Started Jul 19 07:14:23 PM PDT 24
Finished Jul 19 07:16:41 PM PDT 24
Peak memory 201764 kb
Host smart-d3d8e0f6-827e-44ac-9643-411a1bd841bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430173653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.1430173653
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.194289943
Short name T508
Test name
Test status
Simulation time 163257261615 ps
CPU time 385.6 seconds
Started Jul 19 07:14:23 PM PDT 24
Finished Jul 19 07:20:53 PM PDT 24
Peak memory 201680 kb
Host smart-5f63d70b-0289-4520-b666-15b20fa6a107
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=194289943 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrup
t_fixed.194289943
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.2989674693
Short name T303
Test name
Test status
Simulation time 163394163929 ps
CPU time 396.99 seconds
Started Jul 19 07:14:23 PM PDT 24
Finished Jul 19 07:21:03 PM PDT 24
Peak memory 201748 kb
Host smart-3967db00-5828-4626-80a7-519e09b565fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989674693 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.2989674693
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.2302121749
Short name T409
Test name
Test status
Simulation time 159617586357 ps
CPU time 345.18 seconds
Started Jul 19 07:14:21 PM PDT 24
Finished Jul 19 07:20:08 PM PDT 24
Peak memory 201748 kb
Host smart-73661daf-2ad7-4ccd-a583-648bcaae1256
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302121749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fix
ed.2302121749
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.2420539726
Short name T263
Test name
Test status
Simulation time 330301838960 ps
CPU time 764.58 seconds
Started Jul 19 07:14:24 PM PDT 24
Finished Jul 19 07:27:13 PM PDT 24
Peak memory 201780 kb
Host smart-fc92d3bd-bd34-4aa7-91a1-1db099217ed0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420539726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters
_wakeup.2420539726
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.980055143
Short name T718
Test name
Test status
Simulation time 613650102967 ps
CPU time 988.63 seconds
Started Jul 19 07:14:21 PM PDT 24
Finished Jul 19 07:30:51 PM PDT 24
Peak memory 201688 kb
Host smart-65c9ef68-682c-442d-a12d-19f984f9680c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980055143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
adc_ctrl_filters_wakeup_fixed.980055143
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.3661926085
Short name T653
Test name
Test status
Simulation time 116349195591 ps
CPU time 617.36 seconds
Started Jul 19 07:14:35 PM PDT 24
Finished Jul 19 07:24:56 PM PDT 24
Peak memory 202108 kb
Host smart-800a64f1-f0ae-4d59-808d-60111e039aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661926085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.3661926085
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.1675650360
Short name T432
Test name
Test status
Simulation time 36012178691 ps
CPU time 48.06 seconds
Started Jul 19 07:14:38 PM PDT 24
Finished Jul 19 07:15:28 PM PDT 24
Peak memory 201612 kb
Host smart-05b33f72-b041-469c-9ab4-835ece3d3758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675650360 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.1675650360
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.2522933690
Short name T708
Test name
Test status
Simulation time 3319095992 ps
CPU time 7.3 seconds
Started Jul 19 07:14:36 PM PDT 24
Finished Jul 19 07:14:47 PM PDT 24
Peak memory 201612 kb
Host smart-73074a2a-9fe3-43a7-ab78-497df06770bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522933690 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.2522933690
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.1894062283
Short name T633
Test name
Test status
Simulation time 5851634840 ps
CPU time 4.7 seconds
Started Jul 19 07:14:23 PM PDT 24
Finished Jul 19 07:14:31 PM PDT 24
Peak memory 201624 kb
Host smart-736c9bee-5bf1-44ff-b4b7-bb1521083611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894062283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.1894062283
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.3103612731
Short name T571
Test name
Test status
Simulation time 44647671559 ps
CPU time 79.43 seconds
Started Jul 19 07:14:36 PM PDT 24
Finished Jul 19 07:15:59 PM PDT 24
Peak memory 210484 kb
Host smart-8d54d72d-c4a9-4614-9601-42210b1982a8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103612731 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.3103612731
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.588692100
Short name T503
Test name
Test status
Simulation time 352611301 ps
CPU time 0.87 seconds
Started Jul 19 07:14:52 PM PDT 24
Finished Jul 19 07:14:54 PM PDT 24
Peak memory 201540 kb
Host smart-a223121a-3240-4bda-b0b1-6e742dea657d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588692100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.588692100
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.1009424105
Short name T617
Test name
Test status
Simulation time 165986850399 ps
CPU time 214.45 seconds
Started Jul 19 07:14:37 PM PDT 24
Finished Jul 19 07:18:14 PM PDT 24
Peak memory 201740 kb
Host smart-a98fb1a7-6798-45c6-a014-b99fca559461
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009424105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gat
ing.1009424105
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.385028800
Short name T474
Test name
Test status
Simulation time 170238115595 ps
CPU time 192.33 seconds
Started Jul 19 07:14:53 PM PDT 24
Finished Jul 19 07:18:07 PM PDT 24
Peak memory 201820 kb
Host smart-f8de8f92-d587-4d20-a60d-9fb1fdf44b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385028800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.385028800
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.2876250267
Short name T309
Test name
Test status
Simulation time 480956722280 ps
CPU time 324.59 seconds
Started Jul 19 07:14:37 PM PDT 24
Finished Jul 19 07:20:04 PM PDT 24
Peak memory 201756 kb
Host smart-3a2211cf-9521-49cf-992c-456633c3985b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876250267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.2876250267
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.537097168
Short name T386
Test name
Test status
Simulation time 164635889752 ps
CPU time 148.01 seconds
Started Jul 19 07:14:37 PM PDT 24
Finished Jul 19 07:17:08 PM PDT 24
Peak memory 201720 kb
Host smart-8b01cb87-71ad-4cc7-88d4-d5fe761a5a7b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=537097168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrup
t_fixed.537097168
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.3568603994
Short name T254
Test name
Test status
Simulation time 325683854265 ps
CPU time 138.89 seconds
Started Jul 19 07:14:36 PM PDT 24
Finished Jul 19 07:16:58 PM PDT 24
Peak memory 201756 kb
Host smart-651bd774-4d07-41e2-bec3-95f41d9c3dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568603994 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.3568603994
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.3132741258
Short name T11
Test name
Test status
Simulation time 318493767886 ps
CPU time 165.6 seconds
Started Jul 19 07:14:35 PM PDT 24
Finished Jul 19 07:17:24 PM PDT 24
Peak memory 201700 kb
Host smart-cea2717b-4ee3-4899-b6b7-216db437862c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132741258 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fix
ed.3132741258
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.2453292792
Short name T390
Test name
Test status
Simulation time 385419401805 ps
CPU time 150.09 seconds
Started Jul 19 07:14:37 PM PDT 24
Finished Jul 19 07:17:10 PM PDT 24
Peak memory 201696 kb
Host smart-ca9465b4-c926-4c6e-bf3c-df7724237ecf
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453292792 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25
.adc_ctrl_filters_wakeup_fixed.2453292792
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.3443281217
Short name T659
Test name
Test status
Simulation time 80402250125 ps
CPU time 301.26 seconds
Started Jul 19 07:14:53 PM PDT 24
Finished Jul 19 07:19:56 PM PDT 24
Peak memory 202104 kb
Host smart-bef6ed3f-b896-4b10-bdad-909cbd180977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443281217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.3443281217
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.989105324
Short name T639
Test name
Test status
Simulation time 42925519973 ps
CPU time 24.92 seconds
Started Jul 19 07:14:51 PM PDT 24
Finished Jul 19 07:15:17 PM PDT 24
Peak memory 201588 kb
Host smart-fcf5f116-3968-4e3a-84c5-7464d1579e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989105324 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.989105324
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.3210530933
Short name T559
Test name
Test status
Simulation time 4973705414 ps
CPU time 12.44 seconds
Started Jul 19 07:14:52 PM PDT 24
Finished Jul 19 07:15:05 PM PDT 24
Peak memory 201620 kb
Host smart-15a8ec88-4276-47c4-a3a9-843d3fdca662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210530933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.3210530933
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.2507519784
Short name T535
Test name
Test status
Simulation time 5880322292 ps
CPU time 4.26 seconds
Started Jul 19 07:14:37 PM PDT 24
Finished Jul 19 07:14:44 PM PDT 24
Peak memory 201676 kb
Host smart-4f853474-055c-4e9c-976c-10278f1472a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507519784 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.2507519784
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.1627984059
Short name T410
Test name
Test status
Simulation time 108153437901 ps
CPU time 377.81 seconds
Started Jul 19 07:14:51 PM PDT 24
Finished Jul 19 07:21:10 PM PDT 24
Peak memory 202124 kb
Host smart-fd2f6bdf-7915-4695-8dad-3edbfe5a8549
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627984059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all
.1627984059
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.220078839
Short name T478
Test name
Test status
Simulation time 433359413 ps
CPU time 0.95 seconds
Started Jul 19 07:15:03 PM PDT 24
Finished Jul 19 07:15:07 PM PDT 24
Peak memory 201540 kb
Host smart-1000992d-0d12-4eeb-bf73-ef2365b5f01a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220078839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.220078839
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.3740006027
Short name T236
Test name
Test status
Simulation time 530477505450 ps
CPU time 221.85 seconds
Started Jul 19 07:15:03 PM PDT 24
Finished Jul 19 07:18:48 PM PDT 24
Peak memory 201744 kb
Host smart-8b3af171-c6ca-47eb-8d12-4f77c49807fb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740006027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gat
ing.3740006027
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.1656927552
Short name T139
Test name
Test status
Simulation time 365826304173 ps
CPU time 847.97 seconds
Started Jul 19 07:15:04 PM PDT 24
Finished Jul 19 07:29:15 PM PDT 24
Peak memory 201760 kb
Host smart-087a85d5-7060-44de-98c4-3c80d4025509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656927552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.1656927552
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.2877383770
Short name T312
Test name
Test status
Simulation time 493950951043 ps
CPU time 1096.83 seconds
Started Jul 19 07:15:05 PM PDT 24
Finished Jul 19 07:33:25 PM PDT 24
Peak memory 201812 kb
Host smart-a2e6fc2e-e3f4-439e-8573-3e6858f58587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877383770 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.2877383770
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.3302490220
Short name T748
Test name
Test status
Simulation time 166002185048 ps
CPU time 189.75 seconds
Started Jul 19 07:14:53 PM PDT 24
Finished Jul 19 07:18:04 PM PDT 24
Peak memory 201832 kb
Host smart-c5a0ffed-4282-442c-9c20-93a21a9ef970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302490220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.3302490220
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.4076860204
Short name T547
Test name
Test status
Simulation time 494885826452 ps
CPU time 324.85 seconds
Started Jul 19 07:15:05 PM PDT 24
Finished Jul 19 07:20:33 PM PDT 24
Peak memory 201728 kb
Host smart-c31d6d25-92d3-4b62-a61c-565fa9291691
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076860204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fix
ed.4076860204
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.2140764718
Short name T223
Test name
Test status
Simulation time 355171111532 ps
CPU time 110.5 seconds
Started Jul 19 07:15:03 PM PDT 24
Finished Jul 19 07:16:57 PM PDT 24
Peak memory 201784 kb
Host smart-49016ee1-d086-428a-99f6-f833acb090ca
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140764718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters
_wakeup.2140764718
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.3494383439
Short name T554
Test name
Test status
Simulation time 401892639127 ps
CPU time 954.56 seconds
Started Jul 19 07:15:02 PM PDT 24
Finished Jul 19 07:31:00 PM PDT 24
Peak memory 201784 kb
Host smart-7ddec922-1ea7-4c76-a6b5-cf2abb886cf2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494383439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.adc_ctrl_filters_wakeup_fixed.3494383439
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.2101139131
Short name T190
Test name
Test status
Simulation time 88762315074 ps
CPU time 286.78 seconds
Started Jul 19 07:15:02 PM PDT 24
Finished Jul 19 07:19:52 PM PDT 24
Peak memory 202236 kb
Host smart-6d75cdcc-d6d6-45f2-94a7-ab2aa31f0925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101139131 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.2101139131
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.3217652974
Short name T158
Test name
Test status
Simulation time 26836342349 ps
CPU time 16.38 seconds
Started Jul 19 07:15:04 PM PDT 24
Finished Jul 19 07:15:23 PM PDT 24
Peak memory 201608 kb
Host smart-dd8bee69-50fa-4cd3-900a-d2d7790f3dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217652974 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.3217652974
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.4286218470
Short name T445
Test name
Test status
Simulation time 2829127209 ps
CPU time 3.01 seconds
Started Jul 19 07:15:05 PM PDT 24
Finished Jul 19 07:15:12 PM PDT 24
Peak memory 201608 kb
Host smart-cae365be-25c5-49df-ae54-e5d25ebada86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286218470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.4286218470
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.727979988
Short name T153
Test name
Test status
Simulation time 6013296848 ps
CPU time 4.55 seconds
Started Jul 19 07:14:52 PM PDT 24
Finished Jul 19 07:14:57 PM PDT 24
Peak memory 201636 kb
Host smart-46836443-580a-4d55-9fa7-6ffdd5e1978c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727979988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.727979988
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.3892544984
Short name T762
Test name
Test status
Simulation time 350332189658 ps
CPU time 306.18 seconds
Started Jul 19 07:15:03 PM PDT 24
Finished Jul 19 07:20:13 PM PDT 24
Peak memory 201804 kb
Host smart-ce289db5-b403-4570-b054-778fc05b0547
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892544984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all
.3892544984
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.1037315701
Short name T604
Test name
Test status
Simulation time 24460730830 ps
CPU time 63.67 seconds
Started Jul 19 07:15:02 PM PDT 24
Finished Jul 19 07:16:09 PM PDT 24
Peak memory 210372 kb
Host smart-41dc9419-4ced-4e86-a98f-c1914753effc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037315701 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.1037315701
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.4214940876
Short name T422
Test name
Test status
Simulation time 390565810 ps
CPU time 1.55 seconds
Started Jul 19 07:15:13 PM PDT 24
Finished Jul 19 07:15:17 PM PDT 24
Peak memory 201556 kb
Host smart-c86ade7f-554c-4670-9f45-b1d60eee77c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214940876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.4214940876
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.657971092
Short name T293
Test name
Test status
Simulation time 248583806656 ps
CPU time 533.92 seconds
Started Jul 19 07:15:05 PM PDT 24
Finished Jul 19 07:24:03 PM PDT 24
Peak memory 201812 kb
Host smart-84aa1c36-86fc-449d-8710-28b67bc6c9a9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657971092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gati
ng.657971092
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.186585405
Short name T307
Test name
Test status
Simulation time 502811637466 ps
CPU time 106.86 seconds
Started Jul 19 07:15:06 PM PDT 24
Finished Jul 19 07:16:56 PM PDT 24
Peak memory 201740 kb
Host smart-0cc73fb3-ab4f-4f94-8a3d-683968a8b9ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186585405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.186585405
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.1105191161
Short name T318
Test name
Test status
Simulation time 483526042918 ps
CPU time 1093.51 seconds
Started Jul 19 07:15:07 PM PDT 24
Finished Jul 19 07:33:23 PM PDT 24
Peak memory 201756 kb
Host smart-bc371de0-415b-4fbf-bc1a-02c88b29fa40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105191161 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.1105191161
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.1488171028
Short name T534
Test name
Test status
Simulation time 167765331488 ps
CPU time 375.32 seconds
Started Jul 19 07:15:04 PM PDT 24
Finished Jul 19 07:21:23 PM PDT 24
Peak memory 201724 kb
Host smart-36dd552c-9c56-4d1c-a204-5400261cc78c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488171028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interru
pt_fixed.1488171028
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.1847547744
Short name T577
Test name
Test status
Simulation time 165954257715 ps
CPU time 340.09 seconds
Started Jul 19 07:15:05 PM PDT 24
Finished Jul 19 07:20:49 PM PDT 24
Peak memory 201812 kb
Host smart-bf5d7e9c-bba3-4db5-a673-2d0afa58668b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847547744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.1847547744
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.4234310367
Short name T513
Test name
Test status
Simulation time 330838890953 ps
CPU time 418.68 seconds
Started Jul 19 07:15:05 PM PDT 24
Finished Jul 19 07:22:07 PM PDT 24
Peak memory 201748 kb
Host smart-9ee63f60-c663-4450-a813-012fc6987063
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234310367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fix
ed.4234310367
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.2335247838
Short name T321
Test name
Test status
Simulation time 183235526267 ps
CPU time 88.95 seconds
Started Jul 19 07:15:05 PM PDT 24
Finished Jul 19 07:16:37 PM PDT 24
Peak memory 201832 kb
Host smart-37fdad3d-824d-46aa-adab-653ff517912e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335247838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters
_wakeup.2335247838
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.2183687812
Short name T722
Test name
Test status
Simulation time 108088563365 ps
CPU time 404.48 seconds
Started Jul 19 07:15:14 PM PDT 24
Finished Jul 19 07:22:01 PM PDT 24
Peak memory 202200 kb
Host smart-7fdb0adc-1a84-4f04-a508-384d5b93d9eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183687812 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.2183687812
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.3753680099
Short name T334
Test name
Test status
Simulation time 30257018791 ps
CPU time 75.32 seconds
Started Jul 19 07:15:05 PM PDT 24
Finished Jul 19 07:16:24 PM PDT 24
Peak memory 201584 kb
Host smart-b80dba5a-ae5d-40a6-a29e-0c64f6ea0d68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753680099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.3753680099
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.2489149235
Short name T339
Test name
Test status
Simulation time 3084601841 ps
CPU time 3.54 seconds
Started Jul 19 07:15:02 PM PDT 24
Finished Jul 19 07:15:09 PM PDT 24
Peak memory 201600 kb
Host smart-8a037e47-7206-49be-a97f-e055c96bef98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489149235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.2489149235
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.2419124687
Short name T404
Test name
Test status
Simulation time 5793691867 ps
CPU time 13.44 seconds
Started Jul 19 07:15:04 PM PDT 24
Finished Jul 19 07:15:21 PM PDT 24
Peak memory 201596 kb
Host smart-972a2a85-c014-4811-a562-0b036375a69f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419124687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.2419124687
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.2500151200
Short name T589
Test name
Test status
Simulation time 340288050118 ps
CPU time 213.9 seconds
Started Jul 19 07:15:11 PM PDT 24
Finished Jul 19 07:18:47 PM PDT 24
Peak memory 201896 kb
Host smart-56d246a6-9e59-45ca-a978-35a0e4372a12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500151200 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all
.2500151200
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.274188616
Short name T207
Test name
Test status
Simulation time 387027645806 ps
CPU time 207.1 seconds
Started Jul 19 07:15:13 PM PDT 24
Finished Jul 19 07:18:43 PM PDT 24
Peak memory 210496 kb
Host smart-98d12a5d-1676-4637-9383-aa799b664100
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274188616 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.274188616
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.1303993004
Short name T347
Test name
Test status
Simulation time 385607703 ps
CPU time 0.87 seconds
Started Jul 19 07:15:26 PM PDT 24
Finished Jul 19 07:15:28 PM PDT 24
Peak memory 201568 kb
Host smart-373a0cf4-c772-423b-bf90-1c7ac0a4fe7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303993004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.1303993004
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.2216037292
Short name T713
Test name
Test status
Simulation time 492974164933 ps
CPU time 191.32 seconds
Started Jul 19 07:15:15 PM PDT 24
Finished Jul 19 07:18:29 PM PDT 24
Peak memory 201792 kb
Host smart-4cbdba4a-b1b9-4b98-803e-c92ceb6e1225
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216037292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gat
ing.2216037292
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.2475936439
Short name T164
Test name
Test status
Simulation time 325013019410 ps
CPU time 195.95 seconds
Started Jul 19 07:15:13 PM PDT 24
Finished Jul 19 07:18:31 PM PDT 24
Peak memory 201728 kb
Host smart-e89cc663-2ded-47c9-8ecd-742b71c84b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475936439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.2475936439
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.2191226538
Short name T597
Test name
Test status
Simulation time 161472037663 ps
CPU time 107.32 seconds
Started Jul 19 07:15:14 PM PDT 24
Finished Jul 19 07:17:04 PM PDT 24
Peak memory 201748 kb
Host smart-844f3429-fa28-4b56-abc3-eb1fb2ba0dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191226538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.2191226538
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.2454214071
Short name T96
Test name
Test status
Simulation time 498334024632 ps
CPU time 1206.63 seconds
Started Jul 19 07:15:15 PM PDT 24
Finished Jul 19 07:35:23 PM PDT 24
Peak memory 201720 kb
Host smart-4a0a872c-b24c-4315-af27-0392c436c7d7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454214071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interru
pt_fixed.2454214071
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.1381712905
Short name T449
Test name
Test status
Simulation time 340648702550 ps
CPU time 192.81 seconds
Started Jul 19 07:15:12 PM PDT 24
Finished Jul 19 07:18:26 PM PDT 24
Peak memory 201812 kb
Host smart-bc01ef5d-9eed-4828-b47b-94b3b2bd571d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381712905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fix
ed.1381712905
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.760767852
Short name T10
Test name
Test status
Simulation time 188309556799 ps
CPU time 433.48 seconds
Started Jul 19 07:15:14 PM PDT 24
Finished Jul 19 07:22:30 PM PDT 24
Peak memory 201756 kb
Host smart-f7e6e039-fd19-469f-b452-da4cb6a71cc1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760767852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_
wakeup.760767852
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.1531112075
Short name T399
Test name
Test status
Simulation time 606452480447 ps
CPU time 1385.14 seconds
Started Jul 19 07:15:13 PM PDT 24
Finished Jul 19 07:38:21 PM PDT 24
Peak memory 201572 kb
Host smart-415f13d7-afae-4607-95bb-4dfb3772b2ad
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531112075 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.adc_ctrl_filters_wakeup_fixed.1531112075
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.1966489746
Short name T39
Test name
Test status
Simulation time 105654094976 ps
CPU time 347.58 seconds
Started Jul 19 07:15:25 PM PDT 24
Finished Jul 19 07:21:14 PM PDT 24
Peak memory 202128 kb
Host smart-5a562697-1fde-46e0-bb71-1e3a30d3a3d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966489746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.1966489746
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.3853361634
Short name T620
Test name
Test status
Simulation time 24717529625 ps
CPU time 31.15 seconds
Started Jul 19 07:15:16 PM PDT 24
Finished Jul 19 07:15:48 PM PDT 24
Peak memory 201600 kb
Host smart-a4273701-0739-4baa-8fd2-197461f04127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853361634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.3853361634
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.3510340531
Short name T420
Test name
Test status
Simulation time 4101356316 ps
CPU time 5.54 seconds
Started Jul 19 07:15:15 PM PDT 24
Finished Jul 19 07:15:22 PM PDT 24
Peak memory 201592 kb
Host smart-60e6e1df-aa29-4468-ab19-57fbc3f1b90c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510340531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.3510340531
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.550954246
Short name T737
Test name
Test status
Simulation time 5714743664 ps
CPU time 15.86 seconds
Started Jul 19 07:15:13 PM PDT 24
Finished Jul 19 07:15:32 PM PDT 24
Peak memory 201424 kb
Host smart-34fa2653-051b-4349-9643-ddf8dcb168a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550954246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.550954246
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.43220638
Short name T756
Test name
Test status
Simulation time 174665152214 ps
CPU time 49.53 seconds
Started Jul 19 07:15:25 PM PDT 24
Finished Jul 19 07:16:16 PM PDT 24
Peak memory 201736 kb
Host smart-04b5a213-ffde-470e-8188-4ce68dd1165b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43220638 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all.43220638
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.3628349029
Short name T690
Test name
Test status
Simulation time 197627968973 ps
CPU time 193.35 seconds
Started Jul 19 07:15:26 PM PDT 24
Finished Jul 19 07:18:41 PM PDT 24
Peak memory 210644 kb
Host smart-46636a99-5ace-4d56-9307-21b5a28c6354
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628349029 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.3628349029
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.3829930143
Short name T685
Test name
Test status
Simulation time 469129091 ps
CPU time 1.62 seconds
Started Jul 19 07:15:39 PM PDT 24
Finished Jul 19 07:15:43 PM PDT 24
Peak memory 201504 kb
Host smart-a59ecc80-2761-4a66-b3a2-fad35d6c8a1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829930143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.3829930143
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.1552466854
Short name T296
Test name
Test status
Simulation time 367843506820 ps
CPU time 855.19 seconds
Started Jul 19 07:15:41 PM PDT 24
Finished Jul 19 07:29:58 PM PDT 24
Peak memory 201804 kb
Host smart-ae7b17f2-dbcc-4415-9bd8-7174a8a25869
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552466854 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gat
ing.1552466854
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.3056366345
Short name T37
Test name
Test status
Simulation time 164480369731 ps
CPU time 334.72 seconds
Started Jul 19 07:15:38 PM PDT 24
Finished Jul 19 07:21:16 PM PDT 24
Peak memory 201956 kb
Host smart-0a9a50da-4596-4124-bf39-b1302488efe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056366345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.3056366345
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.1902070634
Short name T284
Test name
Test status
Simulation time 475904401847 ps
CPU time 243.06 seconds
Started Jul 19 07:15:57 PM PDT 24
Finished Jul 19 07:20:01 PM PDT 24
Peak memory 201756 kb
Host smart-9d5411fe-dd11-4d9c-8039-8987c1e96cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902070634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.1902070634
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.3555980731
Short name T458
Test name
Test status
Simulation time 164845728357 ps
CPU time 207.51 seconds
Started Jul 19 07:15:50 PM PDT 24
Finished Jul 19 07:19:18 PM PDT 24
Peak memory 201728 kb
Host smart-14a5dfef-5e4d-49ff-bcb4-1188e9e431ba
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555980731 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interru
pt_fixed.3555980731
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.2923471647
Short name T751
Test name
Test status
Simulation time 163294311878 ps
CPU time 183.1 seconds
Started Jul 19 07:15:25 PM PDT 24
Finished Jul 19 07:18:29 PM PDT 24
Peak memory 201812 kb
Host smart-2b668189-4b21-4fa9-b6af-59a26a27722e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923471647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.2923471647
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.496482714
Short name T71
Test name
Test status
Simulation time 498591106328 ps
CPU time 591.17 seconds
Started Jul 19 07:15:25 PM PDT 24
Finished Jul 19 07:25:17 PM PDT 24
Peak memory 201744 kb
Host smart-683d6e86-f5a6-41de-ad9b-b6c7c679b300
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=496482714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fixe
d.496482714
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.741073243
Short name T673
Test name
Test status
Simulation time 404291584536 ps
CPU time 229.18 seconds
Started Jul 19 07:15:41 PM PDT 24
Finished Jul 19 07:19:32 PM PDT 24
Peak memory 201808 kb
Host smart-7dea55d1-3e4e-4571-903c-57ed399db095
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741073243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
adc_ctrl_filters_wakeup_fixed.741073243
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.2917526953
Short name T179
Test name
Test status
Simulation time 105998603102 ps
CPU time 442.87 seconds
Started Jul 19 07:15:40 PM PDT 24
Finished Jul 19 07:23:05 PM PDT 24
Peak memory 202204 kb
Host smart-8c692edd-6fcb-45c0-bbb1-8e4db83559a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917526953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.2917526953
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.4186018550
Short name T493
Test name
Test status
Simulation time 27898793806 ps
CPU time 67.84 seconds
Started Jul 19 07:15:41 PM PDT 24
Finished Jul 19 07:16:51 PM PDT 24
Peak memory 201600 kb
Host smart-0413b277-c6f4-44ff-b16e-f589382c7d18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186018550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.4186018550
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.3179771909
Short name T736
Test name
Test status
Simulation time 4096064504 ps
CPU time 3.43 seconds
Started Jul 19 07:15:40 PM PDT 24
Finished Jul 19 07:15:46 PM PDT 24
Peak memory 201616 kb
Host smart-e357407f-ed1d-4345-925d-67fd860a193b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179771909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.3179771909
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.3200480307
Short name T378
Test name
Test status
Simulation time 5815352130 ps
CPU time 4.27 seconds
Started Jul 19 07:15:26 PM PDT 24
Finished Jul 19 07:15:31 PM PDT 24
Peak memory 201628 kb
Host smart-329a710d-8d65-4d62-966a-f80b387c11a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200480307 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.3200480307
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.620434243
Short name T178
Test name
Test status
Simulation time 54769312517 ps
CPU time 39.09 seconds
Started Jul 19 07:15:43 PM PDT 24
Finished Jul 19 07:16:23 PM PDT 24
Peak memory 210516 kb
Host smart-188ad378-aceb-45ad-9b1b-fe868ce567b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620434243 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.620434243
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.3320844603
Short name T60
Test name
Test status
Simulation time 334188852 ps
CPU time 1.12 seconds
Started Jul 19 07:07:08 PM PDT 24
Finished Jul 19 07:07:11 PM PDT 24
Peak memory 201568 kb
Host smart-6210f416-b9e5-41b4-8994-d737ef35b65b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320844603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.3320844603
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.2849964297
Short name T143
Test name
Test status
Simulation time 158407159629 ps
CPU time 353.14 seconds
Started Jul 19 07:06:52 PM PDT 24
Finished Jul 19 07:12:46 PM PDT 24
Peak memory 201760 kb
Host smart-dafe4ea9-33be-4412-8ada-89370c6de105
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849964297 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gati
ng.2849964297
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.2056169205
Short name T316
Test name
Test status
Simulation time 492421353641 ps
CPU time 337.3 seconds
Started Jul 19 07:06:46 PM PDT 24
Finished Jul 19 07:12:24 PM PDT 24
Peak memory 201800 kb
Host smart-5c23315d-d711-4b87-8b9f-8bd6af342b1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056169205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.2056169205
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.76935728
Short name T423
Test name
Test status
Simulation time 324051247974 ps
CPU time 797.71 seconds
Started Jul 19 07:06:58 PM PDT 24
Finished Jul 19 07:20:18 PM PDT 24
Peak memory 201708 kb
Host smart-4ca35461-8cd6-46d4-b08e-da9a66168366
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=76935728 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt_
fixed.76935728
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.2388477117
Short name T568
Test name
Test status
Simulation time 164178993436 ps
CPU time 23.45 seconds
Started Jul 19 07:06:51 PM PDT 24
Finished Jul 19 07:07:15 PM PDT 24
Peak memory 201704 kb
Host smart-793592d2-a461-44e4-ba18-a6146d440699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388477117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.2388477117
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.1589146106
Short name T373
Test name
Test status
Simulation time 162244478406 ps
CPU time 83 seconds
Started Jul 19 07:06:42 PM PDT 24
Finished Jul 19 07:08:06 PM PDT 24
Peak memory 201760 kb
Host smart-3e3fb549-4d2f-46fb-adf4-05a4671fdeaf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589146106 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixe
d.1589146106
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.597741779
Short name T163
Test name
Test status
Simulation time 619598043303 ps
CPU time 359.28 seconds
Started Jul 19 07:06:53 PM PDT 24
Finished Jul 19 07:12:54 PM PDT 24
Peak memory 201752 kb
Host smart-9a44d821-3646-433d-8b4d-ddc88239ac8f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597741779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_w
akeup.597741779
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.3480693465
Short name T509
Test name
Test status
Simulation time 402086139600 ps
CPU time 153.21 seconds
Started Jul 19 07:06:50 PM PDT 24
Finished Jul 19 07:09:24 PM PDT 24
Peak memory 201728 kb
Host smart-bac87d52-315a-4e80-b8cc-beeea92f8f53
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480693465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
adc_ctrl_filters_wakeup_fixed.3480693465
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.4172148881
Short name T717
Test name
Test status
Simulation time 80149381472 ps
CPU time 448.49 seconds
Started Jul 19 07:07:01 PM PDT 24
Finished Jul 19 07:14:31 PM PDT 24
Peak memory 202112 kb
Host smart-f2f0e060-13c9-4af8-93b4-2cf48579b70b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172148881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.4172148881
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.3613602030
Short name T156
Test name
Test status
Simulation time 26065450875 ps
CPU time 57.11 seconds
Started Jul 19 07:06:59 PM PDT 24
Finished Jul 19 07:07:58 PM PDT 24
Peak memory 201656 kb
Host smart-4ef9f0af-1c4e-4c0e-aa41-6ff57a7bc3d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613602030 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.3613602030
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.1583029815
Short name T336
Test name
Test status
Simulation time 3140835287 ps
CPU time 9.25 seconds
Started Jul 19 07:07:03 PM PDT 24
Finished Jul 19 07:07:13 PM PDT 24
Peak memory 201572 kb
Host smart-7ebd0632-99cc-4914-b6fb-88fc22f1c719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583029815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.1583029815
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.4241081281
Short name T68
Test name
Test status
Simulation time 8087954149 ps
CPU time 19.92 seconds
Started Jul 19 07:06:59 PM PDT 24
Finished Jul 19 07:07:21 PM PDT 24
Peak memory 218304 kb
Host smart-64245813-ce98-4f4a-bd65-ef63b845f9ec
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241081281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.4241081281
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.3078347753
Short name T651
Test name
Test status
Simulation time 5959167482 ps
CPU time 15.39 seconds
Started Jul 19 07:06:42 PM PDT 24
Finished Jul 19 07:06:58 PM PDT 24
Peak memory 201608 kb
Host smart-d8a945db-29e3-4321-aec6-410b0e630aa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078347753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.3078347753
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.1781526941
Short name T565
Test name
Test status
Simulation time 343403323825 ps
CPU time 815.63 seconds
Started Jul 19 07:06:56 PM PDT 24
Finished Jul 19 07:20:34 PM PDT 24
Peak memory 201712 kb
Host smart-056b862b-b85c-4813-bce0-ad97e56aa6d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781526941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.
1781526941
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.2851357984
Short name T709
Test name
Test status
Simulation time 358443342 ps
CPU time 0.8 seconds
Started Jul 19 07:16:06 PM PDT 24
Finished Jul 19 07:16:14 PM PDT 24
Peak memory 201528 kb
Host smart-5576922e-ef53-4db2-a93a-74d884138168
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851357984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.2851357984
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.2080400258
Short name T315
Test name
Test status
Simulation time 169639700259 ps
CPU time 104.11 seconds
Started Jul 19 07:16:08 PM PDT 24
Finished Jul 19 07:17:59 PM PDT 24
Peak memory 201756 kb
Host smart-c8642bd3-29c6-4184-aaa6-22ddc5fbd723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080400258 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.2080400258
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.1986626383
Short name T734
Test name
Test status
Simulation time 323123461061 ps
CPU time 106.24 seconds
Started Jul 19 07:16:06 PM PDT 24
Finished Jul 19 07:18:00 PM PDT 24
Peak memory 201724 kb
Host smart-11abc21b-921d-4964-b157-249b91354335
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986626383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interru
pt_fixed.1986626383
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.633378594
Short name T72
Test name
Test status
Simulation time 165365618652 ps
CPU time 106.18 seconds
Started Jul 19 07:15:40 PM PDT 24
Finished Jul 19 07:17:28 PM PDT 24
Peak memory 201768 kb
Host smart-2a27dd90-8b68-4e47-ada4-5334f03e1a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633378594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.633378594
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.1295421325
Short name T572
Test name
Test status
Simulation time 165338537625 ps
CPU time 51.14 seconds
Started Jul 19 07:16:06 PM PDT 24
Finished Jul 19 07:17:04 PM PDT 24
Peak memory 201796 kb
Host smart-700032e1-55cf-4ab6-93db-26c9fc581fec
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295421325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fix
ed.1295421325
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.3068363357
Short name T439
Test name
Test status
Simulation time 378270248061 ps
CPU time 541.24 seconds
Started Jul 19 07:16:07 PM PDT 24
Finished Jul 19 07:25:16 PM PDT 24
Peak memory 201756 kb
Host smart-c68a80cf-0213-4388-8df8-99eb355cc73f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068363357 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters
_wakeup.3068363357
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.1898155968
Short name T530
Test name
Test status
Simulation time 605859042498 ps
CPU time 686.69 seconds
Started Jul 19 07:16:06 PM PDT 24
Finished Jul 19 07:27:40 PM PDT 24
Peak memory 201732 kb
Host smart-9a971638-10d1-4a4a-8dc6-4613f17be9d5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898155968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.adc_ctrl_filters_wakeup_fixed.1898155968
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.314533267
Short name T92
Test name
Test status
Simulation time 93494655313 ps
CPU time 324.56 seconds
Started Jul 19 07:16:08 PM PDT 24
Finished Jul 19 07:21:39 PM PDT 24
Peak memory 202120 kb
Host smart-f82dd083-be05-4047-9206-1dc9600bec31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314533267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.314533267
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.3733488520
Short name T704
Test name
Test status
Simulation time 30953385549 ps
CPU time 70 seconds
Started Jul 19 07:16:06 PM PDT 24
Finished Jul 19 07:17:24 PM PDT 24
Peak memory 201620 kb
Host smart-e419b387-54d5-439d-9d7f-3ec537ac35e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733488520 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.3733488520
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.3933112881
Short name T654
Test name
Test status
Simulation time 3374107475 ps
CPU time 9.19 seconds
Started Jul 19 07:16:07 PM PDT 24
Finished Jul 19 07:16:23 PM PDT 24
Peak memory 201604 kb
Host smart-a653d93e-1a65-4e22-9dcf-aa278f2359cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933112881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.3933112881
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.345970630
Short name T446
Test name
Test status
Simulation time 5944513490 ps
CPU time 4.38 seconds
Started Jul 19 07:15:41 PM PDT 24
Finished Jul 19 07:15:47 PM PDT 24
Peak memory 201628 kb
Host smart-20ebea05-4ee1-47b3-b5cf-ce07ecb3707a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345970630 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.345970630
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.1957482745
Short name T545
Test name
Test status
Simulation time 177542916731 ps
CPU time 447.77 seconds
Started Jul 19 07:16:05 PM PDT 24
Finished Jul 19 07:23:40 PM PDT 24
Peak memory 201800 kb
Host smart-460def9b-ff72-4ae3-8957-a99de1fae9dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957482745 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all
.1957482745
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.1408671488
Short name T696
Test name
Test status
Simulation time 262467791711 ps
CPU time 199.21 seconds
Started Jul 19 07:16:07 PM PDT 24
Finished Jul 19 07:19:33 PM PDT 24
Peak memory 210452 kb
Host smart-de54bd61-e27f-490f-aeef-26b4a61c3055
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408671488 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.1408671488
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.2840368747
Short name T356
Test name
Test status
Simulation time 365989061 ps
CPU time 1.54 seconds
Started Jul 19 07:16:22 PM PDT 24
Finished Jul 19 07:16:30 PM PDT 24
Peak memory 201548 kb
Host smart-587d53c2-a3cf-45a8-8f9c-4711a60b0b5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840368747 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.2840368747
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.3252872333
Short name T640
Test name
Test status
Simulation time 377496793985 ps
CPU time 739.44 seconds
Started Jul 19 07:16:07 PM PDT 24
Finished Jul 19 07:28:34 PM PDT 24
Peak memory 201808 kb
Host smart-be9d7374-fb91-4086-bc59-4ecdff6dc0f7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252872333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gat
ing.3252872333
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.925579643
Short name T641
Test name
Test status
Simulation time 496074771512 ps
CPU time 279.03 seconds
Started Jul 19 07:16:08 PM PDT 24
Finished Jul 19 07:20:54 PM PDT 24
Peak memory 201760 kb
Host smart-c22a3545-292b-4253-9986-51d0544a11e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925579643 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.925579643
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.65478325
Short name T562
Test name
Test status
Simulation time 326891538013 ps
CPU time 405.94 seconds
Started Jul 19 07:16:05 PM PDT 24
Finished Jul 19 07:22:58 PM PDT 24
Peak memory 201712 kb
Host smart-6913ef62-ace2-451d-9e5f-ef82f6be57c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65478325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.65478325
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.886916952
Short name T333
Test name
Test status
Simulation time 495915615528 ps
CPU time 353.72 seconds
Started Jul 19 07:16:09 PM PDT 24
Finished Jul 19 07:22:09 PM PDT 24
Peak memory 201724 kb
Host smart-7b42f548-1f5c-4bfc-9ced-9f15c59cfd86
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=886916952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrup
t_fixed.886916952
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.844702695
Short name T230
Test name
Test status
Simulation time 494109677192 ps
CPU time 1164.97 seconds
Started Jul 19 07:16:07 PM PDT 24
Finished Jul 19 07:35:39 PM PDT 24
Peak memory 201768 kb
Host smart-126ad69a-2b71-4c0b-b536-4cb66cba5aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844702695 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.844702695
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.2337101120
Short name T522
Test name
Test status
Simulation time 163736025767 ps
CPU time 103.58 seconds
Started Jul 19 07:16:07 PM PDT 24
Finished Jul 19 07:17:58 PM PDT 24
Peak memory 201732 kb
Host smart-298c5b60-828e-4a7e-86c8-ea1012d576ff
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337101120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fix
ed.2337101120
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.3908978013
Short name T723
Test name
Test status
Simulation time 367352358889 ps
CPU time 399.52 seconds
Started Jul 19 07:16:07 PM PDT 24
Finished Jul 19 07:22:54 PM PDT 24
Peak memory 201748 kb
Host smart-5fa00437-f02e-4f5f-b4c2-13c9a845a2b5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908978013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters
_wakeup.3908978013
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.515521694
Short name T433
Test name
Test status
Simulation time 578245512729 ps
CPU time 315.63 seconds
Started Jul 19 07:16:04 PM PDT 24
Finished Jul 19 07:21:27 PM PDT 24
Peak memory 201744 kb
Host smart-b5e2e671-5862-4bcf-89f6-4ba1b387d2b0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515521694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
adc_ctrl_filters_wakeup_fixed.515521694
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.3365848648
Short name T327
Test name
Test status
Simulation time 107373537276 ps
CPU time 536.52 seconds
Started Jul 19 07:16:05 PM PDT 24
Finished Jul 19 07:25:08 PM PDT 24
Peak memory 202144 kb
Host smart-3f3c194f-b5c4-499a-acb7-f2d8cc128ede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365848648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.3365848648
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.2998016659
Short name T761
Test name
Test status
Simulation time 37739493537 ps
CPU time 11.03 seconds
Started Jul 19 07:16:09 PM PDT 24
Finished Jul 19 07:16:26 PM PDT 24
Peak memory 201568 kb
Host smart-c3afb4f7-3e01-4a81-8f7d-06ad4504642e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998016659 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.2998016659
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.2421088290
Short name T563
Test name
Test status
Simulation time 4470358261 ps
CPU time 6.58 seconds
Started Jul 19 07:16:11 PM PDT 24
Finished Jul 19 07:16:22 PM PDT 24
Peak memory 201612 kb
Host smart-5d8588ab-9675-491e-94e3-b3993c7b9968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421088290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.2421088290
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.1462539718
Short name T341
Test name
Test status
Simulation time 6014536914 ps
CPU time 4.68 seconds
Started Jul 19 07:15:51 PM PDT 24
Finished Jul 19 07:15:57 PM PDT 24
Peak memory 201664 kb
Host smart-44de94d6-f1a9-44c2-b946-42d9fb57131e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462539718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.1462539718
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.1280048863
Short name T154
Test name
Test status
Simulation time 165259060034 ps
CPU time 372.61 seconds
Started Jul 19 07:16:20 PM PDT 24
Finished Jul 19 07:22:41 PM PDT 24
Peak memory 201808 kb
Host smart-f62618d1-13f7-4de1-968b-6f4b95a51896
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280048863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all
.1280048863
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.3837600767
Short name T397
Test name
Test status
Simulation time 474838462 ps
CPU time 1 seconds
Started Jul 19 07:16:20 PM PDT 24
Finished Jul 19 07:16:29 PM PDT 24
Peak memory 201548 kb
Host smart-bb7cb231-3c0f-40ca-9e4a-04686cb7fd0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837600767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.3837600767
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.3815850336
Short name T314
Test name
Test status
Simulation time 332375926770 ps
CPU time 804.2 seconds
Started Jul 19 07:16:21 PM PDT 24
Finished Jul 19 07:29:52 PM PDT 24
Peak memory 201760 kb
Host smart-54706445-ac2a-49ab-af6b-663a3b16a4da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815850336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.3815850336
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.362532342
Short name T757
Test name
Test status
Simulation time 488655324042 ps
CPU time 566.24 seconds
Started Jul 19 07:16:23 PM PDT 24
Finished Jul 19 07:25:57 PM PDT 24
Peak memory 201716 kb
Host smart-7c5598ad-de30-49bb-b7f6-7741b4191838
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=362532342 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrup
t_fixed.362532342
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.2123631068
Short name T7
Test name
Test status
Simulation time 168591713196 ps
CPU time 386.05 seconds
Started Jul 19 07:16:24 PM PDT 24
Finished Jul 19 07:22:58 PM PDT 24
Peak memory 201836 kb
Host smart-6acc4703-84f1-45d5-96b2-4aafc5f41537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123631068 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.2123631068
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.2977368419
Short name T437
Test name
Test status
Simulation time 165808349204 ps
CPU time 396.24 seconds
Started Jul 19 07:16:19 PM PDT 24
Finished Jul 19 07:23:03 PM PDT 24
Peak memory 201728 kb
Host smart-8a7afcdc-7c37-45ca-bedc-b1d01bd4e2b8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977368419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fix
ed.2977368419
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.4140936503
Short name T728
Test name
Test status
Simulation time 603851016138 ps
CPU time 567.93 seconds
Started Jul 19 07:16:22 PM PDT 24
Finished Jul 19 07:25:57 PM PDT 24
Peak memory 201772 kb
Host smart-2fa14eb7-294f-43fc-abfa-6a59379ca909
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140936503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters
_wakeup.4140936503
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.2927852706
Short name T9
Test name
Test status
Simulation time 201782137468 ps
CPU time 491.79 seconds
Started Jul 19 07:16:20 PM PDT 24
Finished Jul 19 07:24:39 PM PDT 24
Peak memory 201732 kb
Host smart-303058dc-7b33-41df-9632-1f0310b36b57
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927852706 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.adc_ctrl_filters_wakeup_fixed.2927852706
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.4273641847
Short name T157
Test name
Test status
Simulation time 44526547933 ps
CPU time 21.26 seconds
Started Jul 19 07:16:24 PM PDT 24
Finished Jul 19 07:16:53 PM PDT 24
Peak memory 201624 kb
Host smart-944f22b7-3cb3-4dbe-ae29-5bd128a4e655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273641847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.4273641847
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.1360445669
Short name T660
Test name
Test status
Simulation time 3622056722 ps
CPU time 8.41 seconds
Started Jul 19 07:16:24 PM PDT 24
Finished Jul 19 07:16:40 PM PDT 24
Peak memory 201628 kb
Host smart-a78afb3a-5341-4e7e-aa11-f5809aacf993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360445669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.1360445669
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.1412113192
Short name T413
Test name
Test status
Simulation time 5485882844 ps
CPU time 4.2 seconds
Started Jul 19 07:16:24 PM PDT 24
Finished Jul 19 07:16:36 PM PDT 24
Peak memory 201340 kb
Host smart-b0bd5666-a5f2-4070-94ad-571e15adb347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412113192 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.1412113192
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.1948182583
Short name T569
Test name
Test status
Simulation time 365717468665 ps
CPU time 822.28 seconds
Started Jul 19 07:16:20 PM PDT 24
Finished Jul 19 07:30:10 PM PDT 24
Peak memory 201696 kb
Host smart-58449368-30a8-4709-9f5d-c1a314db6319
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948182583 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all
.1948182583
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.1509378313
Short name T566
Test name
Test status
Simulation time 146514389085 ps
CPU time 293.85 seconds
Started Jul 19 07:16:22 PM PDT 24
Finished Jul 19 07:21:23 PM PDT 24
Peak memory 210456 kb
Host smart-95ee0765-f903-421d-8e14-a17aae35918b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509378313 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.1509378313
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.3833740849
Short name T498
Test name
Test status
Simulation time 354179300 ps
CPU time 1.1 seconds
Started Jul 19 07:16:33 PM PDT 24
Finished Jul 19 07:16:42 PM PDT 24
Peak memory 201560 kb
Host smart-549ac9b3-ebfa-41f8-add1-7a3f792c1e8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833740849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.3833740849
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.3631908764
Short name T203
Test name
Test status
Simulation time 165419934958 ps
CPU time 151.4 seconds
Started Jul 19 07:16:24 PM PDT 24
Finished Jul 19 07:19:03 PM PDT 24
Peak memory 201764 kb
Host smart-95a653bb-8bc3-4466-ac8d-56c7e7c061ed
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631908764 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gat
ing.3631908764
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.567773046
Short name T578
Test name
Test status
Simulation time 342793727706 ps
CPU time 200.82 seconds
Started Jul 19 07:16:22 PM PDT 24
Finished Jul 19 07:19:50 PM PDT 24
Peak memory 201768 kb
Host smart-c9a70901-6296-4d82-8912-6162353f211d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567773046 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.567773046
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.183651136
Short name T256
Test name
Test status
Simulation time 487765287367 ps
CPU time 609.18 seconds
Started Jul 19 07:16:24 PM PDT 24
Finished Jul 19 07:26:41 PM PDT 24
Peak memory 201404 kb
Host smart-cb52452f-88df-4936-9ac7-3054b6621e4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183651136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.183651136
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.2214477224
Short name T773
Test name
Test status
Simulation time 493869205346 ps
CPU time 314.9 seconds
Started Jul 19 07:16:22 PM PDT 24
Finished Jul 19 07:21:44 PM PDT 24
Peak memory 201740 kb
Host smart-ea69f6a0-34c1-4254-ade8-41a9037ab566
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214477224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interru
pt_fixed.2214477224
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.590954880
Short name T764
Test name
Test status
Simulation time 326276364540 ps
CPU time 784.93 seconds
Started Jul 19 07:16:21 PM PDT 24
Finished Jul 19 07:29:33 PM PDT 24
Peak memory 201840 kb
Host smart-145d2288-c4ef-45e7-876d-14e27c66c414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590954880 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.590954880
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.3983614024
Short name T144
Test name
Test status
Simulation time 160859906808 ps
CPU time 40.63 seconds
Started Jul 19 07:16:21 PM PDT 24
Finished Jul 19 07:17:09 PM PDT 24
Peak memory 201728 kb
Host smart-e3bd75b6-960a-4d48-8a80-a09f49338cef
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983614024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fix
ed.3983614024
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.2636585055
Short name T210
Test name
Test status
Simulation time 184359791165 ps
CPU time 110.58 seconds
Started Jul 19 07:16:23 PM PDT 24
Finished Jul 19 07:18:21 PM PDT 24
Peak memory 201800 kb
Host smart-0413b266-ea0b-4ac0-a185-829d3639a64f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636585055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters
_wakeup.2636585055
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.1857922235
Short name T89
Test name
Test status
Simulation time 599531401123 ps
CPU time 1439.23 seconds
Started Jul 19 07:16:24 PM PDT 24
Finished Jul 19 07:40:31 PM PDT 24
Peak memory 201756 kb
Host smart-5081524a-19a0-4dff-a943-4449b075b227
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857922235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.adc_ctrl_filters_wakeup_fixed.1857922235
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.2924529350
Short name T185
Test name
Test status
Simulation time 95154923770 ps
CPU time 470.38 seconds
Started Jul 19 07:16:22 PM PDT 24
Finished Jul 19 07:24:19 PM PDT 24
Peak memory 202104 kb
Host smart-c479aea6-b3e2-4b62-a7cc-9bcb7121cd85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924529350 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.2924529350
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.475892461
Short name T616
Test name
Test status
Simulation time 29869925196 ps
CPU time 68.68 seconds
Started Jul 19 07:16:23 PM PDT 24
Finished Jul 19 07:17:39 PM PDT 24
Peak memory 201600 kb
Host smart-4c425692-0812-43d8-986e-a682915d38e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475892461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.475892461
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.2687199960
Short name T499
Test name
Test status
Simulation time 4807766507 ps
CPU time 12.52 seconds
Started Jul 19 07:16:19 PM PDT 24
Finished Jul 19 07:16:39 PM PDT 24
Peak memory 201564 kb
Host smart-38cea6ae-10b5-4b32-ab57-a0b56274b480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687199960 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.2687199960
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.985453135
Short name T492
Test name
Test status
Simulation time 5921353492 ps
CPU time 4.91 seconds
Started Jul 19 07:16:24 PM PDT 24
Finished Jul 19 07:16:37 PM PDT 24
Peak memory 201600 kb
Host smart-c483def7-b18d-4831-b11b-4bf845f20dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985453135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.985453135
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.3640631765
Short name T666
Test name
Test status
Simulation time 46282879059 ps
CPU time 30.26 seconds
Started Jul 19 07:16:20 PM PDT 24
Finished Jul 19 07:16:57 PM PDT 24
Peak memory 210080 kb
Host smart-dadedfea-8386-4ff7-9533-83ce63777e63
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640631765 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.3640631765
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.2536191818
Short name T482
Test name
Test status
Simulation time 376545930 ps
CPU time 1.09 seconds
Started Jul 19 07:16:36 PM PDT 24
Finished Jul 19 07:16:45 PM PDT 24
Peak memory 201560 kb
Host smart-52fef023-c1bd-4c94-8648-1e2d1947d587
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536191818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.2536191818
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.4106834756
Short name T165
Test name
Test status
Simulation time 524869560620 ps
CPU time 285.57 seconds
Started Jul 19 07:16:32 PM PDT 24
Finished Jul 19 07:21:26 PM PDT 24
Peak memory 201788 kb
Host smart-ba857f01-a818-42ff-92a6-29dcdfb1a1dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106834756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.4106834756
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.1588400630
Short name T200
Test name
Test status
Simulation time 491719906903 ps
CPU time 1204.47 seconds
Started Jul 19 07:16:37 PM PDT 24
Finished Jul 19 07:36:49 PM PDT 24
Peak memory 201756 kb
Host smart-b32981b4-bc3d-4a17-ae1f-049e27dad234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588400630 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.1588400630
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.782294783
Short name T375
Test name
Test status
Simulation time 320662355975 ps
CPU time 754.3 seconds
Started Jul 19 07:16:33 PM PDT 24
Finished Jul 19 07:29:16 PM PDT 24
Peak memory 201784 kb
Host smart-726d0397-928c-4ccb-82d6-242df696f3d9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=782294783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrup
t_fixed.782294783
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.1660241860
Short name T250
Test name
Test status
Simulation time 323777611818 ps
CPU time 61.45 seconds
Started Jul 19 07:16:36 PM PDT 24
Finished Jul 19 07:17:45 PM PDT 24
Peak memory 201816 kb
Host smart-f531d557-d6ec-4ff7-9b3d-ecfe88bcf676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660241860 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.1660241860
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.3066231196
Short name T768
Test name
Test status
Simulation time 500973392815 ps
CPU time 304.27 seconds
Started Jul 19 07:16:34 PM PDT 24
Finished Jul 19 07:21:47 PM PDT 24
Peak memory 201752 kb
Host smart-053c6177-dce2-4cf4-bd9e-954bd87c4f23
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066231196 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fix
ed.3066231196
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.3015073131
Short name T246
Test name
Test status
Simulation time 349070552258 ps
CPU time 716.51 seconds
Started Jul 19 07:16:33 PM PDT 24
Finished Jul 19 07:28:37 PM PDT 24
Peak memory 201784 kb
Host smart-ca49716b-6030-4f24-a770-503f57e732e4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015073131 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters
_wakeup.3015073131
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.1011442676
Short name T466
Test name
Test status
Simulation time 393559634472 ps
CPU time 961.36 seconds
Started Jul 19 07:16:34 PM PDT 24
Finished Jul 19 07:32:44 PM PDT 24
Peak memory 201728 kb
Host smart-42de0720-98ec-46c6-b998-58ad142df33b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011442676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.adc_ctrl_filters_wakeup_fixed.1011442676
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.2496294760
Short name T497
Test name
Test status
Simulation time 68811242671 ps
CPU time 315.22 seconds
Started Jul 19 07:16:34 PM PDT 24
Finished Jul 19 07:21:57 PM PDT 24
Peak memory 202132 kb
Host smart-c5edb70d-2bce-4823-9f36-8da3e665ef45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496294760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.2496294760
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.3599709747
Short name T337
Test name
Test status
Simulation time 31614357650 ps
CPU time 37.45 seconds
Started Jul 19 07:16:36 PM PDT 24
Finished Jul 19 07:17:21 PM PDT 24
Peak memory 201616 kb
Host smart-6751a6a1-04eb-4a45-91a4-9b7d2fee75b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599709747 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.3599709747
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.3253804759
Short name T611
Test name
Test status
Simulation time 4108512193 ps
CPU time 3.85 seconds
Started Jul 19 07:16:35 PM PDT 24
Finished Jul 19 07:16:47 PM PDT 24
Peak memory 201600 kb
Host smart-2ec54765-fd77-40ed-ae72-a8195a616997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253804759 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.3253804759
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.3708927416
Short name T586
Test name
Test status
Simulation time 5819555159 ps
CPU time 3.94 seconds
Started Jul 19 07:16:34 PM PDT 24
Finished Jul 19 07:16:46 PM PDT 24
Peak memory 201588 kb
Host smart-0c4e108c-b958-4e21-90be-9be7f769cc24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708927416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.3708927416
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.3865821360
Short name T308
Test name
Test status
Simulation time 329088551270 ps
CPU time 186.57 seconds
Started Jul 19 07:16:33 PM PDT 24
Finished Jul 19 07:19:47 PM PDT 24
Peak memory 201748 kb
Host smart-152fd25e-18f1-42c3-b38a-8fc8bae09412
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865821360 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all
.3865821360
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.1675291600
Short name T515
Test name
Test status
Simulation time 418191946 ps
CPU time 0.87 seconds
Started Jul 19 07:16:59 PM PDT 24
Finished Jul 19 07:17:03 PM PDT 24
Peak memory 201568 kb
Host smart-eb7994ac-2851-492e-92d0-b1ff48f8283e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675291600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.1675291600
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.1887188273
Short name T304
Test name
Test status
Simulation time 165347175671 ps
CPU time 181.09 seconds
Started Jul 19 07:16:49 PM PDT 24
Finished Jul 19 07:19:54 PM PDT 24
Peak memory 201812 kb
Host smart-3097a924-126b-4fc5-aba4-94d7c0e1f67b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887188273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gat
ing.1887188273
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.1369850998
Short name T667
Test name
Test status
Simulation time 166381769746 ps
CPU time 401.2 seconds
Started Jul 19 07:16:49 PM PDT 24
Finished Jul 19 07:23:34 PM PDT 24
Peak memory 201696 kb
Host smart-09f330cb-808a-441d-bd5c-7a101f8db279
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369850998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interru
pt_fixed.1369850998
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.2251254752
Short name T552
Test name
Test status
Simulation time 325212649014 ps
CPU time 733.19 seconds
Started Jul 19 07:16:48 PM PDT 24
Finished Jul 19 07:29:05 PM PDT 24
Peak memory 201744 kb
Host smart-97365df0-4004-4179-abc5-e6545ce75fcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251254752 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.2251254752
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.410901215
Short name T570
Test name
Test status
Simulation time 329761292976 ps
CPU time 206.38 seconds
Started Jul 19 07:16:47 PM PDT 24
Finished Jul 19 07:20:19 PM PDT 24
Peak memory 201784 kb
Host smart-a3873caf-bae1-4b9c-90b9-05ab14a08f4a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=410901215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fixe
d.410901215
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.3666161795
Short name T222
Test name
Test status
Simulation time 188597753472 ps
CPU time 214.54 seconds
Started Jul 19 07:16:47 PM PDT 24
Finished Jul 19 07:20:26 PM PDT 24
Peak memory 201760 kb
Host smart-159757e6-f8ea-4ac3-926a-ba42bbbe2fc8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666161795 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters
_wakeup.3666161795
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.2345735635
Short name T476
Test name
Test status
Simulation time 200153475900 ps
CPU time 150.49 seconds
Started Jul 19 07:16:47 PM PDT 24
Finished Jul 19 07:19:22 PM PDT 24
Peak memory 201692 kb
Host smart-09161e1b-cc6a-4532-9a4c-49b22204a448
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345735635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.adc_ctrl_filters_wakeup_fixed.2345735635
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.506870054
Short name T403
Test name
Test status
Simulation time 98675665960 ps
CPU time 540.54 seconds
Started Jul 19 07:16:46 PM PDT 24
Finished Jul 19 07:25:52 PM PDT 24
Peak memory 202180 kb
Host smart-59399370-2a6e-4ffe-9641-6ca5883ad7b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506870054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.506870054
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.103776644
Short name T361
Test name
Test status
Simulation time 27232339020 ps
CPU time 15.88 seconds
Started Jul 19 07:16:47 PM PDT 24
Finished Jul 19 07:17:08 PM PDT 24
Peak memory 201616 kb
Host smart-a9566985-6ae5-48e4-b875-552566a8b70d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103776644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.103776644
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.2075443505
Short name T575
Test name
Test status
Simulation time 4742722483 ps
CPU time 11.36 seconds
Started Jul 19 07:16:49 PM PDT 24
Finished Jul 19 07:17:04 PM PDT 24
Peak memory 201616 kb
Host smart-279bb4c5-ee25-4f11-a623-f1bb2aa8773f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075443505 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.2075443505
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.2415491538
Short name T688
Test name
Test status
Simulation time 5986148374 ps
CPU time 4.5 seconds
Started Jul 19 07:16:34 PM PDT 24
Finished Jul 19 07:16:46 PM PDT 24
Peak memory 201600 kb
Host smart-92d47728-afe3-4697-86b9-b1fad9f720e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415491538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.2415491538
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.2716735527
Short name T658
Test name
Test status
Simulation time 487087240609 ps
CPU time 395.83 seconds
Started Jul 19 07:16:47 PM PDT 24
Finished Jul 19 07:23:28 PM PDT 24
Peak memory 202264 kb
Host smart-e7217f35-a20a-4560-98e8-21ffa0761324
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716735527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all
.2716735527
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.3435372785
Short name T205
Test name
Test status
Simulation time 16640948830 ps
CPU time 36.96 seconds
Started Jul 19 07:16:50 PM PDT 24
Finished Jul 19 07:17:30 PM PDT 24
Peak memory 201816 kb
Host smart-51d21b3e-fa96-4f9a-90e6-964788a451b2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435372785 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.3435372785
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.3048707865
Short name T338
Test name
Test status
Simulation time 499701040 ps
CPU time 1.16 seconds
Started Jul 19 07:17:13 PM PDT 24
Finished Jul 19 07:17:15 PM PDT 24
Peak memory 201520 kb
Host smart-f181c897-edba-4030-9902-d2ec99ceed87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048707865 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.3048707865
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.1222868335
Short name T550
Test name
Test status
Simulation time 164236497207 ps
CPU time 197.31 seconds
Started Jul 19 07:17:00 PM PDT 24
Finished Jul 19 07:20:20 PM PDT 24
Peak memory 201760 kb
Host smart-e7d0d6f3-1f23-42a1-8c12-b1c6acc8533e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222868335 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.1222868335
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.3899565956
Short name T6
Test name
Test status
Simulation time 164066235739 ps
CPU time 199.78 seconds
Started Jul 19 07:16:59 PM PDT 24
Finished Jul 19 07:20:22 PM PDT 24
Peak memory 201812 kb
Host smart-de235880-eaa4-4227-9f4a-0e11e9d7bf2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899565956 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.3899565956
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.2629184054
Short name T729
Test name
Test status
Simulation time 498742618075 ps
CPU time 266.01 seconds
Started Jul 19 07:16:59 PM PDT 24
Finished Jul 19 07:21:28 PM PDT 24
Peak memory 201728 kb
Host smart-694a2917-a88a-4269-b939-d67cc5fd751a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629184054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interru
pt_fixed.2629184054
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.500292655
Short name T543
Test name
Test status
Simulation time 494031891911 ps
CPU time 1133.15 seconds
Started Jul 19 07:17:01 PM PDT 24
Finished Jul 19 07:35:56 PM PDT 24
Peak memory 201800 kb
Host smart-496f62de-3787-4961-875b-b3c292fd38d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500292655 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.500292655
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.2524479256
Short name T425
Test name
Test status
Simulation time 164704682153 ps
CPU time 413.98 seconds
Started Jul 19 07:17:00 PM PDT 24
Finished Jul 19 07:23:56 PM PDT 24
Peak memory 201724 kb
Host smart-0cca673e-ad92-454f-94e2-01b059b58232
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524479256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fix
ed.2524479256
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.2838143438
Short name T590
Test name
Test status
Simulation time 203316205050 ps
CPU time 486.4 seconds
Started Jul 19 07:16:59 PM PDT 24
Finished Jul 19 07:25:09 PM PDT 24
Peak memory 201732 kb
Host smart-6ffc1348-694f-4c77-8365-b2afc9431682
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838143438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.adc_ctrl_filters_wakeup_fixed.2838143438
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.2544260833
Short name T41
Test name
Test status
Simulation time 107881454439 ps
CPU time 441.47 seconds
Started Jul 19 07:17:11 PM PDT 24
Finished Jul 19 07:24:34 PM PDT 24
Peak memory 202096 kb
Host smart-a9204135-f6d3-49b4-9c19-ad160e6eeff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544260833 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.2544260833
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.1614310346
Short name T44
Test name
Test status
Simulation time 27314879164 ps
CPU time 31.15 seconds
Started Jul 19 07:17:13 PM PDT 24
Finished Jul 19 07:17:45 PM PDT 24
Peak memory 201616 kb
Host smart-36661147-4c3e-4044-822d-4813088f15f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614310346 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.1614310346
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.3250467274
Short name T785
Test name
Test status
Simulation time 3265095151 ps
CPU time 2.08 seconds
Started Jul 19 07:17:11 PM PDT 24
Finished Jul 19 07:17:14 PM PDT 24
Peak memory 201608 kb
Host smart-228aa9d2-2825-4c38-b460-61e91bf8d79f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250467274 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.3250467274
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.3489235698
Short name T655
Test name
Test status
Simulation time 5941168110 ps
CPU time 4.05 seconds
Started Jul 19 07:16:59 PM PDT 24
Finished Jul 19 07:17:06 PM PDT 24
Peak memory 201556 kb
Host smart-30ba5ce7-9a22-4993-a452-f0bb74990a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489235698 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.3489235698
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.3810504854
Short name T428
Test name
Test status
Simulation time 329211722041 ps
CPU time 234.88 seconds
Started Jul 19 07:17:13 PM PDT 24
Finished Jul 19 07:21:10 PM PDT 24
Peak memory 201744 kb
Host smart-4791edbc-39b8-4738-b0e9-a6b1785fd41b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810504854 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all
.3810504854
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.1238256465
Short name T599
Test name
Test status
Simulation time 90640943044 ps
CPU time 80.27 seconds
Started Jul 19 07:17:14 PM PDT 24
Finished Jul 19 07:18:36 PM PDT 24
Peak memory 210448 kb
Host smart-71f8a6d4-051e-4e7c-9b69-b8c9196f231d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238256465 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.1238256465
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.1171319936
Short name T788
Test name
Test status
Simulation time 444033399 ps
CPU time 1.7 seconds
Started Jul 19 07:17:24 PM PDT 24
Finished Jul 19 07:17:28 PM PDT 24
Peak memory 201544 kb
Host smart-131275ae-0e89-42f5-a846-af5dff5b9037
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171319936 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.1171319936
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.3284309813
Short name T700
Test name
Test status
Simulation time 327328733846 ps
CPU time 757.1 seconds
Started Jul 19 07:17:12 PM PDT 24
Finished Jul 19 07:29:50 PM PDT 24
Peak memory 201732 kb
Host smart-e0988428-653e-490d-9cf9-0af4282bde7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284309813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.3284309813
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.1678418779
Short name T442
Test name
Test status
Simulation time 484735861573 ps
CPU time 293.69 seconds
Started Jul 19 07:17:13 PM PDT 24
Finished Jul 19 07:22:09 PM PDT 24
Peak memory 201720 kb
Host smart-87b11d7f-14a0-4c5d-b550-52f84dc9fc1a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678418779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interru
pt_fixed.1678418779
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.2848810275
Short name T245
Test name
Test status
Simulation time 485267954984 ps
CPU time 1150.82 seconds
Started Jul 19 07:17:11 PM PDT 24
Finished Jul 19 07:36:23 PM PDT 24
Peak memory 201812 kb
Host smart-79f3484c-9841-4009-a224-40922a91d2b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848810275 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.2848810275
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.3438561296
Short name T702
Test name
Test status
Simulation time 330568080510 ps
CPU time 134.38 seconds
Started Jul 19 07:17:13 PM PDT 24
Finished Jul 19 07:19:29 PM PDT 24
Peak memory 201760 kb
Host smart-4df30815-ab8d-4f00-894e-e62623900def
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438561296 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fix
ed.3438561296
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.4001785170
Short name T74
Test name
Test status
Simulation time 462741204882 ps
CPU time 75.38 seconds
Started Jul 19 07:17:12 PM PDT 24
Finished Jul 19 07:18:29 PM PDT 24
Peak memory 201812 kb
Host smart-294b575c-9dd0-4662-be72-132da69d70f1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001785170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters
_wakeup.4001785170
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.2475679602
Short name T479
Test name
Test status
Simulation time 605492629180 ps
CPU time 462.72 seconds
Started Jul 19 07:17:11 PM PDT 24
Finished Jul 19 07:24:55 PM PDT 24
Peak memory 201728 kb
Host smart-8c82b588-d7bc-40f3-a05a-33226f7cf66d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475679602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.adc_ctrl_filters_wakeup_fixed.2475679602
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.2772919169
Short name T86
Test name
Test status
Simulation time 121800813708 ps
CPU time 656.83 seconds
Started Jul 19 07:17:14 PM PDT 24
Finished Jul 19 07:28:12 PM PDT 24
Peak memory 202192 kb
Host smart-1b86fc85-23ec-4354-87e3-de642312ae0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772919169 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.2772919169
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.2153501299
Short name T430
Test name
Test status
Simulation time 35130336454 ps
CPU time 84.19 seconds
Started Jul 19 07:17:11 PM PDT 24
Finished Jul 19 07:18:37 PM PDT 24
Peak memory 201584 kb
Host smart-38f21621-a70b-4d83-a423-b0f6ddf4dab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153501299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.2153501299
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.2923834896
Short name T365
Test name
Test status
Simulation time 3570092918 ps
CPU time 9.3 seconds
Started Jul 19 07:17:10 PM PDT 24
Finished Jul 19 07:17:21 PM PDT 24
Peak memory 201752 kb
Host smart-7ca4132e-1526-4504-ad7b-a572c8c3d0d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923834896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.2923834896
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.1194468568
Short name T564
Test name
Test status
Simulation time 5721919486 ps
CPU time 12.65 seconds
Started Jul 19 07:17:11 PM PDT 24
Finished Jul 19 07:17:25 PM PDT 24
Peak memory 201636 kb
Host smart-7d837456-d7ad-4ace-80e1-0a70e285d929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194468568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.1194468568
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.2759539509
Short name T542
Test name
Test status
Simulation time 332047022396 ps
CPU time 808.27 seconds
Started Jul 19 07:17:24 PM PDT 24
Finished Jul 19 07:30:54 PM PDT 24
Peak memory 201824 kb
Host smart-c18b8f33-d3c5-419e-b1e3-7f9239287617
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759539509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all
.2759539509
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.1040245954
Short name T322
Test name
Test status
Simulation time 119386431710 ps
CPU time 211.87 seconds
Started Jul 19 07:17:25 PM PDT 24
Finished Jul 19 07:20:59 PM PDT 24
Peak memory 213960 kb
Host smart-89a97932-ab28-475d-88e5-bf36357f2195
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040245954 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.1040245954
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.3718323874
Short name T505
Test name
Test status
Simulation time 372753399 ps
CPU time 0.99 seconds
Started Jul 19 07:17:23 PM PDT 24
Finished Jul 19 07:17:26 PM PDT 24
Peak memory 201536 kb
Host smart-e4f292d7-1066-494a-b23a-b795bfef2bf9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718323874 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.3718323874
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.1360447698
Short name T212
Test name
Test status
Simulation time 161864394623 ps
CPU time 63.79 seconds
Started Jul 19 07:17:23 PM PDT 24
Finished Jul 19 07:18:29 PM PDT 24
Peak memory 201764 kb
Host smart-8c1bdd91-a8db-4cb4-99db-455c4c096bf7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360447698 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gat
ing.1360447698
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.1262002641
Short name T289
Test name
Test status
Simulation time 492482106461 ps
CPU time 539.39 seconds
Started Jul 19 07:17:26 PM PDT 24
Finished Jul 19 07:26:27 PM PDT 24
Peak memory 201756 kb
Host smart-f3a35c03-bf4c-4c0d-98fd-11bdc65020c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262002641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.1262002641
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.3081297268
Short name T94
Test name
Test status
Simulation time 321160086161 ps
CPU time 758.49 seconds
Started Jul 19 07:17:26 PM PDT 24
Finished Jul 19 07:30:07 PM PDT 24
Peak memory 201748 kb
Host smart-0c6a8911-fb33-432b-bdc8-06c907cf7958
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081297268 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interru
pt_fixed.3081297268
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.3766087615
Short name T780
Test name
Test status
Simulation time 335623662854 ps
CPU time 394.41 seconds
Started Jul 19 07:17:25 PM PDT 24
Finished Jul 19 07:24:02 PM PDT 24
Peak memory 201776 kb
Host smart-7a63e7fb-cc1e-498f-8289-2e6f876dbd22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766087615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.3766087615
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.617243555
Short name T133
Test name
Test status
Simulation time 491129768709 ps
CPU time 1193.55 seconds
Started Jul 19 07:17:25 PM PDT 24
Finished Jul 19 07:37:21 PM PDT 24
Peak memory 201812 kb
Host smart-d87a56c0-98bd-461c-8026-f25845ec09a1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=617243555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fixe
d.617243555
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.3034571854
Short name T725
Test name
Test status
Simulation time 639339492573 ps
CPU time 1471.28 seconds
Started Jul 19 07:17:26 PM PDT 24
Finished Jul 19 07:41:59 PM PDT 24
Peak memory 201816 kb
Host smart-126a31ae-de8c-4ac8-8cd0-3b96f05f4d78
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034571854 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters
_wakeup.3034571854
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.2626755601
Short name T358
Test name
Test status
Simulation time 402534570188 ps
CPU time 184.19 seconds
Started Jul 19 07:17:27 PM PDT 24
Finished Jul 19 07:20:33 PM PDT 24
Peak memory 201736 kb
Host smart-10d56820-6e54-4196-8d73-126fae52bb24
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626755601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.adc_ctrl_filters_wakeup_fixed.2626755601
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.1143068776
Short name T42
Test name
Test status
Simulation time 118399590703 ps
CPU time 459.71 seconds
Started Jul 19 07:17:24 PM PDT 24
Finished Jul 19 07:25:06 PM PDT 24
Peak memory 202100 kb
Host smart-01348488-c1cd-4dff-8ed0-11642e0c1a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143068776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.1143068776
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.2050056312
Short name T775
Test name
Test status
Simulation time 35478032518 ps
CPU time 41 seconds
Started Jul 19 07:17:25 PM PDT 24
Finished Jul 19 07:18:09 PM PDT 24
Peak memory 201612 kb
Host smart-cf9385d8-3f14-4a7f-bc6d-5efa9fd120c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050056312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.2050056312
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.3408992918
Short name T609
Test name
Test status
Simulation time 3314423647 ps
CPU time 8.76 seconds
Started Jul 19 07:17:24 PM PDT 24
Finished Jul 19 07:17:35 PM PDT 24
Peak memory 201612 kb
Host smart-28d227f9-63f4-4634-99e7-08876d4c1dff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408992918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.3408992918
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.3768731317
Short name T440
Test name
Test status
Simulation time 5762872366 ps
CPU time 11.25 seconds
Started Jul 19 07:17:25 PM PDT 24
Finished Jul 19 07:17:38 PM PDT 24
Peak memory 201584 kb
Host smart-130c0524-0536-4dee-af6e-7e6e450ff17d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768731317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.3768731317
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.3057596837
Short name T23
Test name
Test status
Simulation time 496134694448 ps
CPU time 781.15 seconds
Started Jul 19 07:17:23 PM PDT 24
Finished Jul 19 07:30:26 PM PDT 24
Peak memory 201704 kb
Host smart-fae761dd-3502-4633-953a-2bf223fafb9b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057596837 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all
.3057596837
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.645315640
Short name T18
Test name
Test status
Simulation time 88623526334 ps
CPU time 103.13 seconds
Started Jul 19 07:17:23 PM PDT 24
Finished Jul 19 07:19:08 PM PDT 24
Peak memory 210440 kb
Host smart-d7ac952e-1769-42c7-a96c-44fd046e0ce2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645315640 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.645315640
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.1489769496
Short name T739
Test name
Test status
Simulation time 309449634 ps
CPU time 1.35 seconds
Started Jul 19 07:17:39 PM PDT 24
Finished Jul 19 07:17:43 PM PDT 24
Peak memory 201564 kb
Host smart-395b62cd-5b04-4c06-af85-d82d8ed6c684
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489769496 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.1489769496
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.2094762917
Short name T231
Test name
Test status
Simulation time 186314146970 ps
CPU time 94.69 seconds
Started Jul 19 07:17:44 PM PDT 24
Finished Jul 19 07:19:23 PM PDT 24
Peak memory 201740 kb
Host smart-c7eff117-3f5f-4355-a642-abc9a089c9cb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094762917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gat
ing.2094762917
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.2942055817
Short name T431
Test name
Test status
Simulation time 333310500635 ps
CPU time 318.04 seconds
Started Jul 19 07:17:44 PM PDT 24
Finished Jul 19 07:23:07 PM PDT 24
Peak memory 201752 kb
Host smart-a9a25a33-67a3-44b4-9c37-c45ef119da1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942055817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.2942055817
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.1494401515
Short name T408
Test name
Test status
Simulation time 321033234025 ps
CPU time 782.2 seconds
Started Jul 19 07:17:39 PM PDT 24
Finished Jul 19 07:30:44 PM PDT 24
Peak memory 201668 kb
Host smart-3b56ad7d-2fdb-42a1-a8fd-7518b54db0ba
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494401515 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interru
pt_fixed.1494401515
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.1121378357
Short name T668
Test name
Test status
Simulation time 324507890423 ps
CPU time 53.28 seconds
Started Jul 19 07:17:22 PM PDT 24
Finished Jul 19 07:18:18 PM PDT 24
Peak memory 201752 kb
Host smart-7ccda9d5-0475-407e-bb46-c8e03f1b6787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121378357 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.1121378357
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.1534452688
Short name T776
Test name
Test status
Simulation time 167407912578 ps
CPU time 377.04 seconds
Started Jul 19 07:17:26 PM PDT 24
Finished Jul 19 07:23:45 PM PDT 24
Peak memory 201728 kb
Host smart-e12c5c1c-53ab-432a-ae12-9fff88ebb989
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534452688 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fix
ed.1534452688
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.4119549590
Short name T382
Test name
Test status
Simulation time 598873965159 ps
CPU time 1200.26 seconds
Started Jul 19 07:17:44 PM PDT 24
Finished Jul 19 07:37:50 PM PDT 24
Peak memory 201724 kb
Host smart-b53dce28-56e4-49f1-b43e-adbcc3e89b7f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119549590 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.adc_ctrl_filters_wakeup_fixed.4119549590
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.1313014180
Short name T189
Test name
Test status
Simulation time 110461677651 ps
CPU time 623.02 seconds
Started Jul 19 07:17:39 PM PDT 24
Finished Jul 19 07:28:05 PM PDT 24
Peak memory 202196 kb
Host smart-a9a28149-7a64-4728-9758-7515dd72adf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313014180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.1313014180
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.2274166648
Short name T453
Test name
Test status
Simulation time 42675012940 ps
CPU time 93.07 seconds
Started Jul 19 07:17:40 PM PDT 24
Finished Jul 19 07:19:16 PM PDT 24
Peak memory 201608 kb
Host smart-39563f0e-6e66-42f9-b717-176ce4142c9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274166648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.2274166648
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.2969172008
Short name T392
Test name
Test status
Simulation time 3146853986 ps
CPU time 2.78 seconds
Started Jul 19 07:17:39 PM PDT 24
Finished Jul 19 07:17:45 PM PDT 24
Peak memory 201624 kb
Host smart-2b74b07a-6936-473c-8106-8bf2dce732f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969172008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.2969172008
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.1576135499
Short name T354
Test name
Test status
Simulation time 5871421384 ps
CPU time 14.63 seconds
Started Jul 19 07:17:22 PM PDT 24
Finished Jul 19 07:17:39 PM PDT 24
Peak memory 201624 kb
Host smart-d7029819-dcf8-48ac-b03e-24defdb7275d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576135499 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.1576135499
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.140454894
Short name T155
Test name
Test status
Simulation time 175054793119 ps
CPU time 412.8 seconds
Started Jul 19 07:17:39 PM PDT 24
Finished Jul 19 07:24:35 PM PDT 24
Peak memory 201736 kb
Host smart-03cbcb51-01fb-4944-a683-8b8475182129
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140454894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all.
140454894
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.1146403085
Short name T297
Test name
Test status
Simulation time 62400462443 ps
CPU time 35.69 seconds
Started Jul 19 07:17:38 PM PDT 24
Finished Jul 19 07:18:16 PM PDT 24
Peak memory 210140 kb
Host smart-8ee0154d-cad0-43a7-8f79-e88e2fe4155a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146403085 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.1146403085
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.603608906
Short name T364
Test name
Test status
Simulation time 440415625 ps
CPU time 0.94 seconds
Started Jul 19 07:07:34 PM PDT 24
Finished Jul 19 07:07:39 PM PDT 24
Peak memory 201556 kb
Host smart-fbbe94c6-19bb-4f10-9a54-2abe3673da44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603608906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.603608906
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.482483855
Short name T211
Test name
Test status
Simulation time 338571687425 ps
CPU time 453.67 seconds
Started Jul 19 07:07:15 PM PDT 24
Finished Jul 19 07:14:51 PM PDT 24
Peak memory 201752 kb
Host smart-b0bf2511-6a25-459b-874a-5863fe6feb28
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482483855 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gatin
g.482483855
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.819270316
Short name T627
Test name
Test status
Simulation time 325201226974 ps
CPU time 392.48 seconds
Started Jul 19 07:07:08 PM PDT 24
Finished Jul 19 07:13:43 PM PDT 24
Peak memory 201752 kb
Host smart-21c6ad7e-b4cc-4f9d-b266-c40a9aeef3b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819270316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.819270316
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.887982347
Short name T731
Test name
Test status
Simulation time 495111798501 ps
CPU time 634.22 seconds
Started Jul 19 07:07:06 PM PDT 24
Finished Jul 19 07:17:41 PM PDT 24
Peak memory 201748 kb
Host smart-e07b8107-0a6e-43ae-8c64-2f04924e97c7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=887982347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt
_fixed.887982347
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.2425027415
Short name T523
Test name
Test status
Simulation time 333882542333 ps
CPU time 785.27 seconds
Started Jul 19 07:07:06 PM PDT 24
Finished Jul 19 07:20:12 PM PDT 24
Peak memory 201956 kb
Host smart-3c890fb6-707b-4e29-83e9-aec675a9b0b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425027415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.2425027415
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.1502885370
Short name T635
Test name
Test status
Simulation time 164278941086 ps
CPU time 351.82 seconds
Started Jul 19 07:07:06 PM PDT 24
Finished Jul 19 07:12:59 PM PDT 24
Peak memory 201740 kb
Host smart-956bddf6-9acf-41cf-b368-e0fbb4e6955e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502885370 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixe
d.1502885370
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.1806225869
Short name T229
Test name
Test status
Simulation time 165761536747 ps
CPU time 114.96 seconds
Started Jul 19 07:07:40 PM PDT 24
Finished Jul 19 07:09:37 PM PDT 24
Peak memory 201764 kb
Host smart-a02317c1-c3bb-4105-9e77-8c93010175e8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806225869 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_
wakeup.1806225869
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.3783486121
Short name T625
Test name
Test status
Simulation time 200692418899 ps
CPU time 45.69 seconds
Started Jul 19 07:07:16 PM PDT 24
Finished Jul 19 07:08:03 PM PDT 24
Peak memory 201752 kb
Host smart-e32f994e-acbd-42a7-8fad-20ee9ab49fab
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783486121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
adc_ctrl_filters_wakeup_fixed.3783486121
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.3558597706
Short name T388
Test name
Test status
Simulation time 98118189118 ps
CPU time 391.66 seconds
Started Jul 19 07:07:27 PM PDT 24
Finished Jul 19 07:14:05 PM PDT 24
Peak memory 202200 kb
Host smart-53a845cd-b704-4360-b6a3-b0f7905e7b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558597706 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.3558597706
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.1788020952
Short name T643
Test name
Test status
Simulation time 23764213419 ps
CPU time 5.16 seconds
Started Jul 19 07:07:33 PM PDT 24
Finished Jul 19 07:07:41 PM PDT 24
Peak memory 201548 kb
Host smart-371da712-18f6-4834-a61d-f2356ad48141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788020952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.1788020952
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.378818958
Short name T407
Test name
Test status
Simulation time 4545432307 ps
CPU time 11.88 seconds
Started Jul 19 07:07:23 PM PDT 24
Finished Jul 19 07:07:40 PM PDT 24
Peak memory 201596 kb
Host smart-d034b6d3-a3d2-4ac8-97b6-1e7b65cd52f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378818958 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.378818958
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.2275327083
Short name T69
Test name
Test status
Simulation time 4466079900 ps
CPU time 2.57 seconds
Started Jul 19 07:07:33 PM PDT 24
Finished Jul 19 07:07:39 PM PDT 24
Peak memory 217232 kb
Host smart-943513cb-47fd-440a-92bb-4070421197c3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275327083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.2275327083
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.524223511
Short name T733
Test name
Test status
Simulation time 6065507886 ps
CPU time 17.85 seconds
Started Jul 19 07:07:09 PM PDT 24
Finished Jul 19 07:07:28 PM PDT 24
Peak memory 201588 kb
Host smart-f2b37802-ba0e-4c09-a24b-542afe27d500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524223511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.524223511
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.378174751
Short name T384
Test name
Test status
Simulation time 525488658 ps
CPU time 1.93 seconds
Started Jul 19 07:17:51 PM PDT 24
Finished Jul 19 07:18:01 PM PDT 24
Peak memory 201568 kb
Host smart-69c2ce1b-c83b-48e9-aaef-8221083c9443
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378174751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.378174751
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.2655967891
Short name T670
Test name
Test status
Simulation time 342729518701 ps
CPU time 755.03 seconds
Started Jul 19 07:17:52 PM PDT 24
Finished Jul 19 07:30:34 PM PDT 24
Peak memory 201692 kb
Host smart-ab8050ad-f3b5-4715-ab6e-5192b046fbd3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655967891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gat
ing.2655967891
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.3412887219
Short name T646
Test name
Test status
Simulation time 495161574910 ps
CPU time 117.2 seconds
Started Jul 19 07:17:51 PM PDT 24
Finished Jul 19 07:19:55 PM PDT 24
Peak memory 201756 kb
Host smart-969c86ae-19c6-4747-9939-5bde8a50670f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412887219 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.3412887219
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.911067211
Short name T744
Test name
Test status
Simulation time 488939163650 ps
CPU time 291.85 seconds
Started Jul 19 07:17:38 PM PDT 24
Finished Jul 19 07:22:33 PM PDT 24
Peak memory 201888 kb
Host smart-5da36df7-4cdd-468e-99a4-b8eab9fbcd08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911067211 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.911067211
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.1205753136
Short name T481
Test name
Test status
Simulation time 487287988540 ps
CPU time 788.39 seconds
Started Jul 19 07:17:39 PM PDT 24
Finished Jul 19 07:30:50 PM PDT 24
Peak memory 201724 kb
Host smart-a14ba28f-443e-4df9-843e-9b17e8f31536
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205753136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interru
pt_fixed.1205753136
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.4162344551
Short name T380
Test name
Test status
Simulation time 327332392366 ps
CPU time 354.17 seconds
Started Jul 19 07:17:38 PM PDT 24
Finished Jul 19 07:23:35 PM PDT 24
Peak memory 201808 kb
Host smart-5bade7ae-4950-4cd4-af08-2aa65d8e2a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162344551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.4162344551
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.2781381395
Short name T516
Test name
Test status
Simulation time 485879059369 ps
CPU time 297.5 seconds
Started Jul 19 07:17:38 PM PDT 24
Finished Jul 19 07:22:38 PM PDT 24
Peak memory 201744 kb
Host smart-420497e8-2431-4b2a-b634-282af49a80ff
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781381395 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fix
ed.2781381395
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.2214209257
Short name T242
Test name
Test status
Simulation time 344296802253 ps
CPU time 840.84 seconds
Started Jul 19 07:17:51 PM PDT 24
Finished Jul 19 07:31:59 PM PDT 24
Peak memory 201808 kb
Host smart-f07a85e7-24c0-42e6-8674-368032bbb84c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214209257 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters
_wakeup.2214209257
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.607049557
Short name T383
Test name
Test status
Simulation time 594649053545 ps
CPU time 1320.75 seconds
Started Jul 19 07:17:54 PM PDT 24
Finished Jul 19 07:40:02 PM PDT 24
Peak memory 201756 kb
Host smart-3c8d17bc-ef67-4c1f-8892-810faa499ba5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607049557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
adc_ctrl_filters_wakeup_fixed.607049557
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.2196772788
Short name T426
Test name
Test status
Simulation time 121057681209 ps
CPU time 425.58 seconds
Started Jul 19 07:17:51 PM PDT 24
Finished Jul 19 07:25:04 PM PDT 24
Peak memory 202132 kb
Host smart-16804ea1-3cf3-4b20-a929-8aabdc18ed19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196772788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.2196772788
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.1994262318
Short name T584
Test name
Test status
Simulation time 25970073053 ps
CPU time 33.31 seconds
Started Jul 19 07:17:51 PM PDT 24
Finished Jul 19 07:18:30 PM PDT 24
Peak memory 201588 kb
Host smart-5ac1c583-7a71-4da9-9eb5-b9389625327c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994262318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.1994262318
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.2781456752
Short name T398
Test name
Test status
Simulation time 4641032213 ps
CPU time 3.42 seconds
Started Jul 19 07:17:51 PM PDT 24
Finished Jul 19 07:18:01 PM PDT 24
Peak memory 201560 kb
Host smart-0af35b0b-f837-40b8-a3de-f7a8eacc71bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781456752 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.2781456752
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.1255291718
Short name T687
Test name
Test status
Simulation time 5896009399 ps
CPU time 4.23 seconds
Started Jul 19 07:17:37 PM PDT 24
Finished Jul 19 07:17:45 PM PDT 24
Peak memory 201628 kb
Host smart-65df008c-67be-4c8b-81f3-77130ca0c6aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255291718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.1255291718
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.4073101298
Short name T518
Test name
Test status
Simulation time 330725370962 ps
CPU time 129.73 seconds
Started Jul 19 07:17:50 PM PDT 24
Finished Jul 19 07:20:06 PM PDT 24
Peak memory 201868 kb
Host smart-2dcd223f-1aca-4a62-8e6e-18d68a7edad5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073101298 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all
.4073101298
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.4115244985
Short name T19
Test name
Test status
Simulation time 161783415246 ps
CPU time 284.5 seconds
Started Jul 19 07:17:51 PM PDT 24
Finished Jul 19 07:22:42 PM PDT 24
Peak memory 217804 kb
Host smart-b945a28a-d6ab-4e6b-9c6c-d56eafe96cf4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115244985 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.4115244985
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.1849379243
Short name T400
Test name
Test status
Simulation time 511498488 ps
CPU time 0.87 seconds
Started Jul 19 07:17:51 PM PDT 24
Finished Jul 19 07:18:00 PM PDT 24
Peak memory 201536 kb
Host smart-7c561c70-6b8d-4859-b3aa-5c5564717ee4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849379243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.1849379243
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.171688496
Short name T238
Test name
Test status
Simulation time 170251721343 ps
CPU time 370.66 seconds
Started Jul 19 07:17:51 PM PDT 24
Finished Jul 19 07:24:09 PM PDT 24
Peak memory 201804 kb
Host smart-16d17a73-fca0-478a-9d92-033a74f9ff35
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171688496 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gati
ng.171688496
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.255167962
Short name T199
Test name
Test status
Simulation time 331409157431 ps
CPU time 415.39 seconds
Started Jul 19 07:17:55 PM PDT 24
Finished Jul 19 07:24:58 PM PDT 24
Peak memory 201720 kb
Host smart-eb2df8e2-5790-446c-9701-19399c475dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255167962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.255167962
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.2487229756
Short name T121
Test name
Test status
Simulation time 505634989906 ps
CPU time 656.4 seconds
Started Jul 19 07:17:50 PM PDT 24
Finished Jul 19 07:28:54 PM PDT 24
Peak memory 201776 kb
Host smart-53354f9e-67bf-47e9-8125-d38e447ad0e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487229756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.2487229756
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.1403653813
Short name T461
Test name
Test status
Simulation time 493785805739 ps
CPU time 1210.17 seconds
Started Jul 19 07:17:54 PM PDT 24
Finished Jul 19 07:38:12 PM PDT 24
Peak memory 201692 kb
Host smart-5b90a2e1-5147-43d3-b39a-4fd970c7905d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403653813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interru
pt_fixed.1403653813
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.1180795522
Short name T607
Test name
Test status
Simulation time 162597898976 ps
CPU time 120.33 seconds
Started Jul 19 07:17:50 PM PDT 24
Finished Jul 19 07:19:57 PM PDT 24
Peak memory 201812 kb
Host smart-ab98717b-968d-42b7-ab1b-f670a931627f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180795522 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.1180795522
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.156550399
Short name T601
Test name
Test status
Simulation time 159762053031 ps
CPU time 59.32 seconds
Started Jul 19 07:17:53 PM PDT 24
Finished Jul 19 07:18:59 PM PDT 24
Peak memory 201808 kb
Host smart-6755396b-3dfe-47ee-a01a-1fd953ab5e82
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=156550399 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fixe
d.156550399
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.2795865174
Short name T406
Test name
Test status
Simulation time 584139522728 ps
CPU time 1295.78 seconds
Started Jul 19 07:17:53 PM PDT 24
Finished Jul 19 07:39:37 PM PDT 24
Peak memory 201744 kb
Host smart-92e8143d-8bec-47f6-a5b7-b8c6c405e1d4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795865174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.adc_ctrl_filters_wakeup_fixed.2795865174
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.947677030
Short name T357
Test name
Test status
Simulation time 101161319591 ps
CPU time 558.24 seconds
Started Jul 19 07:17:53 PM PDT 24
Finished Jul 19 07:27:19 PM PDT 24
Peak memory 202084 kb
Host smart-ac1aaf9c-c42d-499c-a22e-973c6540fdc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947677030 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.947677030
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.1858815046
Short name T618
Test name
Test status
Simulation time 47019227573 ps
CPU time 49.79 seconds
Started Jul 19 07:17:50 PM PDT 24
Finished Jul 19 07:18:45 PM PDT 24
Peak memory 201612 kb
Host smart-9c73a333-9395-4edc-8467-b8d9847a9a1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858815046 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.1858815046
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.939833707
Short name T353
Test name
Test status
Simulation time 3130200496 ps
CPU time 8.03 seconds
Started Jul 19 07:17:54 PM PDT 24
Finished Jul 19 07:18:10 PM PDT 24
Peak memory 201560 kb
Host smart-656bd773-39c9-4438-aaff-1ae1a83890f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939833707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.939833707
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.3952373914
Short name T582
Test name
Test status
Simulation time 6091342839 ps
CPU time 3.92 seconds
Started Jul 19 07:17:51 PM PDT 24
Finished Jul 19 07:18:02 PM PDT 24
Peak memory 201628 kb
Host smart-78afd88f-7a9c-44c0-81da-774b3dac372a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952373914 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.3952373914
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.944773648
Short name T24
Test name
Test status
Simulation time 334274311922 ps
CPU time 503.14 seconds
Started Jul 19 07:17:50 PM PDT 24
Finished Jul 19 07:26:19 PM PDT 24
Peak memory 201752 kb
Host smart-d52846b1-8666-4791-81a7-e54e044517ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944773648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all.
944773648
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.1136736783
Short name T656
Test name
Test status
Simulation time 427772863 ps
CPU time 0.77 seconds
Started Jul 19 07:18:05 PM PDT 24
Finished Jul 19 07:18:12 PM PDT 24
Peak memory 201532 kb
Host smart-0df5eee7-0df5-4b5b-aec0-7f35849b1619
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136736783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.1136736783
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.425662524
Short name T711
Test name
Test status
Simulation time 343711325416 ps
CPU time 730.48 seconds
Started Jul 19 07:17:59 PM PDT 24
Finished Jul 19 07:30:16 PM PDT 24
Peak memory 201748 kb
Host smart-a3e5633b-9b6d-4d3e-a20a-4f6163e93973
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425662524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gati
ng.425662524
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.1988414618
Short name T257
Test name
Test status
Simulation time 328049935973 ps
CPU time 791.82 seconds
Started Jul 19 07:17:59 PM PDT 24
Finished Jul 19 07:31:17 PM PDT 24
Peak memory 201832 kb
Host smart-63b44add-0b0b-40c6-bbd0-d6a092807a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988414618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.1988414618
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.748997305
Short name T152
Test name
Test status
Simulation time 313725530876 ps
CPU time 183.54 seconds
Started Jul 19 07:17:59 PM PDT 24
Finished Jul 19 07:21:09 PM PDT 24
Peak memory 201772 kb
Host smart-9c379285-5a8c-4f60-a620-e1febd6a7435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748997305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.748997305
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.1669274149
Short name T679
Test name
Test status
Simulation time 490623285748 ps
CPU time 291.04 seconds
Started Jul 19 07:17:59 PM PDT 24
Finished Jul 19 07:22:56 PM PDT 24
Peak memory 201704 kb
Host smart-b3845204-9ce7-4d1b-8d97-1c6382ba65d4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669274149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interru
pt_fixed.1669274149
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.557169987
Short name T168
Test name
Test status
Simulation time 484665716784 ps
CPU time 266.41 seconds
Started Jul 19 07:18:05 PM PDT 24
Finished Jul 19 07:22:37 PM PDT 24
Peak memory 201744 kb
Host smart-17e17766-77ea-4415-8cbc-1c5edf581010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557169987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.557169987
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.3554654575
Short name T774
Test name
Test status
Simulation time 496404514375 ps
CPU time 193.29 seconds
Started Jul 19 07:18:00 PM PDT 24
Finished Jul 19 07:21:19 PM PDT 24
Peak memory 201808 kb
Host smart-c0e356f9-3af5-4ac3-969c-2ae8fd951742
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554654575 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fix
ed.3554654575
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.3669873164
Short name T169
Test name
Test status
Simulation time 561846682413 ps
CPU time 271.82 seconds
Started Jul 19 07:18:00 PM PDT 24
Finished Jul 19 07:22:38 PM PDT 24
Peak memory 201712 kb
Host smart-2cc2b215-0e57-4b97-86a9-e97bbdd6bb48
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669873164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters
_wakeup.3669873164
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.3244150810
Short name T779
Test name
Test status
Simulation time 193987318089 ps
CPU time 116.91 seconds
Started Jul 19 07:17:59 PM PDT 24
Finished Jul 19 07:20:02 PM PDT 24
Peak memory 201732 kb
Host smart-84d443c5-862a-44e8-a432-f53e0add50dd
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244150810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.adc_ctrl_filters_wakeup_fixed.3244150810
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.3996036779
Short name T539
Test name
Test status
Simulation time 33445462289 ps
CPU time 20.34 seconds
Started Jul 19 07:17:58 PM PDT 24
Finished Jul 19 07:18:25 PM PDT 24
Peak memory 201736 kb
Host smart-9d3302dd-a43d-4908-9670-076a2d9d161e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996036779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.3996036779
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.3203409418
Short name T374
Test name
Test status
Simulation time 5193733423 ps
CPU time 13.02 seconds
Started Jul 19 07:17:59 PM PDT 24
Finished Jul 19 07:18:19 PM PDT 24
Peak memory 201616 kb
Host smart-a64393b1-c98a-47d5-8469-b7f5eddf793b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203409418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.3203409418
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.2777476002
Short name T351
Test name
Test status
Simulation time 5964732767 ps
CPU time 3.01 seconds
Started Jul 19 07:18:00 PM PDT 24
Finished Jul 19 07:18:09 PM PDT 24
Peak memory 201624 kb
Host smart-fdde6fee-9693-4103-9239-7130549fae43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777476002 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.2777476002
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.2423493627
Short name T574
Test name
Test status
Simulation time 4634745640 ps
CPU time 3.84 seconds
Started Jul 19 07:18:01 PM PDT 24
Finished Jul 19 07:18:11 PM PDT 24
Peak memory 201604 kb
Host smart-89337d51-b33a-4b45-a38a-83f067ee01d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423493627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all
.2423493627
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.1966645430
Short name T549
Test name
Test status
Simulation time 544959103 ps
CPU time 0.94 seconds
Started Jul 19 07:18:14 PM PDT 24
Finished Jul 19 07:18:17 PM PDT 24
Peak memory 201504 kb
Host smart-53164809-0229-4643-99cc-6de9bb231bc2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966645430 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.1966645430
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.292189678
Short name T772
Test name
Test status
Simulation time 376799745410 ps
CPU time 33.16 seconds
Started Jul 19 07:18:13 PM PDT 24
Finished Jul 19 07:18:49 PM PDT 24
Peak memory 201700 kb
Host smart-dc173540-c9fe-498e-865b-bfc8f43f75f3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292189678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gati
ng.292189678
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.572195379
Short name T281
Test name
Test status
Simulation time 386169973556 ps
CPU time 843.21 seconds
Started Jul 19 07:18:09 PM PDT 24
Finished Jul 19 07:32:18 PM PDT 24
Peak memory 201724 kb
Host smart-58a2f67e-700e-4fb8-b925-49e2feee91f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572195379 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.572195379
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.4063476249
Short name T215
Test name
Test status
Simulation time 329254156172 ps
CPU time 385.47 seconds
Started Jul 19 07:17:58 PM PDT 24
Finished Jul 19 07:24:30 PM PDT 24
Peak memory 201756 kb
Host smart-5446db44-51f8-4d2e-9698-8a89af7d94c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063476249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.4063476249
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.4009877603
Short name T512
Test name
Test status
Simulation time 496623201622 ps
CPU time 1203.47 seconds
Started Jul 19 07:18:11 PM PDT 24
Finished Jul 19 07:38:19 PM PDT 24
Peak memory 201724 kb
Host smart-abd741b6-4eb6-454d-9cdd-553eb8d0ee63
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009877603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interru
pt_fixed.4009877603
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.4064566569
Short name T306
Test name
Test status
Simulation time 163811682019 ps
CPU time 104.49 seconds
Started Jul 19 07:18:05 PM PDT 24
Finished Jul 19 07:19:55 PM PDT 24
Peak memory 201800 kb
Host smart-467d773b-6233-4598-b00a-5be4c332aa43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064566569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.4064566569
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.3908761791
Short name T758
Test name
Test status
Simulation time 159390887678 ps
CPU time 71.58 seconds
Started Jul 19 07:17:58 PM PDT 24
Finished Jul 19 07:19:17 PM PDT 24
Peak memory 201684 kb
Host smart-692b4c10-b65f-4adf-acde-672f8bb9bea2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908761791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fix
ed.3908761791
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.4120974267
Short name T467
Test name
Test status
Simulation time 192735447936 ps
CPU time 242.3 seconds
Started Jul 19 07:18:09 PM PDT 24
Finished Jul 19 07:22:17 PM PDT 24
Peak memory 201764 kb
Host smart-79ca939b-e0c9-4400-b07f-aacdf8c8b1e4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120974267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters
_wakeup.4120974267
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.1411361694
Short name T591
Test name
Test status
Simulation time 201282734340 ps
CPU time 453.13 seconds
Started Jul 19 07:18:11 PM PDT 24
Finished Jul 19 07:25:48 PM PDT 24
Peak memory 201748 kb
Host smart-2684ca80-6f38-4a6d-b641-a8757d6801f0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411361694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.adc_ctrl_filters_wakeup_fixed.1411361694
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.2445405045
Short name T45
Test name
Test status
Simulation time 105626927062 ps
CPU time 381.16 seconds
Started Jul 19 07:18:13 PM PDT 24
Finished Jul 19 07:24:37 PM PDT 24
Peak memory 202152 kb
Host smart-2cda7c8d-95a5-434c-b453-b6b06d3d2d21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445405045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.2445405045
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.2925232257
Short name T634
Test name
Test status
Simulation time 29063032626 ps
CPU time 70.14 seconds
Started Jul 19 07:18:14 PM PDT 24
Finished Jul 19 07:19:26 PM PDT 24
Peak memory 201564 kb
Host smart-7a131565-9437-409a-8097-16f7f3374552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925232257 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.2925232257
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.3724649844
Short name T686
Test name
Test status
Simulation time 5461499182 ps
CPU time 9.6 seconds
Started Jul 19 07:18:11 PM PDT 24
Finished Jul 19 07:18:25 PM PDT 24
Peak memory 201616 kb
Host smart-8257c7fc-7ead-488e-878c-f367987c9d22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724649844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.3724649844
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.1056881603
Short name T629
Test name
Test status
Simulation time 6004805658 ps
CPU time 4.58 seconds
Started Jul 19 07:18:05 PM PDT 24
Finished Jul 19 07:18:15 PM PDT 24
Peak memory 201588 kb
Host smart-3cb59228-6f97-43f3-a4b6-d7df1b9c559b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056881603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.1056881603
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.1966163972
Short name T233
Test name
Test status
Simulation time 165425988772 ps
CPU time 375.36 seconds
Started Jul 19 07:18:10 PM PDT 24
Finished Jul 19 07:24:30 PM PDT 24
Peak memory 201780 kb
Host smart-0065ab74-9a57-4cbd-9c5a-b53997defa6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966163972 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all
.1966163972
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.1717734538
Short name T21
Test name
Test status
Simulation time 37312332144 ps
CPU time 88.92 seconds
Started Jul 19 07:18:10 PM PDT 24
Finished Jul 19 07:19:44 PM PDT 24
Peak memory 201872 kb
Host smart-5cd71446-a317-4e82-bdcd-8922708f061d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717734538 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.1717734538
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.3032626040
Short name T631
Test name
Test status
Simulation time 480892672 ps
CPU time 1.18 seconds
Started Jul 19 07:18:24 PM PDT 24
Finished Jul 19 07:18:31 PM PDT 24
Peak memory 201532 kb
Host smart-d9d22d1e-6b7b-4f89-b174-bed2ef248f0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032626040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.3032626040
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.1450965624
Short name T147
Test name
Test status
Simulation time 508982334084 ps
CPU time 297.77 seconds
Started Jul 19 07:18:21 PM PDT 24
Finished Jul 19 07:23:23 PM PDT 24
Peak memory 201780 kb
Host smart-61a07502-3216-45b4-9d2b-b10d02a6aa67
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450965624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gat
ing.1450965624
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.1558406302
Short name T770
Test name
Test status
Simulation time 588011028214 ps
CPU time 351.85 seconds
Started Jul 19 07:18:24 PM PDT 24
Finished Jul 19 07:24:21 PM PDT 24
Peak memory 201756 kb
Host smart-5eed0b26-8f3b-4e32-bef3-ad9852529197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558406302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.1558406302
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.3832584336
Short name T587
Test name
Test status
Simulation time 166392160128 ps
CPU time 95.32 seconds
Started Jul 19 07:18:12 PM PDT 24
Finished Jul 19 07:19:51 PM PDT 24
Peak memory 201756 kb
Host smart-8c1bf9fb-4cf8-4521-90e8-0d279564afa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832584336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.3832584336
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.3994950619
Short name T177
Test name
Test status
Simulation time 322215780664 ps
CPU time 159.01 seconds
Started Jul 19 07:18:21 PM PDT 24
Finished Jul 19 07:21:04 PM PDT 24
Peak memory 201704 kb
Host smart-db9eb9f4-ff25-4bb8-946a-a47b3f52b06a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994950619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interru
pt_fixed.3994950619
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.1435039014
Short name T735
Test name
Test status
Simulation time 329048000682 ps
CPU time 376.62 seconds
Started Jul 19 07:18:10 PM PDT 24
Finished Jul 19 07:24:32 PM PDT 24
Peak memory 201724 kb
Host smart-062c0d9f-d2c1-4d65-98bd-58010b8114a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435039014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.1435039014
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.2432958804
Short name T573
Test name
Test status
Simulation time 327107560033 ps
CPU time 210.1 seconds
Started Jul 19 07:18:10 PM PDT 24
Finished Jul 19 07:21:45 PM PDT 24
Peak memory 201804 kb
Host smart-668e05bb-26fc-4a7f-b736-52452a9c6fb8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432958804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fix
ed.2432958804
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.2537407159
Short name T275
Test name
Test status
Simulation time 593916223507 ps
CPU time 1355.17 seconds
Started Jul 19 07:18:22 PM PDT 24
Finished Jul 19 07:41:01 PM PDT 24
Peak memory 201832 kb
Host smart-cce4256d-200c-422c-87fb-4bd25d57ffb6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537407159 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters
_wakeup.2537407159
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.3975476819
Short name T532
Test name
Test status
Simulation time 393645075635 ps
CPU time 227.4 seconds
Started Jul 19 07:18:21 PM PDT 24
Finished Jul 19 07:22:12 PM PDT 24
Peak memory 201872 kb
Host smart-d6ea69bb-20a2-4a17-ac5e-a0f74c897e1a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975476819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.adc_ctrl_filters_wakeup_fixed.3975476819
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.1949480098
Short name T714
Test name
Test status
Simulation time 74789446939 ps
CPU time 404.22 seconds
Started Jul 19 07:18:22 PM PDT 24
Finished Jul 19 07:25:11 PM PDT 24
Peak memory 202104 kb
Host smart-cba1ea0f-0684-4d2c-9877-7d97a7295691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949480098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.1949480098
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.175891592
Short name T608
Test name
Test status
Simulation time 34507454099 ps
CPU time 81.91 seconds
Started Jul 19 07:18:22 PM PDT 24
Finished Jul 19 07:19:47 PM PDT 24
Peak memory 201616 kb
Host smart-2997c846-ef16-412e-b0f7-1d7fc0c931fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175891592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.175891592
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.1382283957
Short name T485
Test name
Test status
Simulation time 4129433404 ps
CPU time 3.3 seconds
Started Jul 19 07:18:23 PM PDT 24
Finished Jul 19 07:18:31 PM PDT 24
Peak memory 201584 kb
Host smart-f6f46de7-12d0-446d-bae5-279dc9674bde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382283957 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.1382283957
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.2710690361
Short name T421
Test name
Test status
Simulation time 5989439235 ps
CPU time 3.95 seconds
Started Jul 19 07:18:11 PM PDT 24
Finished Jul 19 07:18:19 PM PDT 24
Peak memory 201576 kb
Host smart-0f58f45c-b982-4e49-9e5c-d36801fc9817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710690361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.2710690361
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.2268337786
Short name T537
Test name
Test status
Simulation time 520004086371 ps
CPU time 303.03 seconds
Started Jul 19 07:18:23 PM PDT 24
Finished Jul 19 07:23:30 PM PDT 24
Peak memory 201760 kb
Host smart-c8d00860-8183-4e93-9a2c-6bc583cbf59b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268337786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all
.2268337786
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.1193223553
Short name T17
Test name
Test status
Simulation time 126282749750 ps
CPU time 36.13 seconds
Started Jul 19 07:18:24 PM PDT 24
Finished Jul 19 07:19:05 PM PDT 24
Peak memory 201880 kb
Host smart-9e4666e6-fa93-4aee-8c34-c57b5fc7c1ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193223553 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.1193223553
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.1052673711
Short name T531
Test name
Test status
Simulation time 308324658 ps
CPU time 1.34 seconds
Started Jul 19 07:18:32 PM PDT 24
Finished Jul 19 07:18:37 PM PDT 24
Peak memory 201552 kb
Host smart-5ddba333-24da-4a79-9d4a-410573b85e3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052673711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.1052673711
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.99622501
Short name T769
Test name
Test status
Simulation time 338422988170 ps
CPU time 116.05 seconds
Started Jul 19 07:18:31 PM PDT 24
Finished Jul 19 07:20:32 PM PDT 24
Peak memory 201748 kb
Host smart-731af6b3-6daa-4ca5-a7ab-3eacc4ddec8e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99622501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gatin
g.99622501
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.1717639983
Short name T269
Test name
Test status
Simulation time 188053224201 ps
CPU time 125.32 seconds
Started Jul 19 07:18:34 PM PDT 24
Finished Jul 19 07:20:44 PM PDT 24
Peak memory 201832 kb
Host smart-ea661089-82d0-41bd-9593-28e829a45a79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717639983 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.1717639983
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.1042898425
Short name T172
Test name
Test status
Simulation time 326656640887 ps
CPU time 150.48 seconds
Started Jul 19 07:18:31 PM PDT 24
Finished Jul 19 07:21:06 PM PDT 24
Peak memory 201716 kb
Host smart-d0b5f82b-a765-4287-8fa1-70b4609ce52e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042898425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.1042898425
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.4201701335
Short name T514
Test name
Test status
Simulation time 322677917582 ps
CPU time 698.18 seconds
Started Jul 19 07:18:34 PM PDT 24
Finished Jul 19 07:30:17 PM PDT 24
Peak memory 201736 kb
Host smart-b174d135-d168-4c8f-99ff-01facbbee272
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201701335 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interru
pt_fixed.4201701335
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.541524749
Short name T606
Test name
Test status
Simulation time 327202366401 ps
CPU time 419.93 seconds
Started Jul 19 07:18:25 PM PDT 24
Finished Jul 19 07:25:29 PM PDT 24
Peak memory 201748 kb
Host smart-f83e42fc-7f83-491f-a2e3-849e0c55c668
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=541524749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fixe
d.541524749
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.1724117292
Short name T521
Test name
Test status
Simulation time 186439372284 ps
CPU time 434.52 seconds
Started Jul 19 07:18:34 PM PDT 24
Finished Jul 19 07:25:53 PM PDT 24
Peak memory 201740 kb
Host smart-f8fb7580-9602-4be9-b2ef-b3482c12276b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724117292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters
_wakeup.1724117292
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.3123138950
Short name T460
Test name
Test status
Simulation time 190276697603 ps
CPU time 470.99 seconds
Started Jul 19 07:18:33 PM PDT 24
Finished Jul 19 07:26:28 PM PDT 24
Peak memory 201732 kb
Host smart-f9037f35-b000-45e0-9c89-4decd575f891
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123138950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.adc_ctrl_filters_wakeup_fixed.3123138950
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.1992888573
Short name T612
Test name
Test status
Simulation time 71681141612 ps
CPU time 249.18 seconds
Started Jul 19 07:18:33 PM PDT 24
Finished Jul 19 07:22:47 PM PDT 24
Peak memory 202204 kb
Host smart-84ca22a9-57a0-4fd8-b783-26a271dbdcb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992888573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.1992888573
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.1069560539
Short name T556
Test name
Test status
Simulation time 35942437694 ps
CPU time 42.44 seconds
Started Jul 19 07:18:32 PM PDT 24
Finished Jul 19 07:19:18 PM PDT 24
Peak memory 201600 kb
Host smart-2b1612e1-9149-4e8a-92ea-25433aa606e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069560539 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.1069560539
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.2306181132
Short name T328
Test name
Test status
Simulation time 2951077053 ps
CPU time 8.08 seconds
Started Jul 19 07:18:33 PM PDT 24
Finished Jul 19 07:18:45 PM PDT 24
Peak memory 201592 kb
Host smart-3846e7f1-ef0f-445d-8a2a-240dd4146d60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306181132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.2306181132
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.3322140699
Short name T525
Test name
Test status
Simulation time 5901342812 ps
CPU time 4.3 seconds
Started Jul 19 07:18:22 PM PDT 24
Finished Jul 19 07:18:31 PM PDT 24
Peak memory 201632 kb
Host smart-7c6b7f49-daae-451b-a75d-2c79298cbb6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322140699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.3322140699
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.4046108138
Short name T31
Test name
Test status
Simulation time 86368310147 ps
CPU time 142.43 seconds
Started Jul 19 07:18:33 PM PDT 24
Finished Jul 19 07:20:59 PM PDT 24
Peak memory 210496 kb
Host smart-f7f43195-11c8-461f-bc1a-d6f82ce1f0cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046108138 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.4046108138
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.1051100266
Short name T592
Test name
Test status
Simulation time 367684859 ps
CPU time 0.84 seconds
Started Jul 19 07:18:43 PM PDT 24
Finished Jul 19 07:18:45 PM PDT 24
Peak memory 201540 kb
Host smart-3264b69b-2809-419b-9981-701bb76597f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051100266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.1051100266
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.1351706034
Short name T544
Test name
Test status
Simulation time 514977918080 ps
CPU time 1150.24 seconds
Started Jul 19 07:18:42 PM PDT 24
Finished Jul 19 07:37:53 PM PDT 24
Peak memory 201756 kb
Host smart-96d6d60f-fb83-46ff-bc87-ce125c1d6645
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351706034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gat
ing.1351706034
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.2074685602
Short name T320
Test name
Test status
Simulation time 334275583257 ps
CPU time 200.46 seconds
Started Jul 19 07:18:46 PM PDT 24
Finished Jul 19 07:22:09 PM PDT 24
Peak memory 201828 kb
Host smart-5972f964-1e69-48d8-a83d-e836b09511b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074685602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.2074685602
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.3870001101
Short name T707
Test name
Test status
Simulation time 166146660818 ps
CPU time 175.96 seconds
Started Jul 19 07:18:32 PM PDT 24
Finished Jul 19 07:21:33 PM PDT 24
Peak memory 201760 kb
Host smart-2fdc626a-a431-438d-a4a2-3f3ab082fa3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870001101 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.3870001101
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.1277449144
Short name T452
Test name
Test status
Simulation time 323549876450 ps
CPU time 195.39 seconds
Started Jul 19 07:18:46 PM PDT 24
Finished Jul 19 07:22:04 PM PDT 24
Peak memory 201708 kb
Host smart-1c8d6c51-3ae7-4efe-ace2-6cc405e563f9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277449144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interru
pt_fixed.1277449144
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.1848312102
Short name T473
Test name
Test status
Simulation time 164424500713 ps
CPU time 395.16 seconds
Started Jul 19 07:18:32 PM PDT 24
Finished Jul 19 07:25:11 PM PDT 24
Peak memory 201764 kb
Host smart-de0d2b49-606e-4987-a6c2-f956007acb22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848312102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.1848312102
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.1418447973
Short name T385
Test name
Test status
Simulation time 162401593725 ps
CPU time 198.1 seconds
Started Jul 19 07:18:33 PM PDT 24
Finished Jul 19 07:21:56 PM PDT 24
Peak memory 201684 kb
Host smart-e11ee0bb-d385-4dd6-880f-ddea49f0c6df
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418447973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fix
ed.1418447973
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.1443342387
Short name T122
Test name
Test status
Simulation time 192580135774 ps
CPU time 92.04 seconds
Started Jul 19 07:18:45 PM PDT 24
Finished Jul 19 07:20:19 PM PDT 24
Peak memory 201772 kb
Host smart-b981af44-7166-418d-b45c-242a9a7157ab
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443342387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters
_wakeup.1443342387
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.3010575278
Short name T381
Test name
Test status
Simulation time 608039662446 ps
CPU time 1472.83 seconds
Started Jul 19 07:18:43 PM PDT 24
Finished Jul 19 07:43:17 PM PDT 24
Peak memory 201792 kb
Host smart-9cc8b736-6e68-43a5-96b8-d89c43c020cb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010575278 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.adc_ctrl_filters_wakeup_fixed.3010575278
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.3699991364
Short name T193
Test name
Test status
Simulation time 97974686724 ps
CPU time 519.09 seconds
Started Jul 19 07:18:43 PM PDT 24
Finished Jul 19 07:27:24 PM PDT 24
Peak memory 202132 kb
Host smart-c3fa8689-3f22-403b-9bf1-a2149f4e5b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699991364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.3699991364
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.1917881767
Short name T369
Test name
Test status
Simulation time 36296749428 ps
CPU time 20.43 seconds
Started Jul 19 07:18:44 PM PDT 24
Finished Jul 19 07:19:06 PM PDT 24
Peak memory 201604 kb
Host smart-69eea132-e7b1-407e-88b6-f38d87b96ea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917881767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.1917881767
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.1687706827
Short name T746
Test name
Test status
Simulation time 4271914583 ps
CPU time 11.47 seconds
Started Jul 19 07:18:43 PM PDT 24
Finished Jul 19 07:18:56 PM PDT 24
Peak memory 201556 kb
Host smart-7a6c22d9-e262-4d2a-a32c-06bf495b5e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687706827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.1687706827
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.1212799444
Short name T600
Test name
Test status
Simulation time 5873019874 ps
CPU time 2.37 seconds
Started Jul 19 07:18:34 PM PDT 24
Finished Jul 19 07:18:40 PM PDT 24
Peak memory 201628 kb
Host smart-08dd039f-fab1-4ef3-9100-b95295143106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212799444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.1212799444
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.1527382
Short name T280
Test name
Test status
Simulation time 384899313119 ps
CPU time 861.2 seconds
Started Jul 19 07:18:44 PM PDT 24
Finished Jul 19 07:33:07 PM PDT 24
Peak memory 201756 kb
Host smart-98542ed7-2d3a-4363-91ed-183aabf3d4fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527382 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_a
ll_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all.1527382
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.272715357
Short name T78
Test name
Test status
Simulation time 40798692926 ps
CPU time 46.84 seconds
Started Jul 19 07:18:45 PM PDT 24
Finished Jul 19 07:19:34 PM PDT 24
Peak memory 210616 kb
Host smart-0a8ed31e-95bb-4c2b-9a7d-65fbba919af1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272715357 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.272715357
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.2291837158
Short name T491
Test name
Test status
Simulation time 436132467 ps
CPU time 0.87 seconds
Started Jul 19 07:19:00 PM PDT 24
Finished Jul 19 07:19:04 PM PDT 24
Peak memory 201556 kb
Host smart-bab44ef4-b252-4494-81f7-86f315ee5c4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291837158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.2291837158
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.2895635468
Short name T149
Test name
Test status
Simulation time 550070656522 ps
CPU time 99.82 seconds
Started Jul 19 07:18:59 PM PDT 24
Finished Jul 19 07:20:41 PM PDT 24
Peak memory 201732 kb
Host smart-0d274a89-5761-474d-9063-bcade4fe5433
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895635468 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gat
ing.2895635468
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.2874702231
Short name T468
Test name
Test status
Simulation time 164386805836 ps
CPU time 75.53 seconds
Started Jul 19 07:18:42 PM PDT 24
Finished Jul 19 07:19:59 PM PDT 24
Peak memory 201708 kb
Host smart-825e88f2-1950-46d2-8c37-de6eb3aec2d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874702231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.2874702231
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.2427438023
Short name T335
Test name
Test status
Simulation time 334209984385 ps
CPU time 426.11 seconds
Started Jul 19 07:18:44 PM PDT 24
Finished Jul 19 07:25:52 PM PDT 24
Peak memory 201716 kb
Host smart-4f205954-c598-42c3-a9ce-64e912c7125e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427438023 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interru
pt_fixed.2427438023
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.2076094277
Short name T129
Test name
Test status
Simulation time 319255257189 ps
CPU time 208.23 seconds
Started Jul 19 07:18:46 PM PDT 24
Finished Jul 19 07:22:16 PM PDT 24
Peak memory 201828 kb
Host smart-d823afab-278d-4fc2-accd-8ac7deef545d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076094277 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.2076094277
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.1335988577
Short name T533
Test name
Test status
Simulation time 167263758545 ps
CPU time 53.8 seconds
Started Jul 19 07:18:43 PM PDT 24
Finished Jul 19 07:19:39 PM PDT 24
Peak memory 201744 kb
Host smart-dcdea138-7621-431a-8be9-2bf1e6ce6f06
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335988577 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fix
ed.1335988577
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.3861491602
Short name T613
Test name
Test status
Simulation time 191787654541 ps
CPU time 409.66 seconds
Started Jul 19 07:19:00 PM PDT 24
Finished Jul 19 07:25:52 PM PDT 24
Peak memory 201828 kb
Host smart-f2684a3e-1c1e-4434-8a14-86eed8e835a4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861491602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters
_wakeup.3861491602
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.2615775214
Short name T637
Test name
Test status
Simulation time 400512418694 ps
CPU time 878.38 seconds
Started Jul 19 07:18:59 PM PDT 24
Finished Jul 19 07:33:40 PM PDT 24
Peak memory 201732 kb
Host smart-babbf8dd-f73f-45d0-9df7-356ba882af2e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615775214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.adc_ctrl_filters_wakeup_fixed.2615775214
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.3972963048
Short name T345
Test name
Test status
Simulation time 112135943212 ps
CPU time 403.42 seconds
Started Jul 19 07:19:02 PM PDT 24
Finished Jul 19 07:25:48 PM PDT 24
Peak memory 202120 kb
Host smart-37634292-75dc-4c16-84df-4a7d0702b3a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972963048 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.3972963048
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.2325414798
Short name T720
Test name
Test status
Simulation time 48237500671 ps
CPU time 115.49 seconds
Started Jul 19 07:18:58 PM PDT 24
Finished Jul 19 07:20:55 PM PDT 24
Peak memory 201616 kb
Host smart-850a7bef-25fc-4632-8e8e-3cd317d19f64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325414798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.2325414798
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.2686815918
Short name T730
Test name
Test status
Simulation time 3497990637 ps
CPU time 8.17 seconds
Started Jul 19 07:18:58 PM PDT 24
Finished Jul 19 07:19:08 PM PDT 24
Peak memory 201564 kb
Host smart-850ed553-5373-4fd5-9cc2-96cd7363544e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686815918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.2686815918
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.3691150526
Short name T745
Test name
Test status
Simulation time 6003032494 ps
CPU time 2 seconds
Started Jul 19 07:18:43 PM PDT 24
Finished Jul 19 07:18:47 PM PDT 24
Peak memory 201632 kb
Host smart-f9ce34e2-a804-4c58-bfa3-1b5e1bd1d209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691150526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.3691150526
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.4239679704
Short name T416
Test name
Test status
Simulation time 6525720159 ps
CPU time 2.29 seconds
Started Jul 19 07:18:59 PM PDT 24
Finished Jul 19 07:19:03 PM PDT 24
Peak memory 201592 kb
Host smart-91d710b9-2eff-4dc7-af4d-986014e15f9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239679704 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all
.4239679704
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.2911057487
Short name T81
Test name
Test status
Simulation time 163627540695 ps
CPU time 114.32 seconds
Started Jul 19 07:18:59 PM PDT 24
Finished Jul 19 07:20:56 PM PDT 24
Peak memory 210448 kb
Host smart-02b5c7ac-8664-40a8-994e-a50b7a09845a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911057487 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.2911057487
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.741552854
Short name T61
Test name
Test status
Simulation time 405357672 ps
CPU time 1.66 seconds
Started Jul 19 07:19:17 PM PDT 24
Finished Jul 19 07:19:21 PM PDT 24
Peak memory 201540 kb
Host smart-7c916017-8d55-4132-b6ee-cbbe17a29270
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741552854 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.741552854
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.1308737005
Short name T752
Test name
Test status
Simulation time 169659042170 ps
CPU time 24.33 seconds
Started Jul 19 07:19:14 PM PDT 24
Finished Jul 19 07:19:39 PM PDT 24
Peak memory 201724 kb
Host smart-89b0952c-73c3-4da2-be2d-ebac241180fc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308737005 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gat
ing.1308737005
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.3436052416
Short name T754
Test name
Test status
Simulation time 161705551403 ps
CPU time 55.98 seconds
Started Jul 19 07:19:15 PM PDT 24
Finished Jul 19 07:20:13 PM PDT 24
Peak memory 201752 kb
Host smart-2de1c122-14d9-45a9-a8b7-8706b050fe8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436052416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.3436052416
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.742562056
Short name T323
Test name
Test status
Simulation time 325977197433 ps
CPU time 389.9 seconds
Started Jul 19 07:18:59 PM PDT 24
Finished Jul 19 07:25:32 PM PDT 24
Peak memory 201752 kb
Host smart-046ba52c-6530-4f9c-85b3-e67953a4bdcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742562056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.742562056
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.595321523
Short name T740
Test name
Test status
Simulation time 492329972690 ps
CPU time 1222.2 seconds
Started Jul 19 07:19:15 PM PDT 24
Finished Jul 19 07:39:38 PM PDT 24
Peak memory 201732 kb
Host smart-1534717d-127e-41a0-89e9-9d9a03ca5a8d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=595321523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrup
t_fixed.595321523
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.3767845965
Short name T302
Test name
Test status
Simulation time 170963922135 ps
CPU time 103.76 seconds
Started Jul 19 07:18:59 PM PDT 24
Finished Jul 19 07:20:45 PM PDT 24
Peak memory 201772 kb
Host smart-84b44829-9d1b-4551-b4ca-44127d1e6464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767845965 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.3767845965
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.1274107697
Short name T738
Test name
Test status
Simulation time 164113803705 ps
CPU time 389.38 seconds
Started Jul 19 07:18:59 PM PDT 24
Finished Jul 19 07:25:31 PM PDT 24
Peak memory 201752 kb
Host smart-c1d0ab57-42ab-48d7-8197-e84df00a7247
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274107697 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fix
ed.1274107697
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.2270433168
Short name T753
Test name
Test status
Simulation time 606343901451 ps
CPU time 1397.9 seconds
Started Jul 19 07:19:16 PM PDT 24
Finished Jul 19 07:42:37 PM PDT 24
Peak memory 201804 kb
Host smart-cf1cfd8f-d960-4816-ac2c-d51738f3a912
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270433168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.adc_ctrl_filters_wakeup_fixed.2270433168
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.1064237103
Short name T747
Test name
Test status
Simulation time 102463787623 ps
CPU time 385.13 seconds
Started Jul 19 07:19:18 PM PDT 24
Finished Jul 19 07:25:45 PM PDT 24
Peak memory 202120 kb
Host smart-dd89b889-0406-41d9-9167-bfc73cdc081f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064237103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.1064237103
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.3897092222
Short name T348
Test name
Test status
Simulation time 35910530836 ps
CPU time 44.03 seconds
Started Jul 19 07:19:16 PM PDT 24
Finished Jul 19 07:20:03 PM PDT 24
Peak memory 201612 kb
Host smart-771a1f9d-0c4b-42b2-a6e7-39ae59c96725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897092222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.3897092222
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.3127944651
Short name T771
Test name
Test status
Simulation time 3641423435 ps
CPU time 9.48 seconds
Started Jul 19 07:19:16 PM PDT 24
Finished Jul 19 07:19:27 PM PDT 24
Peak memory 201588 kb
Host smart-6499584d-343b-478f-a438-d4474f9fa92b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127944651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.3127944651
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.2526910558
Short name T377
Test name
Test status
Simulation time 6185105765 ps
CPU time 15.56 seconds
Started Jul 19 07:19:02 PM PDT 24
Finished Jul 19 07:19:20 PM PDT 24
Peak memory 201592 kb
Host smart-f8d78995-54ac-462d-bf68-82a506051cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526910558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.2526910558
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.4155321672
Short name T247
Test name
Test status
Simulation time 345441115945 ps
CPU time 224.89 seconds
Started Jul 19 07:19:17 PM PDT 24
Finished Jul 19 07:23:04 PM PDT 24
Peak memory 201724 kb
Host smart-d35e6e7b-1af6-4c91-8b92-f3048abf855e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155321672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all
.4155321672
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.3894277891
Short name T206
Test name
Test status
Simulation time 783964121317 ps
CPU time 158.35 seconds
Started Jul 19 07:19:17 PM PDT 24
Finished Jul 19 07:21:57 PM PDT 24
Peak memory 210108 kb
Host smart-e3322fac-a004-4223-a401-b2b3275e8d96
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894277891 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.3894277891
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.2572234748
Short name T705
Test name
Test status
Simulation time 422267288 ps
CPU time 0.87 seconds
Started Jul 19 07:19:25 PM PDT 24
Finished Jul 19 07:19:28 PM PDT 24
Peak memory 201560 kb
Host smart-68475816-4b37-4959-9d5f-d8d6890a1748
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572234748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.2572234748
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.653033238
Short name T692
Test name
Test status
Simulation time 165223762781 ps
CPU time 178.55 seconds
Started Jul 19 07:19:15 PM PDT 24
Finished Jul 19 07:22:14 PM PDT 24
Peak memory 201748 kb
Host smart-3b1b4f58-7ef1-4640-9b58-01ef8c40f0e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653033238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.653033238
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.3235256914
Short name T540
Test name
Test status
Simulation time 164980695239 ps
CPU time 358.57 seconds
Started Jul 19 07:19:16 PM PDT 24
Finished Jul 19 07:25:17 PM PDT 24
Peak memory 201748 kb
Host smart-aa36a815-49a5-4d61-bf14-78b30e2bdc59
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235256914 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interru
pt_fixed.3235256914
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.1923077886
Short name T282
Test name
Test status
Simulation time 490617597031 ps
CPU time 142.58 seconds
Started Jul 19 07:19:16 PM PDT 24
Finished Jul 19 07:21:40 PM PDT 24
Peak memory 201756 kb
Host smart-3219ed91-665f-4571-bcec-2a809392c5a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923077886 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.1923077886
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.1215661378
Short name T695
Test name
Test status
Simulation time 489211635179 ps
CPU time 1196.07 seconds
Started Jul 19 07:19:14 PM PDT 24
Finished Jul 19 07:39:12 PM PDT 24
Peak memory 201724 kb
Host smart-3e0f9f27-9878-4440-b78d-1f20c2870877
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215661378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fix
ed.1215661378
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.2092059209
Short name T594
Test name
Test status
Simulation time 182680935685 ps
CPU time 165.14 seconds
Started Jul 19 07:19:17 PM PDT 24
Finished Jul 19 07:22:04 PM PDT 24
Peak memory 201872 kb
Host smart-2c1ead15-fbae-4750-bb5e-5298fa4618d7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092059209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters
_wakeup.2092059209
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.1034802072
Short name T450
Test name
Test status
Simulation time 594203430917 ps
CPU time 329.16 seconds
Started Jul 19 07:19:16 PM PDT 24
Finished Jul 19 07:24:47 PM PDT 24
Peak memory 201792 kb
Host smart-5d99c705-bfcd-481a-bbd7-8513d10d3288
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034802072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.adc_ctrl_filters_wakeup_fixed.1034802072
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.1833709224
Short name T419
Test name
Test status
Simulation time 64473210395 ps
CPU time 298.41 seconds
Started Jul 19 07:19:27 PM PDT 24
Finished Jul 19 07:24:30 PM PDT 24
Peak memory 202100 kb
Host smart-de5f1bca-5f29-4cfc-8c58-5a816941e52a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833709224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.1833709224
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.764231062
Short name T682
Test name
Test status
Simulation time 41226949587 ps
CPU time 24.45 seconds
Started Jul 19 07:19:28 PM PDT 24
Finished Jul 19 07:19:58 PM PDT 24
Peak memory 201616 kb
Host smart-e6c6667a-794a-4ebb-8bd5-59dd00da66ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764231062 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.764231062
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.516249215
Short name T1
Test name
Test status
Simulation time 3019377269 ps
CPU time 2.34 seconds
Started Jul 19 07:19:14 PM PDT 24
Finished Jul 19 07:19:17 PM PDT 24
Peak memory 201584 kb
Host smart-be1584c2-b830-48dd-b0cf-f8fc8425e9fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516249215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.516249215
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.877069931
Short name T675
Test name
Test status
Simulation time 5656209847 ps
CPU time 7.36 seconds
Started Jul 19 07:19:15 PM PDT 24
Finished Jul 19 07:19:24 PM PDT 24
Peak memory 201624 kb
Host smart-03337ea4-1c0b-4751-98c5-6e146c867a93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877069931 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.877069931
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.1554163222
Short name T291
Test name
Test status
Simulation time 326090983706 ps
CPU time 72.69 seconds
Started Jul 19 07:19:25 PM PDT 24
Finished Jul 19 07:20:40 PM PDT 24
Peak memory 201736 kb
Host smart-be90fbf2-3145-45dc-9c62-6121d5b63443
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554163222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all
.1554163222
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.3858642010
Short name T650
Test name
Test status
Simulation time 57037721251 ps
CPU time 132.33 seconds
Started Jul 19 07:19:27 PM PDT 24
Finished Jul 19 07:21:44 PM PDT 24
Peak memory 201924 kb
Host smart-062252ca-7f2a-4505-9d31-2cb211cf4931
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858642010 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.3858642010
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.4003987820
Short name T331
Test name
Test status
Simulation time 496934091 ps
CPU time 1.82 seconds
Started Jul 19 07:08:12 PM PDT 24
Finished Jul 19 07:08:14 PM PDT 24
Peak memory 201660 kb
Host smart-352c1a96-938b-4126-8f9f-cc0692de52b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003987820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.4003987820
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.1540154595
Short name T224
Test name
Test status
Simulation time 525329719411 ps
CPU time 321.83 seconds
Started Jul 19 07:08:09 PM PDT 24
Finished Jul 19 07:13:32 PM PDT 24
Peak memory 201752 kb
Host smart-49004933-7f05-4c2f-b0ec-f07c07839601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540154595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.1540154595
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.3354258885
Short name T150
Test name
Test status
Simulation time 494270379926 ps
CPU time 1113.76 seconds
Started Jul 19 07:07:52 PM PDT 24
Finished Jul 19 07:26:27 PM PDT 24
Peak memory 201804 kb
Host smart-0f69818f-28c8-4aa5-bd61-7f8a57cf39f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354258885 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.3354258885
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.2005128548
Short name T526
Test name
Test status
Simulation time 494812984240 ps
CPU time 1170.25 seconds
Started Jul 19 07:07:51 PM PDT 24
Finished Jul 19 07:27:22 PM PDT 24
Peak memory 201712 kb
Host smart-3e8c8a8a-2e4d-4ca9-8f8b-e97961ba447e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005128548 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrup
t_fixed.2005128548
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.2512279095
Short name T622
Test name
Test status
Simulation time 161800743796 ps
CPU time 84.6 seconds
Started Jul 19 07:07:52 PM PDT 24
Finished Jul 19 07:09:17 PM PDT 24
Peak memory 201824 kb
Host smart-542d1296-9437-47b6-9294-12e4d4377bea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512279095 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.2512279095
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.3198424238
Short name T663
Test name
Test status
Simulation time 163744750602 ps
CPU time 381.08 seconds
Started Jul 19 07:07:59 PM PDT 24
Finished Jul 19 07:14:21 PM PDT 24
Peak memory 201680 kb
Host smart-6d2cf5d9-aec7-4201-ace9-f03ca045a575
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198424238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixe
d.3198424238
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.4261846511
Short name T176
Test name
Test status
Simulation time 526371640269 ps
CPU time 98.29 seconds
Started Jul 19 07:07:51 PM PDT 24
Finished Jul 19 07:09:30 PM PDT 24
Peak memory 201836 kb
Host smart-29ec2e46-9383-4993-8453-632a162331da
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261846511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_
wakeup.4261846511
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.42952820
Short name T496
Test name
Test status
Simulation time 405189781010 ps
CPU time 233.46 seconds
Started Jul 19 07:07:53 PM PDT 24
Finished Jul 19 07:11:47 PM PDT 24
Peak memory 201872 kb
Host smart-53fc7da9-5a31-4273-afd6-d28baeff70d1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42952820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.ad
c_ctrl_filters_wakeup_fixed.42952820
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.2458744845
Short name T507
Test name
Test status
Simulation time 132490940137 ps
CPU time 700.99 seconds
Started Jul 19 07:08:02 PM PDT 24
Finished Jul 19 07:19:43 PM PDT 24
Peak memory 202236 kb
Host smart-54e91b28-29d7-4dd2-905d-da1ae81bafa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458744845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.2458744845
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.1443457102
Short name T576
Test name
Test status
Simulation time 25063063372 ps
CPU time 20.08 seconds
Started Jul 19 07:08:06 PM PDT 24
Finished Jul 19 07:08:27 PM PDT 24
Peak memory 201612 kb
Host smart-101a4f17-a167-4aff-9eac-df0eea534298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443457102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.1443457102
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.1867213565
Short name T366
Test name
Test status
Simulation time 4985833011 ps
CPU time 4.12 seconds
Started Jul 19 07:08:05 PM PDT 24
Finished Jul 19 07:08:10 PM PDT 24
Peak memory 201572 kb
Host smart-3b847267-4da2-4101-aeff-7e4d17c787f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867213565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.1867213565
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.2050757132
Short name T519
Test name
Test status
Simulation time 5735019124 ps
CPU time 2.91 seconds
Started Jul 19 07:07:57 PM PDT 24
Finished Jul 19 07:08:01 PM PDT 24
Peak memory 201628 kb
Host smart-376a379e-2107-416f-a3f4-ccd82d64bf97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050757132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.2050757132
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.958917888
Short name T192
Test name
Test status
Simulation time 99590630646 ps
CPU time 265.26 seconds
Started Jul 19 07:08:02 PM PDT 24
Finished Jul 19 07:12:28 PM PDT 24
Peak memory 211720 kb
Host smart-0f492535-4444-4cfe-8a03-7eac39b683a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958917888 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.958917888
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.301996223
Short name T363
Test name
Test status
Simulation time 465595238 ps
CPU time 0.86 seconds
Started Jul 19 07:08:28 PM PDT 24
Finished Jul 19 07:08:30 PM PDT 24
Peak memory 201664 kb
Host smart-338a9f11-1398-4b97-8f9a-1b320e7ba8da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301996223 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.301996223
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.35243354
Short name T778
Test name
Test status
Simulation time 338360888453 ps
CPU time 769.77 seconds
Started Jul 19 07:08:16 PM PDT 24
Finished Jul 19 07:21:07 PM PDT 24
Peak memory 201712 kb
Host smart-9f9cf6c7-3565-4637-ae49-35027591cc01
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35243354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gating
.35243354
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.1217539062
Short name T777
Test name
Test status
Simulation time 163339036723 ps
CPU time 349.83 seconds
Started Jul 19 07:08:22 PM PDT 24
Finished Jul 19 07:14:12 PM PDT 24
Peak memory 201764 kb
Host smart-95f4d6bf-5ecd-4c11-8953-54c026b9d422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217539062 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.1217539062
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.3061696593
Short name T120
Test name
Test status
Simulation time 493149449268 ps
CPU time 174.52 seconds
Started Jul 19 07:08:20 PM PDT 24
Finished Jul 19 07:11:15 PM PDT 24
Peak memory 201752 kb
Host smart-3fca898b-198f-4de8-8e9e-94805654abee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061696593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.3061696593
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.2411610894
Short name T202
Test name
Test status
Simulation time 165290449571 ps
CPU time 115.91 seconds
Started Jul 19 07:08:22 PM PDT 24
Finished Jul 19 07:10:18 PM PDT 24
Peak memory 201780 kb
Host smart-64f483a3-9704-42b8-81f0-a0232081f80e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411610894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrup
t_fixed.2411610894
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.2392026911
Short name T124
Test name
Test status
Simulation time 335677453528 ps
CPU time 456.45 seconds
Started Jul 19 07:08:10 PM PDT 24
Finished Jul 19 07:15:48 PM PDT 24
Peak memory 201740 kb
Host smart-d2d46031-bf44-49b6-8d45-de2a3d75efab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392026911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.2392026911
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.4058070732
Short name T418
Test name
Test status
Simulation time 167953293830 ps
CPU time 200.92 seconds
Started Jul 19 07:08:10 PM PDT 24
Finished Jul 19 07:11:32 PM PDT 24
Peak memory 201764 kb
Host smart-eeae219a-c385-49de-a308-72cbc82eaab6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058070732 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixe
d.4058070732
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.2662241756
Short name T170
Test name
Test status
Simulation time 556501284464 ps
CPU time 364.18 seconds
Started Jul 19 07:08:18 PM PDT 24
Finished Jul 19 07:14:23 PM PDT 24
Peak memory 201760 kb
Host smart-2256f272-a090-429f-9dd2-d8d84cdfda9c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662241756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_
wakeup.2662241756
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.4025964344
Short name T486
Test name
Test status
Simulation time 188892032330 ps
CPU time 404.63 seconds
Started Jul 19 07:08:22 PM PDT 24
Finished Jul 19 07:15:08 PM PDT 24
Peak memory 201724 kb
Host smart-6be86e59-b628-4029-bf52-0589b04786b7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025964344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
adc_ctrl_filters_wakeup_fixed.4025964344
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.4108018917
Short name T555
Test name
Test status
Simulation time 113626530879 ps
CPU time 405.55 seconds
Started Jul 19 07:08:24 PM PDT 24
Finished Jul 19 07:15:10 PM PDT 24
Peak memory 202172 kb
Host smart-a7c706f6-36f7-47ae-bf2e-3c6ea97063fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108018917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.4108018917
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.2162766343
Short name T488
Test name
Test status
Simulation time 35962802842 ps
CPU time 44.32 seconds
Started Jul 19 07:08:27 PM PDT 24
Finished Jul 19 07:09:12 PM PDT 24
Peak memory 201592 kb
Host smart-f6c8b664-b394-4bcd-af1b-0cf45d60579e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162766343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.2162766343
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.113192090
Short name T483
Test name
Test status
Simulation time 2702756801 ps
CPU time 4.18 seconds
Started Jul 19 07:08:17 PM PDT 24
Finished Jul 19 07:08:22 PM PDT 24
Peak memory 201688 kb
Host smart-6e4a5939-ccaa-4b1b-8775-833a73776c06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113192090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.113192090
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.1680014368
Short name T84
Test name
Test status
Simulation time 6006224209 ps
CPU time 7.97 seconds
Started Jul 19 07:08:09 PM PDT 24
Finished Jul 19 07:08:19 PM PDT 24
Peak memory 201600 kb
Host smart-68989dea-1830-493a-b100-c54d4cb66d4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680014368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.1680014368
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.2323216831
Short name T694
Test name
Test status
Simulation time 281491446620 ps
CPU time 346.43 seconds
Started Jul 19 07:08:24 PM PDT 24
Finished Jul 19 07:14:12 PM PDT 24
Peak memory 212412 kb
Host smart-9b13edc5-0e5d-4dd8-97cd-91bf23f01140
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323216831 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.
2323216831
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.680849688
Short name T16
Test name
Test status
Simulation time 70143489941 ps
CPU time 67.08 seconds
Started Jul 19 07:08:28 PM PDT 24
Finished Jul 19 07:09:36 PM PDT 24
Peak memory 210660 kb
Host smart-9fe52d8e-d000-4f51-b69e-99ebcb915c44
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680849688 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.680849688
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.985982280
Short name T626
Test name
Test status
Simulation time 318066344 ps
CPU time 0.77 seconds
Started Jul 19 07:08:46 PM PDT 24
Finished Jul 19 07:08:51 PM PDT 24
Peak memory 201552 kb
Host smart-6ce020aa-f756-49e8-8bc9-a5307c574213
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985982280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.985982280
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.1386633718
Short name T529
Test name
Test status
Simulation time 173417180852 ps
CPU time 98.48 seconds
Started Jul 19 07:08:38 PM PDT 24
Finished Jul 19 07:10:19 PM PDT 24
Peak memory 201808 kb
Host smart-f9352475-6905-481d-90db-c44b103b28de
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386633718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gati
ng.1386633718
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.1520741686
Short name T277
Test name
Test status
Simulation time 334268502283 ps
CPU time 785.71 seconds
Started Jul 19 07:08:28 PM PDT 24
Finished Jul 19 07:21:35 PM PDT 24
Peak memory 201752 kb
Host smart-47c25618-4d52-4574-ac99-b2864eb5a34d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520741686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.1520741686
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.2519819151
Short name T585
Test name
Test status
Simulation time 163770912264 ps
CPU time 377.33 seconds
Started Jul 19 07:08:28 PM PDT 24
Finished Jul 19 07:14:46 PM PDT 24
Peak memory 201728 kb
Host smart-d907f523-1a6b-46aa-b07b-472110c97cab
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519819151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrup
t_fixed.2519819151
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.1589356476
Short name T681
Test name
Test status
Simulation time 332821975099 ps
CPU time 397.61 seconds
Started Jul 19 07:08:34 PM PDT 24
Finished Jul 19 07:15:12 PM PDT 24
Peak memory 201696 kb
Host smart-12a98f4b-11b9-4771-b72a-788d1a47c556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589356476 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.1589356476
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.946066104
Short name T70
Test name
Test status
Simulation time 497898805560 ps
CPU time 1119.02 seconds
Started Jul 19 07:08:27 PM PDT 24
Finished Jul 19 07:27:07 PM PDT 24
Peak memory 201708 kb
Host smart-fb07f206-24d7-424f-823b-1f5201e0136c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=946066104 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixed
.946066104
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.3611375563
Short name T118
Test name
Test status
Simulation time 511472363415 ps
CPU time 313.33 seconds
Started Jul 19 07:08:28 PM PDT 24
Finished Jul 19 07:13:42 PM PDT 24
Peak memory 201764 kb
Host smart-106ed088-5f2f-45c1-8927-50f53cee2eef
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611375563 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_
wakeup.3611375563
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.3106061581
Short name T553
Test name
Test status
Simulation time 584659672398 ps
CPU time 752.99 seconds
Started Jul 19 07:08:38 PM PDT 24
Finished Jul 19 07:21:13 PM PDT 24
Peak memory 201736 kb
Host smart-df64e414-8ed9-453d-ad59-f42f80f6fac8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106061581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
adc_ctrl_filters_wakeup_fixed.3106061581
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.3024854821
Short name T38
Test name
Test status
Simulation time 128427528609 ps
CPU time 708.51 seconds
Started Jul 19 07:08:44 PM PDT 24
Finished Jul 19 07:20:37 PM PDT 24
Peak memory 202160 kb
Host smart-c423d49e-e98a-4bd1-baa8-e37719712892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024854821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.3024854821
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.4018511884
Short name T671
Test name
Test status
Simulation time 33805995873 ps
CPU time 16.43 seconds
Started Jul 19 07:08:33 PM PDT 24
Finished Jul 19 07:08:51 PM PDT 24
Peak memory 201624 kb
Host smart-6ea5e11a-7708-4ac3-a11d-666753d7d4cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018511884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.4018511884
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.774130384
Short name T750
Test name
Test status
Simulation time 5006207236 ps
CPU time 12.85 seconds
Started Jul 19 07:08:37 PM PDT 24
Finished Jul 19 07:08:51 PM PDT 24
Peak memory 201620 kb
Host smart-60fa72a5-4c49-46e8-a3ca-6be214bbc7f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774130384 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.774130384
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.3771573142
Short name T477
Test name
Test status
Simulation time 5670296241 ps
CPU time 14.93 seconds
Started Jul 19 07:08:28 PM PDT 24
Finished Jul 19 07:08:45 PM PDT 24
Peak memory 201596 kb
Host smart-d423df5b-1a38-4781-9493-debc61b044f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771573142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.3771573142
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.871106855
Short name T276
Test name
Test status
Simulation time 457734092200 ps
CPU time 572.12 seconds
Started Jul 19 07:08:44 PM PDT 24
Finished Jul 19 07:18:21 PM PDT 24
Peak memory 202176 kb
Host smart-5510d49c-b356-4d35-842d-907b9eec25ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871106855 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.871106855
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.1395867435
Short name T22
Test name
Test status
Simulation time 162582292012 ps
CPU time 497.26 seconds
Started Jul 19 07:08:46 PM PDT 24
Finished Jul 19 07:17:08 PM PDT 24
Peak memory 210380 kb
Host smart-a6b0321d-2a1d-4522-9842-799c219d5f77
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395867435 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.1395867435
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.435565085
Short name T786
Test name
Test status
Simulation time 332386815 ps
CPU time 0.73 seconds
Started Jul 19 07:09:04 PM PDT 24
Finished Jul 19 07:09:15 PM PDT 24
Peak memory 201552 kb
Host smart-cb04e64e-2e74-4822-bdb2-ca2772c0c9df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435565085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.435565085
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.3722936833
Short name T621
Test name
Test status
Simulation time 211951931770 ps
CPU time 474.87 seconds
Started Jul 19 07:08:55 PM PDT 24
Finished Jul 19 07:16:52 PM PDT 24
Peak memory 201772 kb
Host smart-990fed94-b5aa-457e-a28b-6089433a2892
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722936833 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gati
ng.3722936833
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.3529363261
Short name T241
Test name
Test status
Simulation time 187413232774 ps
CPU time 431.11 seconds
Started Jul 19 07:08:56 PM PDT 24
Finished Jul 19 07:16:11 PM PDT 24
Peak memory 201764 kb
Host smart-81ad90df-a7b5-43c1-aed3-3306be4ac0db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529363261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.3529363261
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.698126759
Short name T489
Test name
Test status
Simulation time 332029083742 ps
CPU time 224.21 seconds
Started Jul 19 07:08:45 PM PDT 24
Finished Jul 19 07:12:33 PM PDT 24
Peak memory 201728 kb
Host smart-d4b47170-0d8e-46a9-b62f-a197e5aff3c1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=698126759 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt
_fixed.698126759
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.2272768467
Short name T5
Test name
Test status
Simulation time 322792642361 ps
CPU time 775.05 seconds
Started Jul 19 07:08:46 PM PDT 24
Finished Jul 19 07:21:45 PM PDT 24
Peak memory 201712 kb
Host smart-97727558-e1f6-4c9d-a32a-7b4322d5e05d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272768467 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.2272768467
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.2172691945
Short name T95
Test name
Test status
Simulation time 492070958563 ps
CPU time 317.64 seconds
Started Jul 19 07:09:31 PM PDT 24
Finished Jul 19 07:15:01 PM PDT 24
Peak memory 201748 kb
Host smart-4dcd9020-1ae9-498b-af35-49231ca6ffb0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172691945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixe
d.2172691945
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.805905964
Short name T469
Test name
Test status
Simulation time 171473872401 ps
CPU time 382.18 seconds
Started Jul 19 07:09:16 PM PDT 24
Finished Jul 19 07:15:54 PM PDT 24
Peak memory 201820 kb
Host smart-fe5ce8d9-1d50-4a3a-b514-fea15afd1e50
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805905964 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_w
akeup.805905964
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.253581484
Short name T75
Test name
Test status
Simulation time 202582959802 ps
CPU time 440.62 seconds
Started Jul 19 07:08:55 PM PDT 24
Finished Jul 19 07:16:19 PM PDT 24
Peak memory 201724 kb
Host smart-869f31c4-e9cc-4d98-af3d-d0aa9b8e1a74
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253581484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.a
dc_ctrl_filters_wakeup_fixed.253581484
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.1111497958
Short name T581
Test name
Test status
Simulation time 84042477927 ps
CPU time 474.71 seconds
Started Jul 19 07:09:09 PM PDT 24
Finished Jul 19 07:17:16 PM PDT 24
Peak memory 202108 kb
Host smart-664e6d8c-bd25-4ca7-a995-9ee334c4d7fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111497958 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.1111497958
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.380215376
Short name T332
Test name
Test status
Simulation time 35909586057 ps
CPU time 84.97 seconds
Started Jul 19 07:08:52 PM PDT 24
Finished Jul 19 07:10:19 PM PDT 24
Peak memory 201748 kb
Host smart-70ed95a2-feff-4ab9-b908-61da53cde7eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380215376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.380215376
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.1594540148
Short name T116
Test name
Test status
Simulation time 4614002382 ps
CPU time 2.1 seconds
Started Jul 19 07:08:55 PM PDT 24
Finished Jul 19 07:09:00 PM PDT 24
Peak memory 201596 kb
Host smart-360fd8fe-4c1c-4048-b5b5-5afa2ae4c3ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594540148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.1594540148
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.1956354433
Short name T677
Test name
Test status
Simulation time 5931394309 ps
CPU time 6.96 seconds
Started Jul 19 07:08:43 PM PDT 24
Finished Jul 19 07:08:54 PM PDT 24
Peak memory 201624 kb
Host smart-b24f1602-1373-48a2-a0ef-f94e88dbbe59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956354433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.1956354433
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.2678366728
Short name T510
Test name
Test status
Simulation time 334087469768 ps
CPU time 811.23 seconds
Started Jul 19 07:09:04 PM PDT 24
Finished Jul 19 07:22:43 PM PDT 24
Peak memory 201816 kb
Host smart-378a70b4-6ea8-49e9-a167-cf620d5cbb63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678366728 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.
2678366728
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.2632956243
Short name T343
Test name
Test status
Simulation time 435709935 ps
CPU time 1.18 seconds
Started Jul 19 07:09:36 PM PDT 24
Finished Jul 19 07:09:47 PM PDT 24
Peak memory 201568 kb
Host smart-21b92fe6-4ed9-495a-8b98-40c74a53286a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632956243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.2632956243
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.1919091349
Short name T763
Test name
Test status
Simulation time 311511068735 ps
CPU time 36.8 seconds
Started Jul 19 07:09:14 PM PDT 24
Finished Jul 19 07:10:04 PM PDT 24
Peak memory 201724 kb
Host smart-6069f46c-2a13-4090-8856-6cf53fee6cc2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919091349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gati
ng.1919091349
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.1603559159
Short name T2
Test name
Test status
Simulation time 166771275499 ps
CPU time 416.01 seconds
Started Jul 19 07:09:15 PM PDT 24
Finished Jul 19 07:16:26 PM PDT 24
Peak memory 201744 kb
Host smart-0225df77-f464-45b8-be7a-d726a1f7aa0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603559159 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.1603559159
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.1403920481
Short name T782
Test name
Test status
Simulation time 167394617398 ps
CPU time 380.97 seconds
Started Jul 19 07:09:13 PM PDT 24
Finished Jul 19 07:15:47 PM PDT 24
Peak memory 201868 kb
Host smart-cea02db6-cdfd-4080-9caf-1481c942f583
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403920481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrup
t_fixed.1403920481
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.3990109048
Short name T676
Test name
Test status
Simulation time 492633071969 ps
CPU time 883.4 seconds
Started Jul 19 07:09:05 PM PDT 24
Finished Jul 19 07:23:58 PM PDT 24
Peak memory 201848 kb
Host smart-c5970d82-dce0-4283-b9ff-51328bbf4322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990109048 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.3990109048
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.747758648
Short name T349
Test name
Test status
Simulation time 163465332794 ps
CPU time 182.57 seconds
Started Jul 19 07:09:14 PM PDT 24
Finished Jul 19 07:12:30 PM PDT 24
Peak memory 201788 kb
Host smart-34dba023-eb4f-44af-9ddd-8e901764d113
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=747758648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixed
.747758648
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.2407095386
Short name T324
Test name
Test status
Simulation time 371907804734 ps
CPU time 165.48 seconds
Started Jul 19 07:09:15 PM PDT 24
Finished Jul 19 07:12:16 PM PDT 24
Peak memory 201752 kb
Host smart-808abdb1-4bd8-4ccc-a3ca-1db112ce33d0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407095386 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_
wakeup.2407095386
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.2041383021
Short name T368
Test name
Test status
Simulation time 613551602136 ps
CPU time 677.22 seconds
Started Jul 19 07:09:15 PM PDT 24
Finished Jul 19 07:20:48 PM PDT 24
Peak memory 201884 kb
Host smart-21720fa4-10cd-4b23-bce4-f6aa87fab439
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041383021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
adc_ctrl_filters_wakeup_fixed.2041383021
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.4269337008
Short name T710
Test name
Test status
Simulation time 85289143162 ps
CPU time 486.41 seconds
Started Jul 19 07:09:23 PM PDT 24
Finished Jul 19 07:17:44 PM PDT 24
Peak memory 202120 kb
Host smart-b63888d9-4396-4535-9f14-19c9ad7c0e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269337008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.4269337008
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.3358318523
Short name T480
Test name
Test status
Simulation time 43322178758 ps
CPU time 24.79 seconds
Started Jul 19 07:09:22 PM PDT 24
Finished Jul 19 07:10:02 PM PDT 24
Peak memory 201592 kb
Host smart-8c73b9cb-0c84-4073-be6e-bc4627ff66c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358318523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.3358318523
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.4212635791
Short name T457
Test name
Test status
Simulation time 4816496761 ps
CPU time 3.78 seconds
Started Jul 19 07:09:14 PM PDT 24
Finished Jul 19 07:09:32 PM PDT 24
Peak memory 201600 kb
Host smart-2ef9280f-90fc-4c7c-a845-2a5d4052bf76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212635791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.4212635791
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.758837514
Short name T4
Test name
Test status
Simulation time 5606108173 ps
CPU time 9.72 seconds
Started Jul 19 07:09:06 PM PDT 24
Finished Jul 19 07:09:25 PM PDT 24
Peak memory 201600 kb
Host smart-c8f89502-1919-49fd-823a-91ab43cf5ce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758837514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.758837514
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.2364138227
Short name T602
Test name
Test status
Simulation time 390546541573 ps
CPU time 227.94 seconds
Started Jul 19 07:09:21 PM PDT 24
Finished Jul 19 07:13:25 PM PDT 24
Peak memory 201744 kb
Host smart-0d47c4f1-a023-4891-bc72-87c11f6fcaf2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364138227 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.
2364138227
Directory /workspace/9.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.3227360098
Short name T712
Test name
Test status
Simulation time 100942576374 ps
CPU time 119.51 seconds
Started Jul 19 07:09:23 PM PDT 24
Finished Jul 19 07:11:37 PM PDT 24
Peak memory 218336 kb
Host smart-82fc1769-dafd-416d-a9eb-7cb7dd0b1738
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227360098 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.3227360098
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest
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