Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	7090	1			T1	62		T3	50		T8	42
testmodes[AdcCtrlTestmodeNormal]	5482	1			T1	51		T2	1		T3	24
testmodes[AdcCtrlTestmodeLowpower]	5914	1			T1	35		T3	34		T4	2
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	3838	1			T1	26		T3	35		T8	14
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1712	1			T1	21		T3	10		T8	12
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1405	1			T1	14		T3	5		T8	16
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1728	1			T1	24		T3	13		T8	11
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	2058	1			T1	16		T3	5		T5	2
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1372	1			T1	11		T3	5		T7	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1408	1			T1	12		T3	2		T8	17
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1370	1			T1	13		T3	9		T8	13
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2896	1			T1	10		T3	23		T4	1