Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26780

1

T1

150

T2

11

T3

123

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22793

1

T1

150

T2

11

T3

123

auto[ADC_CTRL_FILTER_COND_OUT]

3987

1

T5

1

T6

13

T7

11

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20875

1

T1

150

T3

118

T5

1

auto[1]

5905

1

T2

11

T3

5

T4

26

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22677

1

T1

148

T2

1

T3

114

auto[1]

4103

1

T1

2

T2

10

T3

9

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	5	1			T77	5		-	-		-	-
values[0]	74	1			T179	1		T180	34		T181	15
values[1]	635	1			T3	11		T90	25		T93	10
values[2]	811	1			T3	3		T11	23		T12	15
values[3]	494	1			T26	24		T76	1		T182	4
values[4]	815	1			T5	1		T7	32		T9	38
values[5]	878	1			T76	1		T34	18		T131	10
values[6]	577	1			T5	1		T11	23		T34	11
values[7]	842	1			T11	14		T157	11		T27	4
values[8]	662	1			T6	13		T12	2		T26	21
values[9]	3463	1			T2	11		T3	5		T4	26
minimum	17524	1			T1	150		T3	104		T8	133

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	866	1			T3	14		T12	15		T183	7
values[1]	730	1			T11	23		T90	49		T13	1
values[2]	663	1			T7	32		T26	24		T76	1
values[3]	599	1			T5	1		T9	38		T124	33
values[4]	1068	1			T11	23		T76	1		T34	18
values[5]	700	1			T5	1		T34	11		T123	13
values[6]	2945	1			T2	11		T4	26		T11	14
values[7]	596	1			T3	5		T12	2		T183	3
values[8]	923	1			T5	1		T6	13		T7	12
values[9]	158	1			T95	11		T136	17		T32	2
minimum	17532	1			T1	150		T3	104		T8	133

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22589

1

T1

150

T2

11

T3

117

auto[1]

4191

1

T3

6

T4

24

T6

12

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T3	9		T183	7		T89	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T12	10		T13	15		T184	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T11	13		T13	1		T182	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T90	24		T129	11		T136	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T7	10		T26	13		T76	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T7	11		T128	6		T93	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T5	1		T9	19		T124	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T133	16		T185	5		T186	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T34	5		T131	10		T22	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	381	1			T11	12		T76	1		T123	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T34	9		T123	13		T187	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T5	1		T188	4		T32	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1538	1			T2	1		T4	26		T35	29
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	302	1			T11	12		T26	11		T123	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T3	4		T12	1		T95	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T183	3		T45	11		T27	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T5	1		T7	3		T33	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	341	1			T6	13		T25	1		T45	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T136	8		T32	2		T189	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T95	1		T190	1		T191	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17409	1			T1	148		T3	101		T8	133
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T3	5		T89	10		T93	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T12	5		T13	8		T184	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T11	10		T182	3		T184	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T90	25		T136	14		T32	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T7	11		T26	11		T186	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T128	8		T93	11		T30	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T9	19		T124	18		T95	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T133	4		T185	9		T186	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T34	13		T22	9		T89	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T11	11		T184	9		T140	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T34	2		T187	11		T134	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T188	3		T32	1		T192	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	907	1			T2	10		T193	12		T153	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T11	2		T26	10		T157	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T3	1		T12	1		T95	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T45	3		T194	20		T14	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T7	9		T33	1		T195	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T45	7		T182	16		T132	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T136	9		T77	2		T196	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T95	10		T191	6		T197	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T1	2		T3	3		T27	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T77	3		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T198	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T179	1		T180	14		T181	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T3	7		T93	2		T13	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T90	13		T13	15		T184	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T3	2		T11	13		T183	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T12	10		T90	11		T129	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T26	13		T76	1		T182	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T199	1		T200	1		T201	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T5	1		T7	10		T9	19
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T7	11		T128	6		T93	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T34	5		T131	10		T22	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T76	1		T202	10		T140	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T34	9		T123	13		T187	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T5	1		T11	12		T123	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T203	10		T127	1		T134	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T11	12		T157	5		T27	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T12	1		T95	1		T125	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T6	13		T26	11		T123	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1673	1			T2	1		T3	4		T4	26
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	384	1			T25	1		T45	9		T95	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17408	1			T1	148		T3	101		T8	133
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T77	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T180	20		T181	14		T204	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T3	4		T93	8		T13	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T90	12		T13	8		T184	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T3	1		T11	10		T89	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T12	5		T90	13		T136	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T26	11		T182	3		T125	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T200	6		T205	10		T206	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T7	11		T9	19		T124	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T128	8		T93	11		T133	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T34	13		T22	9		T89	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T140	8		T134	19		T122	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T34	2		T187	11		T30	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T11	11		T184	9		T188	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T203	8		T134	8		T186	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T11	2		T157	6		T89	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T12	1		T95	15		T125	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T26	10		T45	3		T28	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1071	1			T2	10		T3	1		T7	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	335	1			T45	7		T95	10		T182	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T1	2		T3	3		T27	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T3	9		T183	1		T89	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T12	11		T13	11		T184	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T11	11		T13	1		T182	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T90	27		T129	1		T136	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T7	12		T26	12		T76	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T7	1		T128	9		T93	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T5	1		T9	20		T124	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T133	5		T185	10		T186	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T34	14		T131	1		T22	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T11	12		T76	1		T123	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T34	3		T123	1		T187	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T5	1		T188	4		T32	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1237	1			T2	11		T4	2		T35	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T11	3		T26	11		T123	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T3	4		T12	2		T95	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T183	1		T45	4		T27	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T5	1		T7	10		T33	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	332	1			T6	1		T25	1		T45	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T136	10		T32	2		T189	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T95	11		T190	1		T191	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17532	1			T1	150		T3	104		T8	133
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T3	5		T183	6		T89	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T12	4		T13	12		T184	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T11	12		T184	8		T207	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T90	22		T129	10		T136	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T7	9		T26	12		T208	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T7	10		T128	5		T30	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T9	18		T124	14		T202	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T133	15		T185	4		T209	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T34	4		T131	9		T22	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	324	1			T11	11		T123	10		T202	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T34	8		T123	12		T187	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T188	3		T32	1		T210	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1208	1			T4	24		T35	26		T163	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T11	11		T26	10		T123	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T3	1		T211	11		T149	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T183	2		T45	10		T27	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T7	2		T33	2		T208	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T6	12		T45	8		T182	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T136	7		T77	2		T212	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T191	6		T197	8		T213	3

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T77	3		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T198	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T179	1		T180	21		T181	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T3	6		T93	10		T13	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T90	13		T13	11		T184	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T3	3		T11	11		T183	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T12	11		T90	14		T129	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T26	12		T76	1		T182	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T199	1		T200	7		T201	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T5	1		T7	12		T9	20
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T7	1		T128	9		T93	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T34	14		T131	1		T22	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T76	1		T202	1		T140	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T34	3		T123	1		T187	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T5	1		T11	12		T123	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T203	9		T127	1		T134	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	323	1			T11	3		T157	7		T27	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T12	2		T95	16		T125	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T6	1		T26	11		T123	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1454	1			T2	11		T3	4		T4	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	403	1			T25	1		T45	8		T95	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17524	1			T1	150		T3	104		T8	133
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T77	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T180	13		T204	9		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T3	5		T13	7		T24	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T90	12		T13	12		T184	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T11	12		T183	6		T89	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T12	4		T90	10		T129	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T26	12		T207	12		T208	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T205	8		T214	6		T206	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T7	9		T9	18		T124	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T7	10		T128	5		T133	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T34	4		T131	9		T22	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T202	9		T140	7		T134	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T34	8		T123	12		T187	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T11	11		T123	10		T184	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T203	9		T134	3		T215	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T11	11		T157	4		T27	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T210	8		T16	1		T211	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T6	12		T26	10		T123	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1290	1			T3	1		T4	24		T7	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	316	1			T45	8		T182	15		T82	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22589

1

T1

150

T2

11

T3

117

auto[1]

auto[0]

4191

1

T3

6

T4

24

T6

12

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26780

1

T1

150

T2

11

T3

123

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23078

1

T1

150

T2

11

T3

123

auto[ADC_CTRL_FILTER_COND_OUT]

3702

1

T5

3

T9

38

T11

23

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20729

1

T1

150

T3

120

T5

2

auto[1]

6051

1

T2

11

T3

3

T4

26

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22677

1

T1

148

T2

1

T3

114

auto[1]

4103

1

T1

2

T2

10

T3

9

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	28	1			T216	12		T217	15		T198	1
values[0]	14	1			T137	1		T218	13		-	-
values[1]	581	1			T3	3		T7	12		T12	15
values[2]	500	1			T7	21		T183	7		T13	19
values[3]	703	1			T3	11		T5	1		T34	18
values[4]	1066	1			T6	13		T9	38		T11	14
values[5]	3019	1			T2	11		T4	26		T5	1
values[6]	570	1			T3	5		T11	23		T34	11
values[7]	720	1			T5	1		T25	1		T26	24
values[8]	825	1			T26	21		T123	13		T45	30
values[9]	1230	1			T7	11		T11	23		T123	8
minimum	17524	1			T1	150		T3	104		T8	133

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	843	1			T3	3		T7	33		T12	15
values[1]	454	1			T3	11		T90	25		T135	1
values[2]	782	1			T5	1		T9	38		T11	14
values[3]	3299	1			T2	11		T4	26		T5	1
values[4]	572	1			T3	5		T34	11		T13	1
values[5]	641	1			T5	1		T11	23		T128	14
values[6]	789	1			T25	1		T123	24		T45	16
values[7]	777	1			T7	11		T26	45		T131	10
values[8]	843	1			T11	23		T89	44		T93	2
values[9]	256	1			T123	8		T187	23		T32	6
minimum	17524	1			T1	150		T3	104		T8	133

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22589

1

T1

150

T2

11

T3

117

auto[1]

4191

1

T3

6

T4

24

T6

12

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T3	2		T7	13		T12	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T183	7		T82	3		T219	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T3	7		T90	13		T29	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T135	1		T129	14		T220	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T11	12		T182	1		T140	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T5	1		T9	19		T76	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1677	1			T2	1		T4	26		T6	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	315	1			T5	1		T12	1		T207	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T3	4		T34	9		T13	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T132	1		T125	1		T136	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T11	12		T128	6		T95	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T5	1		T13	6		T195	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T123	13		T95	1		T202	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T25	1		T123	11		T45	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T7	11		T26	11		T131	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T26	13		T22	5		T45	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T89	3		T93	1		T95	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T11	13		T89	23		T125	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T123	8		T221	1		T222	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T187	12		T32	2		T223	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17408	1			T1	148		T3	101		T8	133
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T3	1		T7	20		T12	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T224	7		T148	25		T225	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T3	4		T90	12		T29	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T82	15		T141	11		T195	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T11	2		T182	3		T140	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T9	19		T34	13		T93	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1087	1			T2	10		T193	12		T153	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T12	1		T134	19		T185	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T3	1		T34	2		T182	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T132	12		T125	17		T136	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T11	11		T128	8		T95	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T195	2		T77	2		T226	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T95	10		T125	6		T215	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T45	7		T184	13		T186	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T26	10		T30	1		T133	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T26	11		T22	9		T45	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T89	2		T93	1		T95	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T11	10		T89	16		T125	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T222	10		T197	7		T227	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T187	11		T32	4		T228	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T1	2		T3	3		T27	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T216	1		T198	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T217	15		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T137	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T218	7		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T3	2		T7	3		T12	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T219	1		T229	1		T224	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T7	10		T13	11		T184	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T183	7		T135	1		T129	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T3	7		T90	13		T140	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T5	1		T34	5		T188	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T6	13		T11	12		T124	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	331	1			T9	19		T12	1		T76	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1569	1			T2	1		T4	26		T35	29
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T5	1		T13	4		T194	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T3	4		T11	12		T34	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T125	1		T136	8		T127	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T128	6		T95	2		T202	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T5	1		T25	1		T26	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T26	11		T123	13		T27	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T45	20		T89	11		T13	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	322	1			T7	11		T123	8		T131	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	386	1			T11	13		T22	5		T89	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17408	1			T1	148		T3	101		T8	133
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T216	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T218	6		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T3	1		T7	9		T12	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T224	7		T148	12		T230	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T7	11		T13	8		T184	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T82	15		T148	13		T225	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T3	4		T90	12		T140	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T34	13		T188	3		T30	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T11	2		T124	18		T90	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T9	19		T12	1		T93	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1001	1			T2	10		T193	12		T153	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T194	20		T31	6		T185	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T3	1		T11	11		T34	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T125	17		T136	9		T24	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T128	8		T95	25		T125	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T26	11		T186	9		T195	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T26	10		T215	12		T174	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T45	10		T89	6		T184	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T89	2		T93	1		T95	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T11	10		T22	9		T89	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T1	2		T3	3		T27	1