Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26780

1

T1

150

T2

11

T3

123

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23363

1

T1

150

T2

11

T3

120

auto[ADC_CTRL_FILTER_COND_OUT]

3417

1

T3

3

T5

3

T6

13

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20717

1

T1

150

T3

109

T5

2

auto[1]

6063

1

T2

11

T3

14

T4

26

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22677

1

T1

148

T2

1

T3

114

auto[1]

4103

1

T1

2

T2

10

T3

9

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	8	1			T188	7		T297	1		-	-
values[0]	70	1			T136	27		T207	13		T298	7
values[1]	881	1			T11	14		T124	33		T95	3
values[2]	523	1			T3	5		T5	1		T183	7
values[3]	634	1			T3	11		T9	38		T12	2
values[4]	755	1			T5	1		T6	13		T7	12
values[5]	688	1			T7	21		T131	10		T157	11
values[6]	880	1			T11	23		T123	11		T27	4
values[7]	664	1			T76	1		T123	8		T13	23
values[8]	2885	1			T2	11		T3	3		T4	26
values[9]	1268	1			T5	1		T7	11		T26	24
minimum	17524	1			T1	150		T3	104		T8	133

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1047	1			T3	5		T11	14		T124	33
values[1]	561	1			T5	1		T183	7		T45	14
values[2]	772	1			T3	11		T5	1		T9	38
values[3]	479	1			T25	1		T76	1		T34	11
values[4]	964	1			T6	13		T7	33		T11	23
values[5]	700	1			T27	4		T95	16		T202	11
values[6]	2929	1			T2	11		T3	3		T4	26
values[7]	683	1			T11	23		T123	13		T128	14
values[8]	915	1			T5	1		T26	24		T89	17
values[9]	189	1			T7	11		T188	7		T140	1
minimum	17541	1			T1	150		T3	104		T8	133

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22589

1

T1

150

T2

11

T3

117

auto[1]

4191

1

T3

6

T4

24

T6

12

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T3	4		T124	15		T221	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	325	1			T11	12		T95	1		T187	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T202	10		T125	1		T32	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T5	1		T183	7		T45	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T3	7		T9	19		T12	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T5	1		T12	10		T95	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T25	1		T34	9		T22	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T76	1		T157	5		T138	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T7	3		T123	11		T131	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T6	13		T7	10		T11	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T27	4		T32	2		T82	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T95	1		T202	11		T13	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1660	1			T2	1		T4	26		T26	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T3	2		T183	3		T220	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T45	9		T93	1		T184	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T11	12		T123	13		T128	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T26	13		T89	11		T13	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T5	1		T90	13		T13	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T188	4		T140	1		T122	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T7	11		T138	1		T209	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17409	1			T1	148		T3	101		T8	133
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T129	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T3	1		T124	18		T237	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T11	2		T95	2		T187	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T125	6		T32	1		T205	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T45	3		T89	2		T13	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T3	4		T9	19		T12	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T12	5		T95	10		T203	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T34	2		T22	9		T29	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T157	6		T138	8		T161	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T7	9		T90	13		T184	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T7	11		T11	10		T93	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T134	8		T185	9		T186	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T95	15		T13	8		T182	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	995	1			T2	10		T26	10		T193	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T3	1		T14	2		T141	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T45	7		T93	1		T184	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T11	11		T128	8		T93	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T26	11		T89	6		T194	20
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T90	12		T184	16		T134	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T188	3		T122	1		T141	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T209	9		T222	7		T278	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T1	2		T3	3		T27	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T188	4		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T297	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T298	3		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T136	13		T207	13		T292	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T124	15		T186	1		T199	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T11	12		T95	1		T187	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T3	4		T202	10		T125	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T5	1		T183	7		T45	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T3	7		T9	19		T12	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T13	8		T125	1		T135	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T7	3		T25	1		T34	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T5	1		T6	13		T12	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T131	10		T22	5		T132	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T7	10		T157	5		T93	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T123	11		T27	4		T90	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T11	13		T95	1		T202	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T76	1		T123	8		T13	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T13	11		T220	1		T14	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1592	1			T2	1		T4	26		T26	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T3	2		T11	12		T183	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	389	1			T26	13		T45	9		T89	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T5	1		T7	11		T123	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17408	1			T1	148		T3	101		T8	133
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T188	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T298	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T136	14		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T124	18		T186	5		T143	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T11	2		T95	2		T187	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T3	1		T125	6		T32	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T45	3		T89	2		T136	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T3	4		T9	19		T12	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T13	6		T125	4		T203	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T7	9		T34	2		T184	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T12	5		T95	10		T138	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T22	9		T132	12		T140	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T7	11		T157	6		T93	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T90	13		T30	7		T185	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T11	10		T95	15		T182	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T182	3		T134	8		T235	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T13	8		T14	2		T141	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1019	1			T2	10		T26	10		T193	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T3	1		T11	11		T122	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T26	11		T45	7		T89	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	315	1			T128	8		T90	12		T93	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T1	2		T3	3		T27	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	308	1			T3	4		T124	19		T221	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T11	3		T95	3		T187	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T202	1		T125	7		T32	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T5	1		T183	1		T45	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T3	6		T9	20		T12	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T5	1		T12	11		T95	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T25	1		T34	3		T22	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T76	1		T157	7		T138	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T7	10		T123	1		T131	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T6	1		T7	12		T11	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T27	3		T32	2		T82	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T95	16		T202	1		T13	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1347	1			T2	11		T4	2		T26	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T3	3		T183	1		T220	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T45	8		T93	2		T184	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T11	12		T123	1		T128	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T26	12		T89	7		T13	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T5	1		T90	13		T13	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T188	4		T140	1		T122	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T7	1		T138	1		T209	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17530	1			T1	150		T3	104		T8	133
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T129	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T3	1		T124	14		T270	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T11	11		T187	11		T136	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T202	9		T32	1		T205	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T183	6		T45	10		T89	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T3	5		T9	18		T34	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T12	4		T203	9		T264	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T34	8		T22	4		T29	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T157	4		T232	8		T267	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T7	2		T123	10		T131	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T6	12		T7	9		T11	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T27	1		T82	2		T134	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T202	10		T13	9		T182	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1308	1			T4	24		T26	10		T35	26
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T183	2		T14	1		T210	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T45	8		T184	13		T129	19
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T11	11		T123	12		T128	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T26	12		T89	10		T194	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T90	12		T184	15		T32	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T188	3		T122	1		T253	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T7	10		T209	11		T222	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T129	10		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T188	4		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T297	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T298	5		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T136	15		T207	1		T292	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T124	19		T186	6		T199	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T11	3		T95	3		T187	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T3	4		T202	1		T125	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T5	1		T183	1		T45	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T3	6		T9	20		T12	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T13	7		T125	5		T135	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T7	10		T25	1		T34	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T5	1		T6	1		T12	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T131	1		T22	10		T132	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T7	12		T157	7		T93	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T123	1		T27	3		T90	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T11	11		T95	16		T202	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T76	1		T123	1		T13	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T13	10		T220	1		T14	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1356	1			T2	11		T4	2		T26	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T3	3		T11	12		T183	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	327	1			T26	12		T45	8		T89	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	374	1			T5	1		T7	1		T123	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17524	1			T1	150		T3	104		T8	133
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T188	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T298	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T136	12		T207	12		T292	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T124	14		T270	9		T143	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T11	11		T187	11		T129	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T3	1		T202	9		T32	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T183	6		T45	10		T89	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T3	5		T9	18		T34	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T13	7		T203	9		T192	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T7	2		T34	8		T184	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T6	12		T12	4		T232	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T131	9		T22	4		T140	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T7	9		T157	4		T28	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T123	10		T27	1		T90	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T11	12		T202	10		T182	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T123	7		T13	3		T134	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T13	9		T14	1		T210	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1255	1			T4	24		T26	10		T35	26
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T11	11		T183	2		T122	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	314	1			T26	12		T45	8		T89	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T7	10		T123	12		T128	5

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22589

1

T1

150

T2

11

T3

117

auto[1]

auto[0]

4191

1

T3

6

T4

24

T6

12