Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26780

1

T1

150

T2

11

T3

123

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23036

1

T1

150

T2

11

T3

123

auto[ADC_CTRL_FILTER_COND_OUT]

3744

1

T5

2

T6

13

T7

21

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20708

1

T1

150

T3

109

T5

1

auto[1]

6072

1

T2

11

T3

14

T4

26

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22677

1

T1

148

T2

1

T3

114

auto[1]

4103

1

T1

2

T2

10

T3

9

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	73	1			T90	25		T207	13		T209	21
values[0]	56	1			T299	7		T257	18		T300	30
values[1]	759	1			T7	21		T26	21		T93	8
values[2]	927	1			T5	2		T11	23		T12	2
values[3]	689	1			T7	11		T9	38		T11	23
values[4]	2898	1			T2	11		T4	26		T5	1
values[5]	725	1			T123	13		T183	3		T22	14
values[6]	691	1			T3	3		T131	10		T89	17
values[7]	721	1			T11	14		T25	1		T76	1
values[8]	635	1			T3	5		T6	13		T12	15
values[9]	1082	1			T3	11		T7	12		T76	1
minimum	17524	1			T1	150		T3	104		T8	133

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	997	1			T5	2		T7	21		T26	21
values[1]	882	1			T11	46		T12	2		T34	18
values[2]	567	1			T7	11		T9	38		T26	24
values[3]	2989	1			T2	11		T4	26		T35	29
values[4]	711	1			T5	1		T183	7		T22	14
values[5]	691	1			T3	3		T25	1		T131	10
values[6]	631	1			T3	5		T11	14		T76	1
values[7]	784	1			T3	11		T6	13		T7	12
values[8]	742	1			T90	25		T93	12		T13	14
values[9]	185	1			T76	1		T187	23		T13	19
minimum	17601	1			T1	150		T3	104		T8	133

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22589

1

T1

150

T2

11

T3

117

auto[1]

4191

1

T3

6

T4

24

T6

12

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T5	1		T26	11		T157	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T5	1		T7	10		T182	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T12	1		T182	1		T125	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	306	1			T11	25		T34	5		T129	20
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T7	11		T9	19		T45	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T26	13		T123	8		T202	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1617	1			T2	1		T4	26		T35	29
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T89	12		T13	1		T203	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T89	11		T90	11		T95	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T5	1		T183	7		T22	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T3	2		T93	1		T202	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T25	1		T131	10		T184	23
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T3	4		T124	15		T13	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T11	12		T76	1		T128	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T3	7		T7	3		T12	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T6	13		T34	9		T215	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T90	13		T125	1		T31	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T93	1		T13	8		T159	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T76	1		T187	12		T132	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T13	11		T188	4		T271	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17421	1			T1	148		T3	101		T8	133
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T252	22		T167	7		T301	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T26	10		T157	6		T93	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T7	11		T182	16		T264	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T12	1		T182	3		T125	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T11	21		T34	13		T264	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T9	19		T45	7		T89	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T26	11		T122	1		T148	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1041	1			T2	10		T193	12		T153	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T89	10		T203	8		T32	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T89	6		T90	13		T95	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T22	9		T45	3		T125	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T3	1		T93	1		T235	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T184	22		T29	4		T33	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T3	1		T124	18		T30	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T11	2		T128	8		T136	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T3	4		T7	9		T12	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T34	2		T215	13		T174	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T90	12		T125	6		T31	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T93	11		T13	6		T122	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T187	11		T132	12		T18	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T13	8		T188	3		T288	19
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T1	2		T3	3		T27	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T252	14		T167	9		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T90	13		T302	9		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T207	13		T209	12		T289	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T299	4		T257	18		T300	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T26	11		T93	1		T95	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T7	10		T160	1		T32	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T5	1		T12	1		T157	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T5	1		T11	13		T182	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T7	11		T9	19		T45	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T11	12		T34	5		T123	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1604	1			T2	1		T4	26		T35	29
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T5	1		T26	13		T183	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T123	13		T183	3		T90	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T22	5		T45	11		T125	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T3	2		T89	11		T93	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T131	10		T136	13		T33	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T123	11		T124	15		T202	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T11	12		T25	1		T76	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T3	4		T12	10		T27	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T6	13		T34	9		T141	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T3	7		T7	3		T76	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	317	1			T93	1		T13	19		T188	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17408	1			T1	148		T3	101		T8	133
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T90	12		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T209	9		T289	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T299	3		T300	14		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T26	10		T93	7		T95	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T7	11		T264	7		T148	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T12	1		T157	6		T182	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T11	10		T182	16		T264	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T9	19		T45	7		T89	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T11	11		T34	13		T122	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1020	1			T2	10		T193	12		T153	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T26	11		T89	10		T203	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T90	13		T95	10		T134	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T22	9		T45	3		T125	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T3	1		T89	6		T93	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T136	14		T33	1		T185	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T124	18		T184	16		T30	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T11	2		T128	8		T184	22
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T3	1		T12	5		T32	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T34	2		T141	9		T215	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T3	4		T7	9		T187	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	315	1			T93	11		T13	14		T188	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T1	2		T3	3		T27	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	308	1			T5	1		T26	11		T157	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T5	1		T7	12		T182	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T12	2		T182	4		T125	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T11	23		T34	14		T129	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T7	1		T9	20		T45	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T26	12		T123	1		T202	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1395	1			T2	11		T4	2		T35	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T89	11		T13	1		T203	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T89	7		T90	14		T95	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T5	1		T183	1		T22	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T3	3		T93	2		T202	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T25	1		T131	1		T184	24
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T3	4		T124	19		T13	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T11	3		T76	1		T128	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T3	6		T7	10		T12	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T6	1		T34	3		T215	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T90	13		T125	7		T31	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T93	12		T13	7		T159	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T76	1		T187	12		T132	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T13	10		T188	4		T271	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17536	1			T1	150		T3	104		T8	133
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T252	15		T167	11		T301	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T26	10		T157	4		T194	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T7	9		T182	15		T32	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T140	7		T133	15		T208	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T11	23		T34	4		T129	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T7	10		T9	18		T45	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T26	12		T123	7		T202	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1263	1			T4	24		T35	26		T163	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T89	11		T203	9		T126	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T89	10		T90	10		T134	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T183	6		T22	4		T45	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T202	9		T208	4		T235	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T131	9		T184	21		T129	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T3	1		T124	14		T129	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T11	11		T128	5		T136	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T3	5		T7	2		T12	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T6	12		T34	8		T215	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T90	12		T31	4		T223	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T13	7		T207	12		T122	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T187	11		T18	2		T292	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T13	9		T188	3		T288	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T303	12		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T252	21		T167	5		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T90	13		T302	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T207	1		T209	10		T289	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T299	4		T257	1		T300	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T26	11		T93	8		T95	19
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T7	12		T160	1		T32	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T5	1		T12	2		T157	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T5	1		T11	11		T182	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T7	1		T9	20		T45	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T11	12		T34	14		T123	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1371	1			T2	11		T4	2		T35	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T5	1		T26	12		T183	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T123	1		T183	1		T90	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T22	10		T45	4		T125	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T3	3		T89	7		T93	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T131	1		T136	15		T33	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T123	1		T124	19		T202	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T11	3		T25	1		T76	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T3	4		T12	11		T27	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T6	1		T34	3		T141	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T3	6		T7	10		T76	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	385	1			T93	12		T13	17		T188	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17524	1			T1	150		T3	104		T8	133
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T90	12		T302	8		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T207	12		T209	11		T289	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T299	3		T257	17		T300	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T26	10		T194	16		T192	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T7	9		T32	1		T264	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T157	4		T140	7		T208	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T11	12		T182	15		T129	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T7	10		T9	18		T45	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T11	11		T34	4		T123	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1253	1			T4	24		T35	26		T163	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T26	12		T183	6		T89	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T123	12		T183	2		T90	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T22	4		T45	10		T136	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T89	10		T129	13		T208	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T131	9		T136	12		T33	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T123	10		T124	14		T202	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T11	11		T128	5		T184	21
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T3	1		T12	4		T27	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T6	12		T34	8		T210	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T3	5		T7	2		T187	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T13	16		T188	3		T122	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22589

1

T1

150

T2

11

T3

117

auto[1]

auto[0]

4191

1

T3

6

T4

24

T6

12