Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26780

1

T1

150

T2

11

T3

123

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20805

1

T1

150

T3

112

T5

2

auto[ADC_CTRL_FILTER_COND_OUT]

5975

1

T2

11

T3

11

T4

26

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20780

1

T1

150

T3

104

T5

2

auto[1]

6000

1

T2

11

T3

19

T4

26

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22677

1

T1

148

T2

1

T3

114

auto[1]

4103

1

T1

2

T2

10

T3

9

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	30	1			T141	10		T299	7		T304	13
values[0]	50	1			T136	17		T211	12		T271	1
values[1]	660	1			T5	1		T26	24		T89	22
values[2]	673	1			T6	13		T123	13		T124	33
values[3]	660	1			T3	11		T11	37		T12	2
values[4]	799	1			T5	1		T7	11		T22	14
values[5]	550	1			T3	3		T7	21		T12	15
values[6]	785	1			T11	23		T123	8		T131	10
values[7]	833	1			T3	5		T9	38		T25	1
values[8]	599	1			T5	1		T34	11		T183	3
values[9]	3617	1			T2	11		T4	26		T7	12
minimum	17524	1			T1	150		T3	104		T8	133

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	949	1			T5	1		T6	13		T26	24
values[1]	2818	1			T2	11		T3	11		T4	26
values[2]	736	1			T7	11		T11	14		T12	2
values[3]	772	1			T5	1		T12	15		T22	14
values[4]	533	1			T3	3		T7	21		T11	23
values[5]	816	1			T25	1		T76	1		T123	8
values[6]	706	1			T3	5		T5	1		T9	38
values[7]	727	1			T7	12		T34	18		T183	3
values[8]	931	1			T76	1		T34	11		T123	11
values[9]	246	1			T93	12		T13	4		T194	37
minimum	17546	1			T1	150		T3	104		T8	133

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22589

1

T1

150

T2

11

T3

117

auto[1]

4191

1

T3

6

T4

24

T6

12

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	332	1			T5	1		T26	13		T89	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T6	13		T187	12		T125	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T89	3		T184	14		T186	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1561	1			T2	1		T3	7		T4	26
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T12	1		T90	13		T184	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T7	11		T11	12		T89	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T22	5		T82	3		T133	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T5	1		T12	10		T93	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T3	2		T7	10		T131	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T11	12		T27	4		T220	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T25	1		T76	1		T45	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T123	8		T128	6		T182	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T3	4		T5	1		T26	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T9	19		T95	1		T13	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T34	5		T183	3		T93	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T7	3		T45	11		T137	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T76	1		T95	1		T202	21
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T34	9		T123	11		T157	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T13	4		T224	3		T294	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T93	1		T194	17		T30	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17409	1			T1	148		T3	101		T8	133
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T136	8		T20	3		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T26	11		T89	10		T182	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T187	11		T125	17		T141	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T89	2		T184	9		T186	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	935	1			T2	10		T3	4		T11	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T12	1		T90	12		T184	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T11	2		T89	6		T95	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T22	9		T133	4		T236	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T12	5		T93	7		T82	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T3	1		T7	11		T28	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T11	11		T138	8		T192	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T45	7		T136	14		T305	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T128	8		T182	16		T32	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T3	1		T26	10		T125	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T9	19		T95	10		T13	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T34	13		T93	1		T13	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T7	9		T45	3		T185	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T95	2		T29	4		T30	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T34	2		T157	6		T90	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T224	7		T306	18		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T93	11		T194	20		T30	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T1	2		T3	3		T27	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T136	9		T20	1		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T304	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T141	1		T299	4		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T307	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T136	8		T211	12		T271	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T5	1		T26	13		T89	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T187	12		T126	14		T141	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T203	10		T186	1		T223	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T6	13		T123	13		T124	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T12	1		T89	3		T184	30
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T3	7		T11	25		T89	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T22	5		T90	13		T82	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T5	1		T7	11		T95	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T3	2		T7	10		T13	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T12	10		T27	4		T93	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T131	10		T45	9		T125	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T11	12		T123	8		T128	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T3	4		T25	1		T26	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T9	19		T95	1		T132	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T5	1		T183	3		T93	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T34	9		T45	11		T137	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	308	1			T76	1		T95	1		T202	21
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1805	1			T2	1		T4	26		T7	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17408	1			T1	148		T3	101		T8	133
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T304	12		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T141	9		T299	3		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T136	9		T164	9		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T26	11		T89	10		T182	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T187	11		T141	11		T264	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T203	8		T186	5		T142	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T124	18		T125	17		T31	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T12	1		T89	2		T184	25
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T3	4		T11	12		T89	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T22	9		T90	12		T133	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T95	15		T82	15		T134	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T3	1		T7	11		T32	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T12	5		T93	7		T192	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T45	7		T125	4		T28	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T11	11		T128	8		T13	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T3	1		T26	10		T34	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T9	19		T95	10		T132	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T93	1		T13	6		T186	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T34	2		T45	3		T215	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T95	2		T29	4		T30	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1236	1			T2	10		T7	9		T193	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T1	2		T3	3		T27	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T5	1		T26	12		T89	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T6	1		T187	12		T125	18
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T89	3		T184	10		T186	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1268	1			T2	11		T3	6		T4	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T12	2		T90	13		T184	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T7	1		T11	3		T89	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T22	10		T82	1		T133	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T5	1		T12	11		T93	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T3	3		T7	12		T131	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T11	12		T27	3		T220	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T25	1		T76	1		T45	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T123	1		T128	9		T182	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T3	4		T5	1		T26	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T9	20		T95	11		T13	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T34	14		T183	1		T93	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T7	10		T45	4		T137	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T76	1		T95	3		T202	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	314	1			T34	3		T123	1		T157	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T13	1		T224	8		T294	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T93	12		T194	21		T30	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17525	1			T1	150		T3	104		T8	133
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T136	10		T20	3		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T26	12		T89	11		T244	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T6	12		T187	11		T126	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T89	2		T184	13		T252	21
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1228	1			T3	5		T4	24		T11	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T90	12		T184	15		T203	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T7	10		T11	11		T89	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T22	4		T82	2		T133	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T12	4		T82	10		T207	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T7	9		T131	9		T28	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T11	11		T27	1		T192	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T45	8		T129	32		T136	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T123	7		T128	5		T182	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T3	1		T26	10		T140	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T9	18		T13	9		T129	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T34	4		T183	2		T13	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T7	2		T45	10		T185	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T202	19		T29	4		T30	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T34	8		T123	10		T157	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T13	3		T224	2		T292	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T194	16		T30	3		T295	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T136	7		T20	1		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T304	13		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T141	10		T299	4		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T307	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T136	10		T211	1		T271	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T5	1		T26	12		T89	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T187	12		T126	2		T141	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T203	9		T186	6		T223	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T6	1		T123	1		T124	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T12	2		T89	3		T184	27
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T3	6		T11	14		T89	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T22	10		T90	13		T82	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	306	1			T5	1		T7	1		T95	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T3	3		T7	12		T13	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T12	11		T27	3		T93	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T131	1		T45	8		T125	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T11	12		T123	1		T128	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T3	4		T25	1		T26	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T9	20		T95	11		T132	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T5	1		T183	1		T93	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T34	3		T45	4		T137	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	334	1			T76	1		T95	3		T202	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1633	1			T2	11		T4	2		T7	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17524	1			T1	150		T3	104		T8	133
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T299	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T136	7		T211	11		T164	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T26	12		T89	11		T244	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T187	11		T126	12		T264	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T203	9		T223	10		T252	21
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T6	12		T123	12		T124	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T89	2		T184	28		T308	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T3	5		T11	23		T89	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T22	4		T90	12		T82	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T7	10		T32	1		T82	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T7	9		T32	1		T208	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T12	4		T27	1		T192	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T131	9		T45	8		T129	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T11	11		T123	7		T128	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T3	1		T26	10		T34	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T9	18		T129	10		T134	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T183	2		T13	7		T309	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T34	8		T45	10		T215	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T202	19		T13	3		T29	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1408	1			T4	24		T7	2		T35	26

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22589

1

T1

150

T2

11

T3

117

auto[1]

auto[0]

4191

1

T3

6

T4

24

T6

12