Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26780

1

T1

150

T2

11

T3

123

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23113

1

T1

150

T2

11

T3

123

auto[ADC_CTRL_FILTER_COND_OUT]

3667

1

T5

2

T7

32

T11

37

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19895

1

T1

148

T3

111

T5

1

auto[1]

6885

1

T1

2

T2

11

T3

12

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22677

1

T1

148

T2

1

T3

114

auto[1]

4103

1

T1

2

T2

10

T3

9

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	684	1			T1	2		T3	7		T8	8
values[0]	65	1			T310	1		T236	26		T249	10
values[1]	720	1			T34	11		T123	11		T93	12
values[2]	3048	1			T2	11		T4	26		T5	1
values[3]	625	1			T3	5		T12	15		T183	3
values[4]	852	1			T6	13		T7	12		T12	2
values[5]	640	1			T3	3		T5	2		T26	24
values[6]	624	1			T7	32		T25	1		T187	23
values[7]	672	1			T3	11		T11	46		T76	1
values[8]	702	1			T132	13		T125	18		T31	13
values[9]	1109	1			T11	14		T76	1		T123	21
minimum	17039	1			T1	148		T3	97		T8	125

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	733	1			T34	11		T123	11		T27	4
values[1]	3094	1			T2	11		T4	26		T5	1
values[2]	651	1			T3	5		T6	13		T12	2
values[3]	764	1			T5	1		T7	12		T34	18
values[4]	650	1			T3	3		T5	1		T7	11
values[5]	555	1			T7	21		T25	1		T128	14
values[6]	780	1			T3	11		T11	46		T76	1
values[7]	776	1			T123	13		T132	13		T125	18
values[8]	900	1			T11	14		T76	1		T123	8
values[9]	119	1			T95	16		T184	32		T220	1
minimum	17758	1			T1	150		T3	104		T8	133

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22589

1

T1

150

T2

11

T3

117

auto[1]

4191

1

T3

6

T4

24

T6

12

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T123	11		T27	4		T182	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T34	9		T93	1		T125	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1600	1			T2	1		T4	26		T9	19
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T5	1		T26	11		T13	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T3	4		T6	13		T183	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T12	1		T89	12		T129	20
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T5	1		T7	3		T34	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T124	15		T131	10		T183	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T3	2		T26	13		T89	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T5	1		T7	11		T159	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T25	1		T14	3		T133	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T7	10		T128	6		T187	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T3	7		T11	12		T76	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T11	13		T90	13		T202	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T132	1		T30	12		T32	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T123	13		T125	1		T126	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T157	5		T22	5		T45	20
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T11	12		T76	1		T123	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T184	16		T220	1		T223	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T95	1		T311	1		T312	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17440	1			T1	148		T3	101		T8	133
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T13	2		T82	11		T236	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T182	16		T33	1		T122	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T34	2		T93	11		T125	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1009	1			T2	10		T9	19		T12	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T26	10		T13	6		T224	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T3	1		T203	8		T29	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T12	1		T89	10		T264	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T7	9		T34	13		T194	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T124	18		T93	1		T95	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T3	1		T26	11		T89	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T186	9		T192	9		T142	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T14	2		T133	4		T122	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T7	11		T128	8		T187	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T3	4		T11	11		T95	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T11	10		T90	12		T28	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T132	12		T30	11		T32	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T125	17		T134	13		T224	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T157	6		T22	9		T45	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T11	2		T136	23		T134	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T184	16		T313	3		T314	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T95	15		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T1	2		T3	3		T27	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T82	15		T236	11		T150	14

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	527	1			T1	2		T3	7		T8	8
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T95	1		T136	8		T134	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T310	1		T249	10		T315	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T236	15		T292	13		T316	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T123	11		T182	16		T29	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T34	9		T93	1		T13	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1623	1			T2	1		T4	26		T9	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T5	1		T26	11		T13	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T3	4		T12	10		T183	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T89	12		T264	6		T236	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T6	13		T7	3		T34	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	342	1			T12	1		T124	15		T131	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T3	2		T5	1		T26	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T5	1		T93	1		T95	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T25	1		T14	3		T133	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T7	21		T187	12		T159	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T3	7		T11	12		T76	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T11	13		T128	6		T90	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T132	1		T31	7		T215	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T125	1		T126	1		T127	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	309	1			T22	5		T45	9		T89	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T11	12		T76	1		T123	21
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16923	1			T1	146		T3	94		T8	125
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T157	6		T45	3		T303	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T95	15		T136	9		T134	19
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T236	11		T304	12		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T182	16		T33	1		T122	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T34	2		T93	11		T188	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1010	1			T2	10		T9	19		T193	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T26	10		T13	6		T125	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T3	1		T12	5		T203	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T89	10		T264	7		T265	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T7	9		T34	13		T295	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T12	1		T124	18		T184	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T3	1		T26	11		T89	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T93	1		T95	2		T140	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T14	2		T133	4		T122	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T7	11		T187	11		T195	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T3	4		T11	11		T95	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T11	10		T128	8		T90	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T132	12		T31	6		T215	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T125	17		T134	13		T141	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	298	1			T22	9		T45	7		T89	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T11	2		T136	14		T138	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T1	2		T3	3		T27	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[9]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T123	1		T27	3		T182	17
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T34	3		T93	12		T125	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1355	1			T2	11		T4	2		T9	20
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T5	1		T26	11		T13	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T3	4		T6	1		T183	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T12	2		T89	11		T129	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T5	1		T7	10		T34	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T124	19		T131	1		T183	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T3	3		T26	12		T89	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T5	1		T7	1		T159	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T25	1		T14	4		T133	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T7	12		T128	9		T187	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T3	6		T11	12		T76	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T11	11		T90	13		T202	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T132	13		T30	12		T32	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T123	1		T125	18		T126	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T157	7		T22	10		T45	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T11	3		T76	1		T123	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T184	17		T220	1		T223	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T95	16		T311	1		T312	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17576	1			T1	150		T3	104		T8	133
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T13	2		T82	16		T236	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T123	10		T27	1		T182	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T34	8		T188	3		T232	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1254	1			T4	24		T9	18		T12	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T26	10		T13	7		T224	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T3	1		T6	12		T183	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T89	11		T129	19		T264	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T7	2		T34	4		T13	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T124	14		T131	9		T183	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T26	12		T89	10		T90	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T7	10		T192	9		T142	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T14	1		T133	15		T122	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T7	9		T128	5		T187	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T3	5		T11	11		T13	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T11	12		T90	12		T202	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T30	11		T32	1		T215	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T123	12		T134	13		T210	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T157	4		T22	4		T45	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T11	11		T123	7		T129	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T184	15		T223	10		T314	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T144	6		T278	1		T180	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T82	10		T236	14		T21	5

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	551	1			T1	2		T3	7		T8	8
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T95	16		T136	10		T134	20
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T310	1		T249	1		T315	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T236	12		T292	1		T316	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T123	1		T182	17		T29	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T34	3		T93	12		T13	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1352	1			T2	11		T4	2		T9	20
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T5	1		T26	11		T13	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T3	4		T12	11		T183	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T89	11		T264	8		T236	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T6	1		T7	10		T34	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T12	2		T124	19		T131	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T3	3		T5	1		T26	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T5	1		T93	2		T95	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T25	1		T14	4		T133	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T7	13		T187	12		T159	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T3	6		T11	12		T76	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T11	11		T128	9		T90	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T132	13		T31	9		T215	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T125	18		T126	1		T127	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	362	1			T22	10		T45	8		T89	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T11	3		T76	1		T123	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17039	1			T1	148		T3	97		T8	125
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T157	4		T45	10		T292	6
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T136	7		T134	10		T317	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T249	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T236	14		T292	12		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T123	10		T182	15		T126	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T34	8		T188	3		T82	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1281	1			T4	24		T9	18		T35	26
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T26	10		T13	7		T224	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T3	1		T12	4		T183	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T89	11		T264	5		T24	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T6	12		T7	2		T34	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T124	14		T131	9		T183	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T26	12		T89	10		T90	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T140	7		T142	18		T226	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T14	1		T133	15		T122	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T7	19		T187	11		T192	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T3	5		T11	11		T13	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T11	12		T128	5		T90	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T31	4		T215	8		T148	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T134	13		T210	8		T224	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T22	4		T45	8		T89	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T11	11		T123	19		T129	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22589

1

T1

150

T2

11

T3

117

auto[1]

auto[0]

4191

1

T3

6

T4

24

T6

12