Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26780

1

T1

150

T2

11

T3

123

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23122

1

T1

150

T2

11

T3

118

auto[ADC_CTRL_FILTER_COND_OUT]

3658

1

T3

5

T7

11

T26

21

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19947

1

T1

148

T3

116

T5

1

auto[1]

6833

1

T1

2

T2

11

T3

7

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22677

1

T1

148

T2

1

T3

114

auto[1]

4103

1

T1

2

T2

10

T3

9

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	546	1			T1	2		T3	7		T8	8
values[0]	83	1			T310	1		T236	26		T214	7
values[1]	665	1			T34	11		T123	11		T93	12
values[2]	3050	1			T2	11		T4	26		T5	1
values[3]	709	1			T3	5		T12	15		T131	10
values[4]	836	1			T5	1		T6	13		T7	12
values[5]	669	1			T3	3		T5	1		T26	24
values[6]	653	1			T7	32		T25	1		T128	14
values[7]	575	1			T3	11		T11	46		T76	1
values[8]	676	1			T95	11		T182	4		T132	13
values[9]	1279	1			T11	14		T76	1		T123	21
minimum	17039	1			T1	148		T3	97		T8	125

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	952	1			T5	1		T34	11		T123	11
values[1]	3090	1			T2	11		T4	26		T9	38
values[2]	697	1			T3	5		T6	13		T12	2
values[3]	700	1			T5	1		T7	12		T34	18
values[4]	627	1			T3	3		T5	1		T7	11
values[5]	557	1			T7	21		T25	1		T128	14
values[6]	779	1			T3	11		T11	46		T76	1
values[7]	811	1			T76	1		T123	21		T132	13
values[8]	863	1			T157	11		T22	14		T45	30
values[9]	155	1			T11	14		T184	32		T220	1
minimum	17549	1			T1	150		T3	104		T8	133

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22589

1

T1

150

T2

11

T3

117

auto[1]

4191

1

T3

6

T4

24

T6

12

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T5	1		T123	11		T182	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T34	9		T27	4		T93	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1574	1			T2	1		T4	26		T9	19
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	302	1			T26	11		T13	8		T174	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T6	13		T12	1		T13	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T3	4		T129	20		T244	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T5	1		T7	3		T34	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T131	10		T183	7		T93	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T3	2		T5	1		T26	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T7	11		T129	11		T159	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T7	10		T25	1		T128	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T187	12		T140	1		T14	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T3	7		T11	25		T76	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T90	13		T202	11		T28	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T132	1		T32	2		T186	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T76	1		T123	21		T125	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T22	5		T89	3		T95	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T157	5		T45	20		T13	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T11	12		T184	16		T220	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T223	11		T313	1		T314	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17412	1			T1	148		T3	101		T8	133
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T249	10		T151	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T182	16		T125	6		T82	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T34	2		T93	11		T188	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	952	1			T2	10		T9	19		T12	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T26	10		T13	6		T174	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T12	1		T203	8		T29	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T3	1		T244	5		T264	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T7	9		T34	13		T124	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T93	1		T95	2		T184	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T3	1		T26	11		T89	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T186	9		T236	2		T142	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T7	11		T128	8		T133	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T187	11		T14	2		T122	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T3	4		T11	21		T95	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T90	12		T28	2		T215	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T132	12		T32	1		T186	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T125	21		T30	11		T32	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T22	9		T89	2		T95	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T157	6		T45	10		T136	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T11	2		T184	16		T318	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T313	3		T314	13		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T1	2		T3	3		T27	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T151	10		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	510	1			T1	2		T3	7		T8	8
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T223	11		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T310	1		T214	7		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T236	15		T249	10		T292	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T123	11		T182	16		T29	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T34	9		T93	1		T13	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1561	1			T2	1		T4	26		T5	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	316	1			T26	11		T27	4		T13	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T12	10		T183	3		T89	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T3	4		T131	10		T129	20
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T5	1		T6	13		T7	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T184	14		T244	15		T127	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T3	2		T5	1		T26	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T183	7		T93	1		T95	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T7	10		T25	1		T128	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T7	11		T187	12		T159	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T3	7		T11	25		T76	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T90	13		T202	11		T125	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T95	1		T182	1		T132	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T125	1		T126	1		T134	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	351	1			T11	12		T22	5		T89	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	338	1			T76	1		T123	21		T157	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16923	1			T1	146		T3	94		T8	125
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T184	16		T266	9		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T236	11		T304	12		T319	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T182	16		T82	15		T33	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T34	2		T93	11		T188	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	968	1			T2	10		T9	19		T193	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T26	10		T13	6		T224	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T12	5		T89	10		T29	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T3	1		T264	17		T24	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T7	9		T12	1		T34	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T184	9		T244	5		T264	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T3	1		T26	11		T89	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T93	1		T95	2		T140	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T7	11		T128	8		T184	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T187	11		T14	2		T122	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T3	4		T11	21		T13	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T90	12		T125	4		T28	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T95	10		T182	3		T132	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T125	17		T134	13		T236	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	302	1			T11	2		T22	9		T89	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T157	6		T45	10		T136	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T1	2		T3	3		T27	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	297	1			T5	1		T123	1		T182	17
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T34	3		T27	3		T93	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1298	1			T2	11		T4	2		T9	20
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T26	11		T13	7		T174	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T6	1		T12	2		T13	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T3	4		T129	1		T244	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T5	1		T7	10		T34	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T131	1		T183	1		T93	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T3	3		T5	1		T26	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T7	1		T129	1		T159	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T7	12		T25	1		T128	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T187	12		T140	1		T14	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T3	6		T11	23		T76	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T90	13		T202	1		T28	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T132	13		T32	2		T186	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T76	1		T123	2		T125	23
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T22	10		T89	3		T95	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T157	7		T45	12		T13	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T11	3		T184	17		T220	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T223	1		T313	4		T314	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17525	1			T1	150		T3	104		T8	133
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T249	1		T151	11		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T123	10		T182	15		T82	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T34	8		T27	1		T188	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1228	1			T4	24		T9	18		T12	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T26	10		T13	7		T174	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T6	12		T203	9		T29	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T3	1		T129	19		T244	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T7	2		T34	4		T124	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T131	9		T183	6		T202	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T26	12		T89	10		T90	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T7	10		T129	10		T236	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T7	9		T128	5		T133	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T187	11		T14	1		T122	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T3	5		T11	23		T13	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T90	12		T202	10		T28	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T32	1		T210	8		T224	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T123	19		T30	11		T134	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T22	4		T89	2		T129	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T157	4		T45	18		T136	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T11	11		T184	15		T318	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T223	10		T314	4		T320	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T321	3		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T249	9		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	512	1			T1	2		T3	7		T8	8
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T223	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T310	1		T214	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T236	12		T249	1		T292	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T123	1		T182	17		T29	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T34	3		T93	12		T13	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1304	1			T2	11		T4	2		T5	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T26	11		T27	3		T13	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T12	11		T183	1		T89	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T3	4		T131	1		T129	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T5	1		T6	1		T7	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T184	10		T244	6		T127	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T3	3		T5	1		T26	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T183	1		T93	2		T95	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T7	12		T25	1		T128	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T7	1		T187	12		T159	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T3	6		T11	23		T76	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T90	13		T202	1		T125	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T95	11		T182	4		T132	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T125	18		T126	1		T134	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	367	1			T11	3		T22	10		T89	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	353	1			T76	1		T123	2		T157	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17039	1			T1	148		T3	97		T8	125
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T184	15		T266	8		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T223	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T214	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T236	14		T249	9		T292	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T123	10		T182	15		T82	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T34	8		T188	3		T126	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1225	1			T4	24		T9	18		T35	26
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T26	10		T27	1		T13	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T12	4		T183	2		T89	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T3	1		T131	9		T129	19
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T6	12		T7	2		T34	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T184	13		T244	14		T264	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T26	12		T89	10		T13	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T183	6		T202	9		T129	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T7	9		T128	5		T184	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T7	10		T187	11		T14	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T3	5		T11	23		T13	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T90	12		T202	10		T28	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T31	4		T215	8		T224	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T134	13		T276	12		T211	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T11	11		T22	4		T89	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T123	19		T157	4		T45	18

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22589

1

T1

150

T2

11

T3

117

auto[1]

auto[0]

4191

1

T3

6

T4

24

T6

12