Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26780

1

T1

150

T2

11

T3

123

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23250

1

T1

150

T2

11

T3

118

auto[ADC_CTRL_FILTER_COND_OUT]

3530

1

T3

5

T5

1

T7

12

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20300

1

T1

150

T3

120

T7

23

auto[1]

6480

1

T2

11

T3

3

T4

26

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22677

1

T1

148

T2

1

T3

114

auto[1]

4103

1

T1

2

T2

10

T3

9

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	71	1			T184	22		T142	3		T206	24
values[0]	57	1			T220	1		T214	1		T322	2
values[1]	630	1			T76	2		T123	13		T157	11
values[2]	3127	1			T2	11		T4	26		T7	11
values[3]	596	1			T5	1		T26	21		T29	9
values[4]	767	1			T7	21		T26	24		T123	8
values[5]	574	1			T5	1		T25	1		T22	14
values[6]	753	1			T5	1		T6	13		T11	37
values[7]	810	1			T3	11		T34	18		T183	7
values[8]	595	1			T7	12		T9	38		T34	11
values[9]	1276	1			T3	8		T11	23		T12	15
minimum	17524	1			T1	150		T3	104		T8	133

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	917	1			T76	2		T123	13		T93	2
values[1]	2920	1			T2	11		T4	26		T7	11
values[2]	704	1			T89	5		T202	10		T132	13
values[3]	737	1			T5	1		T7	21		T26	24
values[4]	653	1			T5	1		T25	1		T95	16
values[5]	774	1			T3	11		T5	1		T11	37
values[6]	723	1			T6	13		T9	38		T183	7
values[7]	537	1			T7	12		T12	15		T34	11
values[8]	940	1			T3	5		T11	23		T89	17
values[9]	309	1			T3	3		T210	1		T305	17
minimum	17566	1			T1	150		T3	104		T8	133

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22589

1

T1

150

T2

11

T3

117

auto[1]

4191

1

T3

6

T4

24

T6

12

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T76	1		T123	13		T182	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T76	1		T93	1		T125	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1687	1			T2	1		T4	26		T7	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T131	10		T13	4		T184	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T202	10		T135	1		T129	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T89	3		T132	1		T129	20
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T5	1		T7	10		T26	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T22	5		T208	15		T186	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T5	1		T13	1		T140	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T25	1		T95	1		T13	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T3	7		T12	1		T34	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T5	1		T11	24		T89	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T6	13		T9	19		T183	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T27	4		T90	11		T202	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T95	1		T13	3		T207	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T7	3		T12	10		T34	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T89	11		T90	13		T184	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T3	4		T11	13		T13	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T3	2		T210	1		T267	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T305	9		T234	1		T200	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17410	1			T1	148		T3	101		T8	133
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T157	5		T323	14		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T182	16		T32	1		T122	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T93	1		T125	17		T188	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1003	1			T2	10		T26	10		T193	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T184	9		T186	9		T122	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T192	4		T144	5		T280	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T89	2		T132	12		T29	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T7	11		T26	11		T128	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T22	9		T186	11		T148	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T31	6		T229	2		T161	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T95	15		T13	8		T136	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T3	4		T12	1		T34	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T11	13		T89	10		T203	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T9	19		T93	11		T182	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T90	13		T125	10		T140	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T95	10		T185	9		T141	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T7	9		T12	5		T34	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T89	6		T90	12		T184	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T3	1		T11	10		T13	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T3	1		T324	9		T254	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T305	8		T200	9		T142	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T1	2		T3	3		T27	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T157	6		T323	14		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T184	9		T273	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T142	1		T206	13		T325	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T220	1		T322	1		T326	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T214	1		T286	1		T327	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T76	1		T123	13		T122	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T76	1		T157	5		T125	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1683	1			T2	1		T4	26		T7	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T131	10		T93	1		T13	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T5	1		T26	11		T127	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T29	5		T244	15		T186	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T7	10		T26	13		T123	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T89	3		T159	1		T186	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T5	1		T95	1		T140	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T25	1		T22	5		T95	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T6	13		T12	1		T13	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T5	1		T11	24		T13	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T3	7		T34	5		T183	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T45	9		T27	4		T89	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T9	19		T90	13		T95	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T7	3		T34	9		T183	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T3	2		T89	11		T29	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	379	1			T3	4		T11	13		T12	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17408	1			T1	148		T3	101		T8	133
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T184	13		T273	9		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T142	2		T206	11		T325	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T322	1		T326	13		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T327	2		T328	17		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T122	9		T195	10		T192	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T157	6		T125	17		T188	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1034	1			T2	10		T193	12		T153	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T93	1		T184	9		T132	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T26	10		T192	4		T200	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T29	4		T244	5		T186	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T7	11		T26	11		T128	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T89	2		T186	11		T191	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T95	2		T134	8		T229	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T22	9		T95	15		T28	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T12	1		T31	6		T148	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T11	13		T13	8		T136	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T3	4		T34	13		T93	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T45	7		T89	10		T90	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T9	19		T90	12		T95	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T7	9		T34	2		T125	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T3	1		T89	6		T30	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	378	1			T3	1		T11	10		T12	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T1	2		T3	3		T27	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T76	1		T123	1		T182	17
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T76	1		T93	2		T125	18
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1349	1			T2	11		T4	2		T7	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T131	1		T13	1		T184	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T202	1		T135	1		T129	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T89	3		T132	13		T129	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T5	1		T7	12		T26	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T22	10		T208	1		T186	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T5	1		T13	1		T140	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T25	1		T95	16		T13	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T3	6		T12	2		T34	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T5	1		T11	15		T89	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T6	1		T9	20		T183	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T27	3		T90	14		T202	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T95	11		T13	3		T207	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T7	10		T12	11		T34	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T89	7		T90	13		T184	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	316	1			T3	4		T11	11		T13	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T3	3		T210	1		T267	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T305	9		T234	1		T200	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17527	1			T1	150		T3	104		T8	133
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T157	7		T323	15		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T123	12		T182	15		T32	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T129	10		T188	3		T82	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1341	1			T4	24		T7	10		T26	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T131	9		T13	3		T184	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T202	9		T129	13		T210	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T89	2		T129	19		T29	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T7	9		T26	12		T123	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T22	4		T208	14		T223	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T31	4		T210	8		T209	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T13	9		T136	7		T28	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T3	5		T34	4		T134	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T11	22		T89	11		T203	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T6	12		T9	18		T183	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T27	1		T90	10		T202	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T207	12		T126	12		T185	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T7	2		T12	4		T34	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T89	10		T90	12		T184	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T3	1		T11	12		T13	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T267	7		T324	8		T329	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T305	8		T197	11		T167	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T157	4		T323	13		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T184	14		T273	10		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T142	3		T206	12		T325	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T220	1		T322	2		T326	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T214	1		T286	1		T327	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T76	1		T123	1		T122	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T76	1		T157	7		T125	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1381	1			T2	11		T4	2		T7	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T131	1		T93	2		T13	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T5	1		T26	11		T127	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T29	5		T244	6		T186	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T7	12		T26	12		T123	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T89	3		T159	1		T186	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T5	1		T95	3		T140	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T25	1		T22	10		T95	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T6	1		T12	2		T13	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T5	1		T11	15		T13	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T3	6		T34	14		T183	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T45	8		T27	3		T89	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T9	20		T90	13		T95	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T7	10		T34	3		T183	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	303	1			T3	3		T89	7		T29	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	464	1			T3	4		T11	11		T12	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17524	1			T1	150		T3	104		T8	133
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T184	8		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T206	12		T325	9		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T328	15		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T123	12		T122	6		T192	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T157	4		T188	3		T82	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1336	1			T4	24		T7	10		T35	26
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T131	9		T13	3		T184	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T26	10		T210	12		T192	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T29	4		T244	14		T122	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T7	9		T26	12		T123	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T89	2		T223	10		T276	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T134	3		T210	8		T270	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T22	4		T28	1		T194	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T6	12		T31	4		T148	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T11	22		T13	9		T136	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T3	5		T34	4		T183	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T45	8		T27	1		T89	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T9	18		T90	12		T207	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T7	2		T34	8		T183	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T89	10		T14	1		T185	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T3	1		T11	12		T12	4

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22589

1

T1

150

T2

11

T3

117

auto[1]

auto[0]

4191

1

T3

6

T4

24

T6

12