interrupt_cp | min_v_cp | cond_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
values[0] |
auto[ADC_CTRL_FILTER_COND_IN] |
210 |
1 |
|
|
T123 |
13 |
|
T182 |
16 |
|
T220 |
1 |
auto[0] |
values[0] |
auto[ADC_CTRL_FILTER_COND_OUT] |
215 |
1 |
|
|
T76 |
1 |
|
T157 |
5 |
|
T93 |
1 |
auto[0] |
values[1] |
auto[ADC_CTRL_FILTER_COND_IN] |
1694 |
1 |
|
|
T2 |
1 |
|
T4 |
26 |
|
T7 |
11 |
auto[0] |
values[1] |
auto[ADC_CTRL_FILTER_COND_OUT] |
153 |
1 |
|
|
T13 |
4 |
|
T184 |
14 |
|
T132 |
1 |
auto[0] |
values[2] |
auto[ADC_CTRL_FILTER_COND_IN] |
170 |
1 |
|
|
T135 |
1 |
|
T129 |
14 |
|
T127 |
1 |
auto[0] |
values[2] |
auto[ADC_CTRL_FILTER_COND_OUT] |
227 |
1 |
|
|
T131 |
10 |
|
T89 |
3 |
|
T159 |
1 |
auto[0] |
values[3] |
auto[ADC_CTRL_FILTER_COND_IN] |
251 |
1 |
|
|
T5 |
1 |
|
T7 |
10 |
|
T26 |
13 |
auto[0] |
values[3] |
auto[ADC_CTRL_FILTER_COND_OUT] |
172 |
1 |
|
|
T22 |
5 |
|
T208 |
15 |
|
T186 |
1 |
auto[0] |
values[4] |
auto[ADC_CTRL_FILTER_COND_IN] |
151 |
1 |
|
|
T5 |
1 |
|
T13 |
1 |
|
T140 |
1 |
auto[0] |
values[4] |
auto[ADC_CTRL_FILTER_COND_OUT] |
150 |
1 |
|
|
T25 |
1 |
|
T95 |
1 |
|
T13 |
11 |
auto[0] |
values[5] |
auto[ADC_CTRL_FILTER_COND_IN] |
219 |
1 |
|
|
T3 |
7 |
|
T12 |
1 |
|
T34 |
5 |
auto[0] |
values[5] |
auto[ADC_CTRL_FILTER_COND_OUT] |
257 |
1 |
|
|
T5 |
1 |
|
T11 |
24 |
|
T89 |
12 |
auto[0] |
values[6] |
auto[ADC_CTRL_FILTER_COND_IN] |
263 |
1 |
|
|
T6 |
13 |
|
T9 |
19 |
|
T183 |
7 |
auto[0] |
values[6] |
auto[ADC_CTRL_FILTER_COND_OUT] |
144 |
1 |
|
|
T45 |
9 |
|
T27 |
4 |
|
T90 |
11 |
auto[0] |
values[7] |
auto[ADC_CTRL_FILTER_COND_IN] |
116 |
1 |
|
|
T90 |
13 |
|
T95 |
1 |
|
T13 |
2 |
auto[0] |
values[7] |
auto[ADC_CTRL_FILTER_COND_OUT] |
198 |
1 |
|
|
T7 |
3 |
|
T12 |
10 |
|
T34 |
9 |
auto[0] |
values[8] |
auto[ADC_CTRL_FILTER_COND_IN] |
240 |
1 |
|
|
T89 |
11 |
|
T13 |
1 |
|
T184 |
9 |
auto[0] |
values[8] |
auto[ADC_CTRL_FILTER_COND_OUT] |
303 |
1 |
|
|
T3 |
4 |
|
T11 |
13 |
|
T13 |
8 |
auto[0] |
values[9] |
auto[ADC_CTRL_FILTER_COND_IN] |
32 |
1 |
|
|
T3 |
2 |
|
T30 |
1 |
|
T210 |
1 |
auto[0] |
values[9] |
auto[ADC_CTRL_FILTER_COND_OUT] |
42 |
1 |
|
|
T200 |
1 |
|
T142 |
1 |
|
T303 |
1 |
auto[0] |
minimum |
auto[ADC_CTRL_FILTER_COND_IN] |
17435 |
1 |
|
|
T1 |
148 |
|
T3 |
101 |
|
T8 |
133 |
auto[0] |
minimum |
auto[ADC_CTRL_FILTER_COND_OUT] |
35 |
1 |
|
|
T162 |
1 |
|
T190 |
1 |
|
T271 |
1 |
auto[1] |
values[0] |
auto[ADC_CTRL_FILTER_COND_IN] |
168 |
1 |
|
|
T182 |
16 |
|
T32 |
1 |
|
T122 |
9 |
auto[1] |
values[0] |
auto[ADC_CTRL_FILTER_COND_OUT] |
224 |
1 |
|
|
T157 |
6 |
|
T93 |
1 |
|
T125 |
17 |
auto[1] |
values[1] |
auto[ADC_CTRL_FILTER_COND_IN] |
1017 |
1 |
|
|
T2 |
10 |
|
T26 |
10 |
|
T193 |
12 |
auto[1] |
values[1] |
auto[ADC_CTRL_FILTER_COND_OUT] |
142 |
1 |
|
|
T184 |
9 |
|
T132 |
12 |
|
T186 |
9 |
auto[1] |
values[2] |
auto[ADC_CTRL_FILTER_COND_IN] |
87 |
1 |
|
|
T192 |
4 |
|
T144 |
5 |
|
T280 |
12 |
auto[1] |
values[2] |
auto[ADC_CTRL_FILTER_COND_OUT] |
167 |
1 |
|
|
T89 |
2 |
|
T29 |
4 |
|
T244 |
5 |
auto[1] |
values[3] |
auto[ADC_CTRL_FILTER_COND_IN] |
207 |
1 |
|
|
T7 |
11 |
|
T26 |
11 |
|
T128 |
8 |
auto[1] |
values[3] |
auto[ADC_CTRL_FILTER_COND_OUT] |
123 |
1 |
|
|
T22 |
9 |
|
T186 |
11 |
|
T148 |
13 |
auto[1] |
values[4] |
auto[ADC_CTRL_FILTER_COND_IN] |
136 |
1 |
|
|
T31 |
6 |
|
T134 |
8 |
|
T229 |
2 |
auto[1] |
values[4] |
auto[ADC_CTRL_FILTER_COND_OUT] |
175 |
1 |
|
|
T95 |
15 |
|
T13 |
8 |
|
T136 |
9 |
auto[1] |
values[5] |
auto[ADC_CTRL_FILTER_COND_IN] |
188 |
1 |
|
|
T3 |
4 |
|
T12 |
1 |
|
T34 |
13 |
auto[1] |
values[5] |
auto[ADC_CTRL_FILTER_COND_OUT] |
137 |
1 |
|
|
T11 |
13 |
|
T89 |
10 |
|
T203 |
8 |
auto[1] |
values[6] |
auto[ADC_CTRL_FILTER_COND_IN] |
196 |
1 |
|
|
T9 |
19 |
|
T93 |
11 |
|
T122 |
1 |
auto[1] |
values[6] |
auto[ADC_CTRL_FILTER_COND_OUT] |
119 |
1 |
|
|
T45 |
7 |
|
T90 |
13 |
|
T182 |
3 |
auto[1] |
values[7] |
auto[ADC_CTRL_FILTER_COND_IN] |
116 |
1 |
|
|
T90 |
12 |
|
T95 |
10 |
|
T185 |
9 |
auto[1] |
values[7] |
auto[ADC_CTRL_FILTER_COND_OUT] |
150 |
1 |
|
|
T7 |
9 |
|
T12 |
5 |
|
T34 |
2 |
auto[1] |
values[8] |
auto[ADC_CTRL_FILTER_COND_IN] |
186 |
1 |
|
|
T89 |
6 |
|
T184 |
13 |
|
T32 |
4 |
auto[1] |
values[8] |
auto[ADC_CTRL_FILTER_COND_OUT] |
293 |
1 |
|
|
T3 |
1 |
|
T11 |
10 |
|
T13 |
6 |
auto[1] |
values[9] |
auto[ADC_CTRL_FILTER_COND_IN] |
33 |
1 |
|
|
T3 |
1 |
|
T30 |
1 |
|
T330 |
2 |
auto[1] |
values[9] |
auto[ADC_CTRL_FILTER_COND_OUT] |
65 |
1 |
|
|
T200 |
9 |
|
T142 |
2 |
|
T303 |
10 |
auto[1] |
minimum |
auto[ADC_CTRL_FILTER_COND_IN] |
143 |
1 |
|
|
T1 |
2 |
|
T3 |
3 |
|
T27 |
1 |
auto[1] |
minimum |
auto[ADC_CTRL_FILTER_COND_OUT] |
31 |
1 |
|
|
T323 |
14 |
|
T255 |
4 |
|
T239 |
11 |
interrupt_cp | max_v_cp | cond_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
maximum |
auto[ADC_CTRL_FILTER_COND_IN] |
63 |
1 |
|
|
T3 |
2 |
|
T184 |
9 |
|
T30 |
1 |
auto[0] |
maximum |
auto[ADC_CTRL_FILTER_COND_OUT] |
106 |
1 |
|
|
T11 |
13 |
|
T138 |
1 |
|
T161 |
1 |
auto[0] |
values[0] |
auto[ADC_CTRL_FILTER_COND_IN] |
3 |
1 |
|
|
T220 |
1 |
|
T322 |
1 |
|
T326 |
1 |
auto[0] |
values[0] |
auto[ADC_CTRL_FILTER_COND_OUT] |
18 |
1 |
|
|
T214 |
1 |
|
T327 |
1 |
|
T328 |
16 |
auto[0] |
values[1] |
auto[ADC_CTRL_FILTER_COND_IN] |
183 |
1 |
|
|
T76 |
1 |
|
T123 |
13 |
|
T122 |
8 |
auto[0] |
values[1] |
auto[ADC_CTRL_FILTER_COND_OUT] |
183 |
1 |
|
|
T76 |
1 |
|
T157 |
5 |
|
T125 |
1 |
auto[0] |
values[2] |
auto[ADC_CTRL_FILTER_COND_IN] |
1691 |
1 |
|
|
T2 |
1 |
|
T4 |
26 |
|
T7 |
11 |
auto[0] |
values[2] |
auto[ADC_CTRL_FILTER_COND_OUT] |
180 |
1 |
|
|
T93 |
1 |
|
T13 |
4 |
|
T184 |
14 |
auto[0] |
values[3] |
auto[ADC_CTRL_FILTER_COND_IN] |
152 |
1 |
|
|
T127 |
1 |
|
T331 |
1 |
|
T221 |
1 |
auto[0] |
values[3] |
auto[ADC_CTRL_FILTER_COND_OUT] |
227 |
1 |
|
|
T131 |
10 |
|
T29 |
5 |
|
T244 |
15 |
auto[0] |
values[4] |
auto[ADC_CTRL_FILTER_COND_IN] |
287 |
1 |
|
|
T5 |
1 |
|
T7 |
10 |
|
T26 |
13 |
auto[0] |
values[4] |
auto[ADC_CTRL_FILTER_COND_OUT] |
144 |
1 |
|
|
T89 |
3 |
|
T159 |
1 |
|
T186 |
1 |
auto[0] |
values[5] |
auto[ADC_CTRL_FILTER_COND_IN] |
143 |
1 |
|
|
T5 |
1 |
|
T95 |
1 |
|
T140 |
1 |
auto[0] |
values[5] |
auto[ADC_CTRL_FILTER_COND_OUT] |
178 |
1 |
|
|
T25 |
1 |
|
T22 |
5 |
|
T28 |
3 |
auto[0] |
values[6] |
auto[ADC_CTRL_FILTER_COND_IN] |
230 |
1 |
|
|
T3 |
7 |
|
T6 |
13 |
|
T12 |
1 |
auto[0] |
values[6] |
auto[ADC_CTRL_FILTER_COND_OUT] |
192 |
1 |
|
|
T5 |
1 |
|
T11 |
24 |
|
T95 |
1 |
auto[0] |
values[7] |
auto[ADC_CTRL_FILTER_COND_IN] |
219 |
1 |
|
|
T34 |
5 |
|
T183 |
7 |
|
T93 |
1 |
auto[0] |
values[7] |
auto[ADC_CTRL_FILTER_COND_OUT] |
198 |
1 |
|
|
T45 |
9 |
|
T27 |
4 |
|
T89 |
12 |
auto[0] |
values[8] |
auto[ADC_CTRL_FILTER_COND_IN] |
155 |
1 |
|
|
T9 |
19 |
|
T95 |
1 |
|
T13 |
3 |
auto[0] |
values[8] |
auto[ADC_CTRL_FILTER_COND_OUT] |
173 |
1 |
|
|
T7 |
3 |
|
T34 |
9 |
|
T183 |
3 |
auto[0] |
values[9] |
auto[ADC_CTRL_FILTER_COND_IN] |
247 |
1 |
|
|
T89 |
11 |
|
T90 |
13 |
|
T29 |
1 |
auto[0] |
values[9] |
auto[ADC_CTRL_FILTER_COND_OUT] |
297 |
1 |
|
|
T3 |
4 |
|
T12 |
10 |
|
T124 |
15 |
auto[0] |
minimum |
auto[ADC_CTRL_FILTER_COND_IN] |
17408 |
1 |
|
|
T1 |
148 |
|
T3 |
101 |
|
T8 |
133 |
auto[1] |
maximum |
auto[ADC_CTRL_FILTER_COND_IN] |
61 |
1 |
|
|
T3 |
1 |
|
T184 |
13 |
|
T30 |
1 |
auto[1] |
maximum |
auto[ADC_CTRL_FILTER_COND_OUT] |
144 |
1 |
|
|
T11 |
10 |
|
T138 |
8 |
|
T161 |
4 |
auto[1] |
values[0] |
auto[ADC_CTRL_FILTER_COND_IN] |
14 |
1 |
|
|
T322 |
1 |
|
T326 |
13 |
|
- |
- |
auto[1] |
values[0] |
auto[ADC_CTRL_FILTER_COND_OUT] |
19 |
1 |
|
|
T327 |
2 |
|
T328 |
17 |
|
- |
- |
auto[1] |
values[1] |
auto[ADC_CTRL_FILTER_COND_IN] |
147 |
1 |
|
|
T122 |
9 |
|
T195 |
10 |
|
T192 |
9 |
auto[1] |
values[1] |
auto[ADC_CTRL_FILTER_COND_OUT] |
157 |
1 |
|
|
T157 |
6 |
|
T125 |
17 |
|
T188 |
3 |
auto[1] |
values[2] |
auto[ADC_CTRL_FILTER_COND_IN] |
1030 |
1 |
|
|
T2 |
10 |
|
T26 |
10 |
|
T193 |
12 |
auto[1] |
values[2] |
auto[ADC_CTRL_FILTER_COND_OUT] |
178 |
1 |
|
|
T93 |
1 |
|
T184 |
9 |
|
T132 |
12 |
auto[1] |
values[3] |
auto[ADC_CTRL_FILTER_COND_IN] |
77 |
1 |
|
|
T192 |
4 |
|
T200 |
6 |
|
T144 |
5 |
auto[1] |
values[3] |
auto[ADC_CTRL_FILTER_COND_OUT] |
194 |
1 |
|
|
T29 |
4 |
|
T244 |
5 |
|
T186 |
9 |
auto[1] |
values[4] |
auto[ADC_CTRL_FILTER_COND_IN] |
216 |
1 |
|
|
T7 |
11 |
|
T26 |
11 |
|
T128 |
8 |
auto[1] |
values[4] |
auto[ADC_CTRL_FILTER_COND_OUT] |
110 |
1 |
|
|
T89 |
2 |
|
T186 |
11 |
|
T191 |
10 |
auto[1] |
values[5] |
auto[ADC_CTRL_FILTER_COND_IN] |
112 |
1 |
|
|
T95 |
2 |
|
T134 |
8 |
|
T229 |
2 |
auto[1] |
values[5] |
auto[ADC_CTRL_FILTER_COND_OUT] |
151 |
1 |
|
|
T22 |
9 |
|
T28 |
2 |
|
T194 |
20 |
auto[1] |
values[6] |
auto[ADC_CTRL_FILTER_COND_IN] |
178 |
1 |
|
|
T3 |
4 |
|
T12 |
1 |
|
T31 |
6 |
auto[1] |
values[6] |
auto[ADC_CTRL_FILTER_COND_OUT] |
156 |
1 |
|
|
T11 |
13 |
|
T95 |
15 |
|
T13 |
8 |
auto[1] |
values[7] |
auto[ADC_CTRL_FILTER_COND_IN] |
202 |
1 |
|
|
T34 |
13 |
|
T93 |
11 |
|
T122 |
1 |
auto[1] |
values[7] |
auto[ADC_CTRL_FILTER_COND_OUT] |
122 |
1 |
|
|
T45 |
7 |
|
T89 |
10 |
|
T90 |
13 |
auto[1] |
values[8] |
auto[ADC_CTRL_FILTER_COND_IN] |
115 |
1 |
|
|
T9 |
19 |
|
T95 |
10 |
|
T141 |
9 |
auto[1] |
values[8] |
auto[ADC_CTRL_FILTER_COND_OUT] |
152 |
1 |
|
|
T7 |
9 |
|
T34 |
2 |
|
T125 |
4 |
auto[1] |
values[9] |
auto[ADC_CTRL_FILTER_COND_IN] |
209 |
1 |
|
|
T89 |
6 |
|
T90 |
12 |
|
T32 |
4 |
auto[1] |
values[9] |
auto[ADC_CTRL_FILTER_COND_OUT] |
243 |
1 |
|
|
T3 |
1 |
|
T12 |
5 |
|
T124 |
18 |
auto[1] |
minimum |
auto[ADC_CTRL_FILTER_COND_IN] |
116 |
1 |
|
|
T1 |
2 |
|
T3 |
3 |
|
T27 |
1 |
wakeup_cp | min_v_cp | cond_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
values[0] |
auto[ADC_CTRL_FILTER_COND_IN] |
205 |
1 |
|
|
T123 |
1 |
|
T182 |
17 |
|
T220 |
1 |
auto[0] |
values[0] |
auto[ADC_CTRL_FILTER_COND_OUT] |
267 |
1 |
|
|
T76 |
1 |
|
T157 |
7 |
|
T93 |
2 |
auto[0] |
values[1] |
auto[ADC_CTRL_FILTER_COND_IN] |
1364 |
1 |
|
|
T2 |
11 |
|
T4 |
2 |
|
T7 |
1 |
auto[0] |
values[1] |
auto[ADC_CTRL_FILTER_COND_OUT] |
168 |
1 |
|
|
T13 |
1 |
|
T184 |
10 |
|
T132 |
13 |
auto[0] |
values[2] |
auto[ADC_CTRL_FILTER_COND_IN] |
117 |
1 |
|
|
T135 |
1 |
|
T129 |
1 |
|
T127 |
1 |
auto[0] |
values[2] |
auto[ADC_CTRL_FILTER_COND_OUT] |
210 |
1 |
|
|
T131 |
1 |
|
T89 |
3 |
|
T159 |
1 |
auto[0] |
values[3] |
auto[ADC_CTRL_FILTER_COND_IN] |
264 |
1 |
|
|
T5 |
1 |
|
T7 |
12 |
|
T26 |
12 |
auto[0] |
values[3] |
auto[ADC_CTRL_FILTER_COND_OUT] |
152 |
1 |
|
|
T22 |
10 |
|
T208 |
1 |
|
T186 |
12 |
auto[0] |
values[4] |
auto[ADC_CTRL_FILTER_COND_IN] |
170 |
1 |
|
|
T5 |
1 |
|
T13 |
1 |
|
T140 |
1 |
auto[0] |
values[4] |
auto[ADC_CTRL_FILTER_COND_OUT] |
212 |
1 |
|
|
T25 |
1 |
|
T95 |
16 |
|
T13 |
10 |
auto[0] |
values[5] |
auto[ADC_CTRL_FILTER_COND_IN] |
228 |
1 |
|
|
T3 |
6 |
|
T12 |
2 |
|
T34 |
14 |
auto[0] |
values[5] |
auto[ADC_CTRL_FILTER_COND_OUT] |
178 |
1 |
|
|
T5 |
1 |
|
T11 |
15 |
|
T89 |
11 |
auto[0] |
values[6] |
auto[ADC_CTRL_FILTER_COND_IN] |
247 |
1 |
|
|
T6 |
1 |
|
T9 |
20 |
|
T183 |
1 |
auto[0] |
values[6] |
auto[ADC_CTRL_FILTER_COND_OUT] |
153 |
1 |
|
|
T45 |
8 |
|
T27 |
3 |
|
T90 |
14 |
auto[0] |
values[7] |
auto[ADC_CTRL_FILTER_COND_IN] |
142 |
1 |
|
|
T90 |
13 |
|
T95 |
11 |
|
T13 |
2 |
auto[0] |
values[7] |
auto[ADC_CTRL_FILTER_COND_OUT] |
192 |
1 |
|
|
T7 |
10 |
|
T12 |
11 |
|
T34 |
3 |
auto[0] |
values[8] |
auto[ADC_CTRL_FILTER_COND_IN] |
239 |
1 |
|
|
T89 |
7 |
|
T13 |
1 |
|
T184 |
14 |
auto[0] |
values[8] |
auto[ADC_CTRL_FILTER_COND_OUT] |
363 |
1 |
|
|
T3 |
4 |
|
T11 |
11 |
|
T13 |
7 |
auto[0] |
values[9] |
auto[ADC_CTRL_FILTER_COND_IN] |
42 |
1 |
|
|
T3 |
3 |
|
T30 |
2 |
|
T210 |
1 |
auto[0] |
values[9] |
auto[ADC_CTRL_FILTER_COND_OUT] |
72 |
1 |
|
|
T200 |
10 |
|
T142 |
3 |
|
T303 |
11 |
auto[0] |
minimum |
auto[ADC_CTRL_FILTER_COND_IN] |
17560 |
1 |
|
|
T1 |
150 |
|
T3 |
104 |
|
T8 |
133 |
auto[0] |
minimum |
auto[ADC_CTRL_FILTER_COND_OUT] |
44 |
1 |
|
|
T162 |
1 |
|
T190 |
1 |
|
T271 |
1 |
auto[1] |
values[0] |
auto[ADC_CTRL_FILTER_COND_IN] |
173 |
1 |
|
|
T123 |
12 |
|
T182 |
15 |
|
T32 |
1 |
auto[1] |
values[0] |
auto[ADC_CTRL_FILTER_COND_OUT] |
172 |
1 |
|
|
T157 |
4 |
|
T129 |
10 |
|
T188 |
3 |
auto[1] |
values[1] |
auto[ADC_CTRL_FILTER_COND_IN] |
1347 |
1 |
|
|
T4 |
24 |
|
T7 |
10 |
|
T26 |
10 |
auto[1] |
values[1] |
auto[ADC_CTRL_FILTER_COND_OUT] |
127 |
1 |
|
|
T13 |
3 |
|
T184 |
13 |
|
T129 |
19 |
auto[1] |
values[2] |
auto[ADC_CTRL_FILTER_COND_IN] |
140 |
1 |
|
|
T129 |
13 |
|
T210 |
12 |
|
T192 |
4 |
auto[1] |
values[2] |
auto[ADC_CTRL_FILTER_COND_OUT] |
184 |
1 |
|
|
T131 |
9 |
|
T89 |
2 |
|
T29 |
4 |
auto[1] |
values[3] |
auto[ADC_CTRL_FILTER_COND_IN] |
194 |
1 |
|
|
T7 |
9 |
|
T26 |
12 |
|
T123 |
7 |
auto[1] |
values[3] |
auto[ADC_CTRL_FILTER_COND_OUT] |
143 |
1 |
|
|
T22 |
4 |
|
T208 |
14 |
|
T223 |
10 |
auto[1] |
values[4] |
auto[ADC_CTRL_FILTER_COND_IN] |
117 |
1 |
|
|
T31 |
4 |
|
T134 |
3 |
|
T209 |
11 |
auto[1] |
values[4] |
auto[ADC_CTRL_FILTER_COND_OUT] |
113 |
1 |
|
|
T13 |
9 |
|
T136 |
7 |
|
T28 |
1 |
auto[1] |
values[5] |
auto[ADC_CTRL_FILTER_COND_IN] |
179 |
1 |
|
|
T3 |
5 |
|
T34 |
4 |
|
T148 |
11 |
auto[1] |
values[5] |
auto[ADC_CTRL_FILTER_COND_OUT] |
216 |
1 |
|
|
T11 |
22 |
|
T89 |
11 |
|
T203 |
9 |
auto[1] |
values[6] |
auto[ADC_CTRL_FILTER_COND_IN] |
212 |
1 |
|
|
T6 |
12 |
|
T9 |
18 |
|
T183 |
6 |
auto[1] |
values[6] |
auto[ADC_CTRL_FILTER_COND_OUT] |
110 |
1 |
|
|
T45 |
8 |
|
T27 |
1 |
|
T90 |
10 |
auto[1] |
values[7] |
auto[ADC_CTRL_FILTER_COND_IN] |
90 |
1 |
|
|
T90 |
12 |
|
T207 |
12 |
|
T185 |
4 |
auto[1] |
values[7] |
auto[ADC_CTRL_FILTER_COND_OUT] |
156 |
1 |
|
|
T7 |
2 |
|
T12 |
4 |
|
T34 |
8 |
auto[1] |
values[8] |
auto[ADC_CTRL_FILTER_COND_IN] |
187 |
1 |
|
|
T89 |
10 |
|
T184 |
8 |
|
T14 |
1 |
auto[1] |
values[8] |
auto[ADC_CTRL_FILTER_COND_OUT] |
233 |
1 |
|
|
T3 |
1 |
|
T11 |
12 |
|
T13 |
7 |
auto[1] |
values[9] |
auto[ADC_CTRL_FILTER_COND_IN] |
23 |
1 |
|
|
T324 |
8 |
|
T329 |
15 |
|
- |
- |
auto[1] |
values[9] |
auto[ADC_CTRL_FILTER_COND_OUT] |
35 |
1 |
|
|
T206 |
12 |
|
T332 |
8 |
|
T300 |
15 |
auto[1] |
minimum |
auto[ADC_CTRL_FILTER_COND_IN] |
18 |
1 |
|
|
T206 |
18 |
|
- |
- |
|
- |
- |
auto[1] |
minimum |
auto[ADC_CTRL_FILTER_COND_OUT] |
22 |
1 |
|
|
T323 |
13 |
|
T239 |
9 |
|
- |
- |
wakeup_cp | max_v_cp | cond_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
maximum |
auto[ADC_CTRL_FILTER_COND_IN] |
75 |
1 |
|
|
T3 |
3 |
|
T184 |
14 |
|
T30 |
2 |
auto[0] |
maximum |
auto[ADC_CTRL_FILTER_COND_OUT] |
166 |
1 |
|
|
T11 |
11 |
|
T138 |
9 |
|
T161 |
5 |
auto[0] |
values[0] |
auto[ADC_CTRL_FILTER_COND_IN] |
17 |
1 |
|
|
T220 |
1 |
|
T322 |
2 |
|
T326 |
14 |
auto[0] |
values[0] |
auto[ADC_CTRL_FILTER_COND_OUT] |
22 |
1 |
|
|
T214 |
1 |
|
T327 |
3 |
|
T328 |
18 |
auto[0] |
values[1] |
auto[ADC_CTRL_FILTER_COND_IN] |
183 |
1 |
|
|
T76 |
1 |
|
T123 |
1 |
|
T122 |
11 |
auto[0] |
values[1] |
auto[ADC_CTRL_FILTER_COND_OUT] |
193 |
1 |
|
|
T76 |
1 |
|
T157 |
7 |
|
T125 |
18 |
auto[0] |
values[2] |
auto[ADC_CTRL_FILTER_COND_IN] |
1375 |
1 |
|
|
T2 |
11 |
|
T4 |
2 |
|
T7 |
1 |
auto[0] |
values[2] |
auto[ADC_CTRL_FILTER_COND_OUT] |
216 |
1 |
|
|
T93 |
2 |
|
T13 |
1 |
|
T184 |
10 |
auto[0] |
values[3] |
auto[ADC_CTRL_FILTER_COND_IN] |
105 |
1 |
|
|
T127 |
1 |
|
T331 |
1 |
|
T221 |
1 |
auto[0] |
values[3] |
auto[ADC_CTRL_FILTER_COND_OUT] |
234 |
1 |
|
|
T131 |
1 |
|
T29 |
5 |
|
T244 |
6 |
auto[0] |
values[4] |
auto[ADC_CTRL_FILTER_COND_IN] |
279 |
1 |
|
|
T5 |
1 |
|
T7 |
12 |
|
T26 |
12 |
auto[0] |
values[4] |
auto[ADC_CTRL_FILTER_COND_OUT] |
140 |
1 |
|
|
T89 |
3 |
|
T159 |
1 |
|
T186 |
12 |
auto[0] |
values[5] |
auto[ADC_CTRL_FILTER_COND_IN] |
138 |
1 |
|
|
T5 |
1 |
|
T95 |
3 |
|
T140 |
1 |
auto[0] |
values[5] |
auto[ADC_CTRL_FILTER_COND_OUT] |
182 |
1 |
|
|
T25 |
1 |
|
T22 |
10 |
|
T28 |
4 |
auto[0] |
values[6] |
auto[ADC_CTRL_FILTER_COND_IN] |
223 |
1 |
|
|
T3 |
6 |
|
T6 |
1 |
|
T12 |
2 |
auto[0] |
values[6] |
auto[ADC_CTRL_FILTER_COND_OUT] |
195 |
1 |
|
|
T5 |
1 |
|
T11 |
15 |
|
T95 |
16 |
auto[0] |
values[7] |
auto[ADC_CTRL_FILTER_COND_IN] |
248 |
1 |
|
|
T34 |
14 |
|
T183 |
1 |
|
T93 |
12 |
auto[0] |
values[7] |
auto[ADC_CTRL_FILTER_COND_OUT] |
160 |
1 |
|
|
T45 |
8 |
|
T27 |
3 |
|
T89 |
11 |
auto[0] |
values[8] |
auto[ADC_CTRL_FILTER_COND_IN] |
148 |
1 |
|
|
T9 |
20 |
|
T95 |
11 |
|
T13 |
3 |
auto[0] |
values[8] |
auto[ADC_CTRL_FILTER_COND_OUT] |
192 |
1 |
|
|
T7 |
10 |
|
T34 |
3 |
|
T183 |
1 |
auto[0] |
values[9] |
auto[ADC_CTRL_FILTER_COND_IN] |
263 |
1 |
|
|
T89 |
7 |
|
T90 |
13 |
|
T29 |
1 |
auto[0] |
values[9] |
auto[ADC_CTRL_FILTER_COND_OUT] |
311 |
1 |
|
|
T3 |
4 |
|
T12 |
11 |
|
T124 |
19 |
auto[0] |
minimum |
auto[ADC_CTRL_FILTER_COND_IN] |
17524 |
1 |
|
|
T1 |
150 |
|
T3 |
104 |
|
T8 |
133 |
auto[1] |
maximum |
auto[ADC_CTRL_FILTER_COND_IN] |
49 |
1 |
|
|
T184 |
8 |
|
T236 |
2 |
|
T149 |
13 |
auto[1] |
maximum |
auto[ADC_CTRL_FILTER_COND_OUT] |
84 |
1 |
|
|
T11 |
12 |
|
T197 |
11 |
|
T206 |
12 |
auto[1] |
values[0] |
auto[ADC_CTRL_FILTER_COND_OUT] |
15 |
1 |
|
|
T328 |
15 |
|
- |
- |
|
- |
- |
auto[1] |
values[1] |
auto[ADC_CTRL_FILTER_COND_IN] |
147 |
1 |
|
|
T123 |
12 |
|
T122 |
6 |
|
T192 |
9 |
auto[1] |
values[1] |
auto[ADC_CTRL_FILTER_COND_OUT] |
147 |
1 |
|
|
T157 |
4 |
|
T129 |
10 |
|
T188 |
3 |
auto[1] |
values[2] |
auto[ADC_CTRL_FILTER_COND_IN] |
1346 |
1 |
|
|
T4 |
24 |
|
T7 |
10 |
|
T26 |
10 |
auto[1] |
values[2] |
auto[ADC_CTRL_FILTER_COND_OUT] |
142 |
1 |
|
|
T13 |
3 |
|
T184 |
13 |
|
T129 |
19 |
auto[1] |
values[3] |
auto[ADC_CTRL_FILTER_COND_IN] |
124 |
1 |
|
|
T210 |
12 |
|
T192 |
4 |
|
T222 |
9 |
auto[1] |
values[3] |
auto[ADC_CTRL_FILTER_COND_OUT] |
187 |
1 |
|
|
T131 |
9 |
|
T29 |
4 |
|
T244 |
14 |
auto[1] |
values[4] |
auto[ADC_CTRL_FILTER_COND_IN] |
224 |
1 |
|
|
T7 |
9 |
|
T26 |
12 |
|
T123 |
7 |
auto[1] |
values[4] |
auto[ADC_CTRL_FILTER_COND_OUT] |
114 |
1 |
|
|
T89 |
2 |
|
T223 |
10 |
|
T308 |
8 |
auto[1] |
values[5] |
auto[ADC_CTRL_FILTER_COND_IN] |
117 |
1 |
|
|
T134 |
3 |
|
T210 |
8 |
|
T276 |
12 |
auto[1] |
values[5] |
auto[ADC_CTRL_FILTER_COND_OUT] |
147 |
1 |
|
|
T22 |
4 |
|
T28 |
1 |
|
T194 |
16 |
auto[1] |
values[6] |
auto[ADC_CTRL_FILTER_COND_IN] |
185 |
1 |
|
|
T3 |
5 |
|
T6 |
12 |
|
T31 |
4 |
auto[1] |
values[6] |
auto[ADC_CTRL_FILTER_COND_OUT] |
153 |
1 |
|
|
T11 |
22 |
|
T13 |
9 |
|
T136 |
7 |
auto[1] |
values[7] |
auto[ADC_CTRL_FILTER_COND_IN] |
173 |
1 |
|
|
T34 |
4 |
|
T183 |
6 |
|
T126 |
12 |
auto[1] |
values[7] |
auto[ADC_CTRL_FILTER_COND_OUT] |
160 |
1 |
|
|
T45 |
8 |
|
T27 |
1 |
|
T89 |
11 |
auto[1] |
values[8] |
auto[ADC_CTRL_FILTER_COND_IN] |
122 |
1 |
|
|
T9 |
18 |
|
T207 |
12 |
|
T142 |
18 |
auto[1] |
values[8] |
auto[ADC_CTRL_FILTER_COND_OUT] |
133 |
1 |
|
|
T7 |
2 |
|
T34 |
8 |
|
T183 |
2 |
auto[1] |
values[9] |
auto[ADC_CTRL_FILTER_COND_IN] |
193 |
1 |
|
|
T89 |
10 |
|
T90 |
12 |
|
T14 |
1 |
auto[1] |
values[9] |
auto[ADC_CTRL_FILTER_COND_OUT] |
229 |
1 |
|
|
T3 |
1 |
|
T12 |
4 |
|
T124 |
14 |