Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T3	3		T7	22		T12	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T183	1		T82	1		T219	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T3	6		T90	13		T29	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T135	1		T129	1		T220	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T11	3		T182	4		T140	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T5	1		T9	20		T76	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1454	1			T2	11		T4	2		T6	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T5	1		T12	2		T207	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T3	4		T34	3		T13	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T132	13		T125	18		T136	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T11	12		T128	9		T95	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T5	1		T13	3		T195	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T123	1		T95	11		T202	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T25	1		T123	1		T45	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T7	1		T26	11		T131	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T26	12		T22	10		T45	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T89	3		T93	2		T95	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T11	11		T89	18		T125	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T123	1		T221	1		T222	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T187	12		T32	6		T223	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17524	1			T1	150		T3	104		T8	133
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T7	11		T12	4		T157	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T183	6		T82	2		T224	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T3	5		T90	12		T29	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T129	13		T32	1		T82	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T11	11		T140	7		T30	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T9	18		T34	4		T136	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1310	1			T4	24		T6	12		T35	26
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T207	12		T134	10		T185	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T3	1		T34	8		T182	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T136	7		T194	16		T31	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T11	11		T128	5		T203	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T13	3		T77	2		T226	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T123	12		T202	9		T210	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T123	10		T45	8		T184	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T7	10		T26	10		T131	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T26	12		T22	4		T45	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T89	2		T13	7		T184	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T11	12		T89	21		T142	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T123	7		T222	13		T231	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T187	11		T223	10		T232	8

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T216	12		T198	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T217	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T137	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T218	7		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T3	3		T7	10		T12	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T219	1		T229	1		T224	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T7	12		T13	10		T184	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T183	1		T135	1		T129	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T3	6		T90	13		T140	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T5	1		T34	14		T188	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T6	1		T11	3		T124	19
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	330	1			T9	20		T12	2		T76	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1353	1			T2	11		T4	2		T35	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T5	1		T13	1		T194	21
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T3	4		T11	12		T34	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T125	18		T136	10		T127	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T128	9		T95	27		T202	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T5	1		T25	1		T26	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T26	11		T123	1		T27	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T45	12		T89	7		T13	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T7	1		T123	1		T131	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	370	1			T11	11		T22	10		T89	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17524	1			T1	150		T3	104		T8	133
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T217	14		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T218	6		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T7	2		T12	4		T157	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T224	2		T148	4		T233	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T7	9		T13	9		T184	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T183	6		T129	13		T32	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T3	5		T90	12		T140	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T34	4		T188	3		T30	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T6	12		T11	11		T124	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T9	18		T136	12		T134	23
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1217	1			T4	24		T35	26		T163	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T13	3		T194	16		T31	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T3	1		T11	11		T34	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T136	7		T208	4		T24	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T128	5		T202	9		T134	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T26	12		T123	10		T143	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T26	10		T123	12		T27	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T45	18		T89	10		T184	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T7	10		T123	7		T131	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T11	12		T22	4		T89	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22589

1

T1

150

T2

11

T3

117

auto[1]

auto[0]

4191

1

T3

6

T4

24

T6

12