Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26780

1

T1

150

T2

11

T3

123

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22943

1

T1

150

T2

11

T3

123

auto[ADC_CTRL_FILTER_COND_OUT]

3837

1

T5

1

T6

13

T7

11

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20950

1

T1

150

T3

118

T5

1

auto[1]

5830

1

T2

11

T3

5

T4

26

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22677

1

T1

148

T2

1

T3

114

auto[1]

4103

1

T1

2

T2

10

T3

9

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	208	1			T7	12		T25	1		T95	11
values[0]	1	1			T179	1		-	-		-	-
values[1]	682	1			T3	11		T93	10		T13	37
values[2]	793	1			T3	3		T11	23		T12	15
values[3]	590	1			T7	11		T26	24		T76	1
values[4]	697	1			T5	1		T7	21		T9	38
values[5]	913	1			T76	1		T34	18		T131	10
values[6]	634	1			T5	1		T11	23		T34	11
values[7]	806	1			T11	14		T157	11		T89	17
values[8]	630	1			T12	2		T26	21		T123	8
values[9]	3302	1			T2	11		T3	5		T4	26
minimum	17524	1			T1	150		T3	104		T8	133

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	706	1			T3	14		T12	15		T89	22
values[1]	643	1			T11	23		T183	7		T90	49
values[2]	663	1			T7	32		T26	24		T76	1
values[3]	658	1			T5	1		T9	38		T124	33
values[4]	1014	1			T76	1		T34	18		T123	24
values[5]	690	1			T5	1		T11	23		T34	11
values[6]	2970	1			T2	11		T4	26		T11	14
values[7]	638	1			T3	5		T12	2		T123	8
values[8]	944	1			T5	1		T6	13		T7	12
values[9]	111	1			T95	11		T132	13		T234	1
minimum	17743	1			T1	150		T3	104		T8	133

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22589

1

T1

150

T2

11

T3

117

auto[1]

4191

1

T3

6

T4

24

T6

12

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T3	9		T89	12		T93	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T12	10		T184	16		T235	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T11	13		T183	7		T182	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T90	24		T13	1		T129	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T7	10		T26	13		T76	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T7	11		T30	12		T208	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T5	1		T9	19		T124	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T128	6		T93	1		T133	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T34	5		T123	13		T131	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	342	1			T76	1		T123	11		T202	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T34	9		T187	12		T129	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T5	1		T11	12		T89	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1539	1			T2	1		T4	26		T35	29
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T11	12		T26	11		T157	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T3	4		T12	1		T95	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T123	8		T183	3		T45	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T5	1		T7	3		T32	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	325	1			T6	13		T25	1		T45	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T95	1		T234	1		T189	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T132	1		T190	1		T197	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17469	1			T1	148		T3	101		T8	133
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T13	15		T31	7		T82	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T3	5		T89	10		T93	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T12	5		T184	16		T235	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T11	10		T182	3		T125	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T90	25		T136	14		T32	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T7	11		T26	11		T186	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T30	11		T236	13		T237	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T9	19		T124	18		T95	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T128	8		T93	11		T133	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T34	13		T22	9		T89	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T140	8		T30	7		T134	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T34	2		T187	11		T134	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T11	11		T89	6		T184	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	928	1			T2	10		T193	12		T153	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T11	2		T26	10		T157	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T3	1		T12	1		T95	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T45	3		T194	20		T14	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T7	9		T33	1		T195	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T45	7		T182	16		T136	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T95	10		T77	2		T238	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T132	12		T197	7		T213	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T1	2		T3	3		T27	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T13	8		T31	6		T239	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T7	3		T95	1		T33	7
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T25	1		T132	1		T136	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T179	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T3	7		T93	2		T13	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T13	15		T184	16		T31	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T3	2		T11	13		T183	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T12	10		T90	24		T13	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T26	13		T76	1		T182	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T7	11		T30	12		T208	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T5	1		T7	10		T9	19
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T128	6		T93	1		T13	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T34	5		T131	10		T22	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T76	1		T202	10		T29	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T34	9		T123	13		T187	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T5	1		T11	12		T123	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T203	10		T127	1		T134	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T11	12		T157	5		T89	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T12	1		T95	1		T125	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T26	11		T123	8		T183	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1632	1			T2	1		T3	4		T4	26
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	339	1			T6	13		T45	9		T182	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17408	1			T1	148		T3	101		T8	133
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T7	9		T95	10		T33	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T132	12		T136	9		T240	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T3	4		T93	8		T13	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T13	8		T184	16		T31	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T3	1		T11	10		T89	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T12	5		T90	25		T136	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T26	11		T182	3		T125	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T30	11		T200	6		T205	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T7	11		T9	19		T124	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T128	8		T93	11		T133	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T34	13		T22	9		T89	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T140	8		T30	7		T122	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T34	2		T187	11		T141	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T11	11		T184	9		T188	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T203	8		T134	8		T186	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T11	2		T157	6		T89	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T12	1		T95	15		T125	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T26	10		T45	3		T28	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1050	1			T2	10		T3	1		T193	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T45	7		T182	16		T82	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T1	2		T3	3		T27	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T3	9		T89	11		T93	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T12	11		T184	17		T235	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T11	11		T183	1		T182	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T90	27		T13	1		T129	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T7	12		T26	12		T76	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T7	1		T30	12		T208	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T5	1		T9	20		T124	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T128	9		T93	12		T133	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T34	14		T123	1		T131	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T76	1		T123	1		T202	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T34	3		T187	12		T129	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T5	1		T11	12		T89	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1261	1			T2	11		T4	2		T35	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T11	3		T26	11		T157	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T3	4		T12	2		T95	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T123	1		T183	1		T45	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T5	1		T7	10		T32	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	314	1			T6	1		T25	1		T45	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T95	11		T234	1		T189	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T132	13		T190	1		T197	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17616	1			T1	150		T3	104		T8	133
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T13	11		T31	9		T82	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T3	5		T89	11		T13	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T12	4		T184	15		T235	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T11	12		T183	6		T207	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T90	22		T129	10		T136	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T7	9		T26	12		T208	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T7	10		T30	11		T208	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T9	18		T124	14		T202	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T128	5		T133	15		T185	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T34	4		T123	12		T131	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T123	10		T202	9		T140	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T34	8		T187	11		T129	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T11	11		T89	10		T184	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1206	1			T4	24		T35	26		T163	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T11	11		T26	10		T157	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T3	1		T149	11		T222	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T123	7		T183	2		T45	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T7	2		T33	2		T208	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T6	12		T45	8		T182	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T77	2		T241	6		T212	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T197	8		T213	3		T242	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T24	11		T143	11		T19	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T13	12		T31	4		T82	2

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T7	10		T95	11		T33	6
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T25	1		T132	13		T136	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T179	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T3	6		T93	10		T13	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T13	11		T184	17		T31	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T3	3		T11	11		T183	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T12	11		T90	27		T13	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T26	12		T76	1		T182	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T7	1		T30	12		T208	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T5	1		T7	12		T9	20
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T128	9		T93	12		T13	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T34	14		T131	1		T22	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T76	1		T202	1		T29	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T34	3		T123	1		T187	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T5	1		T11	12		T123	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T203	9		T127	1		T134	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T11	3		T157	7		T89	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T12	2		T95	16		T125	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T26	11		T123	1		T183	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1418	1			T2	11		T3	4		T4	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	333	1			T6	1		T45	8		T182	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17524	1			T1	150		T3	104		T8	133
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T7	2		T33	2		T17	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T136	7		T243	3		T71	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T3	5		T13	7		T24	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T13	12		T184	15		T31	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T11	12		T183	6		T89	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T12	4		T90	22		T129	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T26	12		T208	4		T215	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T7	10		T30	11		T208	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T7	9		T9	18		T124	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T128	5		T133	15		T185	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T34	4		T131	9		T22	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T202	9		T140	7		T30	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T34	8		T123	12		T187	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T11	11		T123	10		T184	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T203	9		T134	3		T215	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T11	11		T157	4		T89	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T244	14		T210	8		T16	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T26	10		T123	7		T183	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1264	1			T3	1		T4	24		T35	26
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T6	12		T45	8		T182	15

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22589

1

T1

150

T2

11

T3

117

auto[1]

auto[0]

4191

1

T3

6

T4

24

T6

12