Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26780

1

T1

150

T2

11

T3

123

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23101

1

T1

150

T2

11

T3

123

auto[ADC_CTRL_FILTER_COND_OUT]

3679

1

T5

3

T9

38

T11

23

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20717

1

T1

150

T3

120

T5

2

auto[1]

6063

1

T2

11

T3

3

T4

26

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22677

1

T1

148

T2

1

T3

114

auto[1]

4103

1

T1

2

T2

10

T3

9

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	177	1			T232	9		T228	3		T216	12
values[0]	1	1			T245	1		-	-		-	-
values[1]	649	1			T3	3		T7	12		T12	15
values[2]	448	1			T7	21		T183	7		T13	19
values[3]	693	1			T3	11		T5	1		T34	18
values[4]	1058	1			T6	13		T9	38		T11	14
values[5]	2946	1			T2	11		T4	26		T5	1
values[6]	687	1			T3	5		T11	23		T34	11
values[7]	633	1			T5	1		T25	1		T26	24
values[8]	831	1			T26	21		T45	30		T27	4
values[9]	1133	1			T7	11		T11	23		T123	8
minimum	17524	1			T1	150		T3	104		T8	133

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	672	1			T3	3		T7	33		T12	15
values[1]	437	1			T3	11		T5	1		T90	25
values[2]	793	1			T9	38		T11	14		T76	1
values[3]	3287	1			T2	11		T4	26		T5	1
values[4]	613	1			T34	11		T13	1		T182	32
values[5]	639	1			T3	5		T5	1		T11	23
values[6]	790	1			T25	1		T26	24		T123	24
values[7]	773	1			T7	11		T26	21		T131	10
values[8]	949	1			T89	44		T93	2		T95	3
values[9]	143	1			T11	23		T123	8		T232	9
minimum	17684	1			T1	150		T3	104		T8	133

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22589

1

T1

150

T2

11

T3

117

auto[1]

4191

1

T3

6

T4

24

T6

12

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T3	2		T7	13		T12	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T183	7		T82	3		T219	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T3	7		T90	13		T13	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T5	1		T135	1		T129	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T11	12		T182	1		T140	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T9	19		T76	1		T34	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1655	1			T2	1		T4	26		T6	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	327	1			T5	1		T12	1		T207	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T34	9		T13	1		T182	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T132	1		T125	1		T136	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T3	4		T11	12		T128	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T5	1		T13	6		T195	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T123	13		T95	1		T202	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T25	1		T26	13		T123	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T7	11		T26	11		T131	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T22	5		T45	11		T13	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T89	3		T93	1		T95	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T89	23		T187	12		T125	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T123	8		T231	13		T197	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T11	13		T232	9		T246	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17455	1			T1	148		T3	101		T8	133
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T224	3		T189	1		T233	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T3	1		T7	20		T12	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T148	25		T225	2		T230	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T3	4		T90	12		T13	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T82	15		T141	11		T195	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T11	2		T182	3		T140	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T9	19		T34	13		T93	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1053	1			T2	10		T193	12		T153	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T12	1		T134	19		T185	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T34	2		T182	16		T28	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T132	12		T125	17		T136	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T3	1		T11	11		T128	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T195	2		T77	2		T226	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T95	10		T125	6		T215	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T26	11		T45	7		T184	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T26	10		T30	1		T133	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T22	9		T45	3		T14	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T89	2		T93	1		T95	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T89	16		T187	11		T125	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T197	7		T247	14		T248	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T11	10		T246	12		T21	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T1	2		T3	3		T27	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T224	7		T233	12		T144	5

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T228	3		T216	1		T231	13
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T232	9		T249	15		T21	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T245	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T3	2		T7	3		T12	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T219	1		T229	1		T224	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T7	10		T13	11		T29	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T183	7		T135	1		T129	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T3	7		T90	13		T140	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T5	1		T34	5		T136	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T6	13		T11	12		T124	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	339	1			T9	19		T12	1		T76	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1542	1			T2	1		T4	26		T35	29
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T5	1		T194	17		T29	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T3	4		T11	12		T34	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T123	11		T13	4		T125	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T123	13		T95	2		T125	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T5	1		T25	1		T26	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T26	11		T27	4		T202	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T45	20		T13	1		T184	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	293	1			T7	11		T123	8		T131	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	337	1			T11	13		T22	5		T89	23
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17408	1			T1	148		T3	101		T8	133
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T216	11		T197	7		T227	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T21	8		T250	10		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T3	1		T7	9		T12	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T224	7		T148	12		T230	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T7	11		T13	8		T29	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T82	15		T141	11		T148	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T3	4		T90	12		T140	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T34	13		T136	14		T188	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T11	2		T124	18		T90	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T9	19		T12	1		T93	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	963	1			T2	10		T193	12		T153	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T194	20		T31	6		T185	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T3	1		T11	11		T34	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T125	17		T136	9		T24	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T95	25		T125	6		T134	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T26	11		T186	9		T195	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T26	10		T30	1		T192	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T45	10		T184	13		T14	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T89	2		T93	1		T95	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T11	10		T22	9		T89	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T1	2		T3	3		T27	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T3	3		T7	22		T12	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T183	1		T82	1		T219	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T3	6		T90	13		T13	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T5	1		T135	1		T129	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T11	3		T182	4		T140	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T9	20		T76	1		T34	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1413	1			T2	11		T4	2		T6	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T5	1		T12	2		T207	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T34	3		T13	1		T182	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T132	13		T125	18		T136	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T3	4		T11	12		T128	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T5	1		T13	3		T195	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T123	1		T95	11		T202	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T25	1		T26	12		T123	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T7	1		T26	11		T131	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T22	10		T45	4		T13	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T89	3		T93	2		T95	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T89	18		T187	12		T125	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T123	1		T231	1		T197	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T11	11		T232	1		T246	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17561	1			T1	150		T3	104		T8	133
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T224	8		T189	1		T233	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T7	11		T12	4		T157	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T183	6		T82	2		T148	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T3	5		T90	12		T13	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T129	13		T32	1		T82	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T11	11		T140	7		T30	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T9	18		T34	4		T136	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1295	1			T4	24		T6	12		T35	26
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T207	12		T134	10		T185	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T34	8		T182	15		T28	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T136	7		T194	16		T31	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T3	1		T11	11		T128	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T13	3		T77	2		T226	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T123	12		T202	9		T210	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T26	12		T123	10		T45	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T7	10		T26	10		T131	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T22	4		T45	10		T14	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T89	2		T13	7		T184	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T89	21		T187	11		T223	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T123	7		T231	12		T197	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T11	12		T232	8		T21	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T251	7		T249	9		T75	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T224	2		T233	12		T144	6

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T228	1		T216	12		T231	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T232	1		T249	1		T21	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T245	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T3	3		T7	10		T12	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T219	1		T229	1		T224	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T7	12		T13	10		T29	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T183	1		T135	1		T129	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T3	6		T90	13		T140	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T5	1		T34	14		T136	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T6	1		T11	3		T124	19
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	318	1			T9	20		T12	2		T76	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1311	1			T2	11		T4	2		T35	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T5	1		T194	21		T29	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T3	4		T11	12		T34	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T123	1		T13	1		T125	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T123	1		T95	27		T125	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T5	1		T25	1		T26	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T26	11		T27	3		T202	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T45	12		T13	1		T184	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T7	1		T123	1		T131	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	342	1			T11	11		T22	10		T89	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17524	1			T1	150		T3	104		T8	133
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T228	2		T231	12		T197	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T232	8		T249	14		T21	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T7	2		T12	4		T157	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T224	2		T148	4		T252	21
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T7	9		T13	9		T29	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T183	6		T129	13		T32	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T3	5		T90	12		T140	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T34	4		T136	12		T188	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T6	12		T11	11		T124	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T9	18		T207	12		T33	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1194	1			T4	24		T35	26		T163	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T194	16		T31	4		T185	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T3	1		T11	11		T34	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T123	10		T13	3		T136	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T123	12		T134	3		T210	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T26	12		T253	13		T143	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T26	10		T27	1		T202	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T45	18		T184	8		T14	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T7	10		T123	7		T131	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T11	12		T22	4		T89	21

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22589

1

T1

150

T2

11

T3

117

auto[1]

auto[0]

4191

1

T3

6

T4

24

T6

12