Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26780

1

T1

150

T2

11

T3

123

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23081

1

T1

150

T2

11

T3

107

auto[ADC_CTRL_FILTER_COND_OUT]

3699

1

T3

16

T5

2

T7

32

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20786

1

T1

150

T3

112

T5

1

auto[1]

5994

1

T2

11

T3

11

T4

26

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22677

1

T1

148

T2

1

T3

114

auto[1]

4103

1

T1

2

T2

10

T3

9

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	37	1			T162	1		T254	12		T255	1
values[0]	78	1			T220	1		T30	2		T134	30
values[1]	628	1			T3	5		T5	1		T26	24
values[2]	701	1			T5	1		T9	38		T157	11
values[3]	948	1			T123	13		T183	7		T45	14
values[4]	768	1			T3	14		T12	15		T76	1
values[5]	3036	1			T2	11		T4	26		T11	37
values[6]	504	1			T12	2		T34	11		T186	22
values[7]	840	1			T7	21		T11	23		T123	8
values[8]	541	1			T5	1		T7	23		T128	14
values[9]	1175	1			T6	13		T26	21		T76	1
minimum	17524	1			T1	150		T3	104		T8	133

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	985	1			T3	5		T5	2		T9	38
values[1]	716	1			T157	11		T183	3		T27	4
values[2]	819	1			T3	3		T123	13		T183	7
values[3]	3027	1			T2	11		T3	11		T4	26
values[4]	689	1			T11	23		T12	2		T25	1
values[5]	748	1			T34	11		T93	12		T184	22
values[6]	688	1			T5	1		T7	32		T11	23
values[7]	538	1			T7	12		T128	14		T89	17
values[8]	826	1			T6	13		T26	21		T76	1
values[9]	220	1			T184	23		T15	6		T256	1
minimum	17524	1			T1	150		T3	104		T8	133

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22589

1

T1

150

T2

11

T3

117

auto[1]

4191

1

T3

6

T4

24

T6

12

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T5	1		T9	19		T26	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T3	4		T5	1		T34	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T27	4		T182	16		T125	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T157	5		T183	3		T90	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T3	2		T45	9		T129	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T123	13		T183	7		T45	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1603	1			T2	1		T4	26		T11	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T3	7		T12	10		T22	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T11	13		T25	1		T93	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T12	1		T76	1		T131	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T34	9		T184	9		T134	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T93	1		T30	8		T33	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T132	1		T133	16		T126	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T5	1		T7	21		T11	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T7	3		T128	6		T89	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T93	1		T31	7		T221	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T6	13		T26	11		T220	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T76	1		T124	15		T202	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T184	14		T15	4		T256	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T167	1		T68	10		T257	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17408	1			T1	148		T3	101		T8	133
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T9	19		T26	11		T95	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T3	1		T34	13		T13	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T182	16		T125	6		T134	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T157	6		T90	13		T187	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T3	1		T45	7		T140	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T45	3		T182	3		T32	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1028	1			T2	10		T11	2		T193	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T3	4		T12	5		T22	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T11	10		T93	7		T95	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T12	1		T95	15		T136	23
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T34	2		T184	13		T134	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T93	11		T30	7		T33	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T132	12		T133	4		T244	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T7	11		T11	11		T13	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T7	9		T128	8		T89	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T93	1		T31	6		T258	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T26	10		T148	12		T230	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T124	18		T125	17		T259	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T184	9		T15	2		T246	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T68	10		T250	10		T260	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T1	2		T3	3		T27	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T162	1		T254	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T255	1		T261	12		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T30	1		T134	11		T143	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T220	1		T262	15		T263	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T26	13		T95	1		T13	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T3	4		T5	1		T34	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T5	1		T9	19		T134	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T157	5		T183	3		T202	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T27	4		T182	16		T125	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	308	1			T123	13		T183	7		T45	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T3	2		T45	9		T203	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T3	7		T12	10		T76	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1651	1			T2	1		T4	26		T11	25
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T22	5		T95	1		T136	21
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T34	9		T186	2		T209	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T12	1		T122	3		T264	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T184	9		T132	1		T133	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T7	10		T11	12		T123	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T7	3		T128	6		T89	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T5	1		T7	11		T93	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	321	1			T6	13		T26	11		T90	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	347	1			T76	1		T124	15		T202	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17408	1			T1	148		T3	101		T8	133
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T254	11		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T261	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T30	1		T134	19		T143	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T262	19		T263	1		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T26	11		T95	2		T265	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T3	1		T34	13		T13	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T9	19		T134	13		T195	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T157	6		T187	11		T188	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T182	16		T125	6		T140	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T45	3		T90	13		T32	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T3	1		T45	7		T203	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T3	4		T12	5		T89	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1015	1			T2	10		T11	12		T193	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T22	9		T95	15		T136	23
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T34	2		T186	20		T174	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T12	1		T122	1		T264	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T184	13		T132	12		T133	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T7	11		T11	11		T93	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T7	9		T128	8		T89	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T93	1		T13	8		T31	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T26	10		T90	12		T184	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T124	18		T125	17		T259	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T1	2		T3	3		T27	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T5	1		T9	20		T26	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	340	1			T3	4		T5	1		T34	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T27	3		T182	17		T125	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T157	7		T183	1		T90	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T3	3		T45	8		T129	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T123	1		T183	1		T45	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1367	1			T2	11		T4	2		T11	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T3	6		T12	11		T22	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T11	11		T25	1		T93	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T12	2		T76	1		T131	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T34	3		T184	14		T134	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T93	12		T30	12		T33	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T132	13		T133	5		T126	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T5	1		T7	13		T11	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T7	10		T128	9		T89	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T93	2		T31	9		T221	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T6	1		T26	11		T220	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T76	1		T124	19		T202	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T184	10		T15	5		T256	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T167	1		T68	14		T257	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17524	1			T1	150		T3	104		T8	133
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T9	18		T26	12		T134	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T3	1		T34	4		T123	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T27	1		T182	15		T134	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T157	4		T183	2		T90	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T45	8		T129	13		T140	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T123	12		T183	6		T45	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1264	1			T4	24		T11	11		T35	26
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T3	5		T12	4		T22	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T11	12		T266	4		T205	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T131	9		T136	19		T30	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T34	8		T184	8		T134	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T30	3		T33	2		T208	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T133	15		T244	14		T122	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T7	19		T11	11		T123	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T7	2		T128	5		T89	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T31	4		T267	7		T222	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T6	12		T26	10		T32	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T124	14		T202	10		T82	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T184	13		T15	1		T268	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T68	6		T257	17		T269	13

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T162	1		T254	12		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T255	1		T261	12		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T30	2		T134	20		T143	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T220	1		T262	20		T263	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T26	12		T95	3		T13	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T3	4		T5	1		T34	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T5	1		T9	20		T134	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T157	7		T183	1		T202	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T27	3		T182	17		T125	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T123	1		T183	1		T45	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T3	3		T45	8		T203	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T3	6		T12	11		T76	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1362	1			T2	11		T4	2		T11	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T22	10		T95	16		T136	25
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T34	3		T186	22		T209	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T12	2		T122	3		T264	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T184	14		T132	13		T133	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T7	12		T11	12		T123	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T7	10		T128	9		T89	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T5	1		T7	1		T93	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	309	1			T6	1		T26	11		T90	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	342	1			T76	1		T124	19		T202	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17524	1			T1	150		T3	104		T8	133
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T261	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T134	10		T143	4		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T262	14		T263	1		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T26	12		T223	10		T253	22
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T3	1		T34	4		T123	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T9	18		T134	13		T264	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T157	4		T183	2		T202	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T27	1		T182	15		T129	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T123	12		T183	6		T45	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T45	8		T203	9		T192	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T3	5		T12	4		T131	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1304	1			T4	24		T11	23		T35	26
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T22	4		T136	19		T28	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T34	8		T174	15		T270	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T122	1		T264	12		T233	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T184	8		T133	15		T244	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T7	9		T11	11		T123	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T7	2		T128	5		T89	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T7	10		T13	12		T31	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T6	12		T26	10		T90	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T124	14		T202	10		T82	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22589

1

T1

150

T2

11

T3

117

auto[1]

auto[0]

4191

1

T3

6

T4

24

T6

12