Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26780

1

T1

150

T2

11

T3

123

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23051

1

T1

150

T2

11

T3

104

auto[ADC_CTRL_FILTER_COND_OUT]

3729

1

T3

19

T5

1

T6

13

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20689

1

T1

150

T3

112

T6

13

auto[1]

6091

1

T2

11

T3

11

T4

26

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22677

1

T1

148

T2

1

T3

114

auto[1]

4103

1

T1

2

T2

10

T3

9

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	296	1			T6	13		T26	21		T184	23
values[0]	2	1			T30	2		-	-		-	-
values[1]	721	1			T3	5		T5	1		T26	24
values[2]	736	1			T5	1		T9	38		T157	11
values[3]	877	1			T123	13		T183	7		T45	14
values[4]	793	1			T3	14		T12	15		T76	1
values[5]	2978	1			T2	11		T4	26		T11	37
values[6]	574	1			T12	2		T34	11		T136	17
values[7]	860	1			T7	21		T11	23		T123	8
values[8]	521	1			T5	1		T7	23		T128	14
values[9]	898	1			T76	1		T124	33		T90	25
minimum	17524	1			T1	150		T3	104		T8	133

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	876	1			T3	5		T5	2		T9	38
values[1]	673	1			T157	11		T183	3		T27	4
values[2]	805	1			T3	3		T123	13		T183	7
values[3]	3112	1			T2	11		T3	11		T4	26
values[4]	606	1			T11	23		T12	2		T25	1
values[5]	741	1			T34	11		T184	22		T30	15
values[6]	724	1			T5	1		T7	32		T11	23
values[7]	478	1			T7	12		T128	14		T89	17
values[8]	960	1			T6	13		T26	21		T76	1
values[9]	130	1			T184	23		T15	6		T271	1
minimum	17675	1			T1	150		T3	104		T8	133

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22589

1

T1

150

T2

11

T3

117

auto[1]

4191

1

T3

6

T4

24

T6

12

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T5	2		T13	9		T234	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T3	4		T9	19		T26	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T27	4		T182	16		T125	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T157	5		T183	3		T90	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T183	7		T45	9		T129	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T3	2		T123	13		T45	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1649	1			T2	1		T4	26		T11	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T3	7		T12	10		T76	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T11	13		T25	1		T93	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T12	1		T95	1		T136	21
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T34	9		T184	9		T244	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T30	8		T33	7		T122	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T13	13		T132	1		T133	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T5	1		T7	21		T11	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T7	3		T128	6		T89	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T31	7		T208	15		T221	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T90	13		T220	1		T159	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T6	13		T26	11		T76	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T184	14		T15	4		T256	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T271	1		T167	1		T268	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17459	1			T1	148		T3	101		T8	133
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T95	1		T220	1		T134	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T13	6		T265	2		T142	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T3	1		T9	19		T26	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T182	16		T125	6		T134	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T157	6		T90	13		T187	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T45	7		T140	8		T195	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T3	1		T45	3		T182	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1059	1			T2	10		T11	2		T193	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T3	4		T12	5		T22	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T11	10		T93	7		T95	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T12	1		T95	15		T136	23
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T34	2		T184	13		T244	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T30	7		T33	1		T122	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T13	8		T132	12		T133	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T7	11		T11	11		T93	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T7	9		T128	8		T89	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T31	6		T215	12		T258	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T90	12		T230	14		T266	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T26	10		T124	18		T125	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T184	9		T15	2		T272	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T269	17		T273	12		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T1	2		T3	3		T27	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T95	2		T134	19		T274	9

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T184	14		T159	1		T140	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T6	13		T26	11		T135	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T30	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T5	1		T13	9		T138	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T3	4		T26	13		T34	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T5	1		T134	14		T264	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T9	19		T157	5		T183	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T183	7		T27	4		T182	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T123	13		T45	11		T90	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T45	9		T127	1		T229	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T3	9		T12	10		T76	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1616	1			T2	1		T4	26		T11	25
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T22	5		T95	1		T136	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T34	9		T134	4		T186	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T12	1		T136	8		T122	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T184	9		T132	1		T133	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T7	10		T11	12		T123	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T7	3		T128	6		T89	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T5	1		T7	11		T13	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T90	13		T220	1		T82	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T76	1		T124	15		T202	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17408	1			T1	148		T3	101		T8	133
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T184	9		T15	2		T222	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T26	10		T259	1		T228	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T30	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T13	6		T265	2		T143	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T3	1		T26	11		T34	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T134	13		T264	10		T142	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T9	19		T157	6		T187	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T182	16		T125	6		T140	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T45	3		T90	13		T32	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T45	7		T229	2		T141	20
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T3	5		T12	5		T89	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	975	1			T2	10		T11	12		T193	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T22	9		T95	15		T136	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T34	2		T134	8		T186	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T12	1		T136	9		T122	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T184	13		T132	12		T133	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T7	11		T11	11		T93	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T7	9		T128	8		T89	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T31	6		T215	12		T258	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T90	12		T230	14		T266	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T124	18		T125	17		T148	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T1	2		T3	3		T27	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T5	2		T13	8		T234	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	340	1			T3	4		T9	20		T26	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T27	3		T182	17		T125	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T157	7		T183	1		T90	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T183	1		T45	8		T129	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T3	3		T123	1		T45	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1406	1			T2	11		T4	2		T11	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T3	6		T12	11		T76	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T11	11		T25	1		T93	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T12	2		T95	16		T136	25
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T34	3		T184	14		T244	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T30	12		T33	6		T122	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T13	12		T132	13		T133	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T5	1		T7	13		T11	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T7	10		T128	9		T89	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T31	9		T208	1		T221	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T90	13		T220	1		T159	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T6	1		T26	11		T76	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T184	10		T15	5		T256	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T271	1		T167	1		T268	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17559	1			T1	150		T3	104		T8	133
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T95	3		T220	1		T134	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T13	7		T142	18		T205	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T3	1		T9	18		T26	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T27	1		T182	15		T134	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T157	4		T183	2		T90	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T183	6		T45	8		T129	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T123	12		T45	10		T129	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1302	1			T4	24		T11	11		T35	26
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T3	5		T12	4		T22	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T11	12		T266	4		T205	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T136	19		T28	1		T30	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T34	8		T184	8		T244	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T30	3		T33	2		T122	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T13	9		T133	15		T122	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T7	19		T11	11		T123	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T7	2		T128	5		T89	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T31	4		T208	14		T215	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T90	12		T32	1		T82	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T6	12		T26	10		T124	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T184	13		T15	1		T275	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T268	3		T257	17		T269	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T223	10		T233	7		T251	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T134	10		T228	2		T274	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T184	10		T159	1		T140	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T6	1		T26	11		T135	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T30	2		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T5	1		T13	8		T138	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T3	4		T26	12		T34	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T5	1		T134	14		T264	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T9	20		T157	7		T183	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T183	1		T27	3		T182	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T123	1		T45	4		T90	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T45	8		T127	1		T229	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T3	9		T12	11		T76	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1318	1			T2	11		T4	2		T11	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T22	10		T95	16		T136	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T34	3		T134	9		T186	22
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T12	2		T136	10		T122	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T184	14		T132	13		T133	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T7	12		T11	12		T123	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T7	10		T128	9		T89	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T5	1		T7	1		T13	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T90	13		T220	1		T82	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T76	1		T124	19		T202	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17524	1			T1	150		T3	104		T8	133
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T184	13		T32	1		T15	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T6	12		T26	10		T228	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T13	7		T223	10		T233	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T3	1		T26	12		T34	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T134	13		T264	15		T142	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T9	18		T157	4		T183	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T183	6		T27	1		T182	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T123	12		T45	10		T90	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T45	8		T192	4		T148	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T3	5		T12	4		T89	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1273	1			T4	24		T11	23		T35	26
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T22	4		T136	12		T28	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T34	8		T134	3		T174	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T136	7		T122	1		T264	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T184	8		T133	15		T244	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T7	9		T11	11		T123	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T7	2		T128	5		T89	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T7	10		T13	3		T31	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T90	12		T82	2		T276	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T124	14		T202	10		T207	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22589

1

T1

150

T2

11

T3

117

auto[1]

auto[0]

4191

1

T3

6

T4

24

T6

12