Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26780

1

T1

150

T2

11

T3

123

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23355

1

T1

150

T2

11

T3

120

auto[ADC_CTRL_FILTER_COND_OUT]

3425

1

T3

3

T5

3

T6

13

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20718

1

T1

150

T3

109

T5

2

auto[1]

6062

1

T2

11

T3

14

T4

26

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22677

1

T1

148

T2

1

T3

114

auto[1]

4103

1

T1

2

T2

10

T3

9

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	282	1			T5	1		T184	32		T188	7
values[0]	77	1			T129	11		T136	27		T207	13
values[1]	875	1			T3	5		T11	14		T124	33
values[2]	537	1			T5	1		T183	7		T45	14
values[3]	608	1			T3	11		T5	1		T9	38
values[4]	680	1			T7	12		T12	15		T25	1
values[5]	796	1			T6	13		T7	21		T131	10
values[6]	804	1			T11	23		T123	11		T27	4
values[7]	662	1			T76	1		T123	8		T202	11
values[8]	2949	1			T2	11		T3	3		T4	26
values[9]	986	1			T7	11		T26	24		T123	13
minimum	17524	1			T1	150		T3	104		T8	133

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	766	1			T3	5		T124	33		T95	3
values[1]	492	1			T5	1		T183	7		T45	14
values[2]	732	1			T3	11		T5	1		T9	38
values[3]	594	1			T12	15		T25	1		T76	1
values[4]	961	1			T6	13		T7	33		T11	23
values[5]	706	1			T123	11		T27	4		T95	16
values[6]	2854	1			T2	11		T3	3		T4	26
values[7]	679	1			T11	23		T123	13		T128	14
values[8]	940	1			T5	1		T7	11		T26	24
values[9]	194	1			T188	7		T29	1		T140	1
minimum	17862	1			T1	150		T3	104		T8	133

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22589

1

T1

150

T2

11

T3

117

auto[1]

4191

1

T3

6

T4

24

T6

12

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T3	4		T124	15		T229	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T95	1		T187	12		T136	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T125	1		T32	2		T162	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T5	1		T183	7		T45	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T3	7		T9	19		T12	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T5	1		T95	1		T13	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T25	1		T34	9		T131	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T12	10		T76	1		T157	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T7	3		T90	11		T13	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	304	1			T6	13		T7	10		T11	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T123	11		T27	4		T182	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T95	1		T13	11		T29	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1649	1			T2	1		T4	26		T26	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T3	2		T183	3		T202	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T45	9		T93	1		T184	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T11	12		T123	13		T128	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	305	1			T26	13		T89	11		T13	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T5	1		T7	11		T90	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T188	4		T29	1		T122	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T140	1		T138	1		T209	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17471	1			T1	148		T3	101		T8	133
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T11	12		T125	1		T129	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T3	1		T124	18		T186	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T95	2		T187	11		T136	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T125	6		T32	1		T205	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T45	3		T89	2		T125	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T3	4		T9	19		T12	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T95	10		T13	6		T203	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T34	2		T22	9		T184	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T12	5		T157	6		T138	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T7	9		T90	13		T132	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T7	11		T11	10		T93	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T182	16		T134	8		T186	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T95	15		T13	8		T31	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	982	1			T2	10		T26	10		T193	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T3	1		T14	2		T141	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T45	7		T93	1		T184	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T11	11		T128	8		T93	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T26	11		T89	6		T184	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T90	12		T229	2		T161	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T188	3		T122	1		T277	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T209	9		T222	7		T278	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T1	2		T3	3		T27	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T11	2		T125	17		T200	6

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T184	16		T188	4		T194	17
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T5	1		T140	1		T234	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T129	11		T136	13		T207	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T3	4		T124	15		T229	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T11	12		T95	1		T187	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T125	1		T32	2		T221	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T5	1		T183	7		T45	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T3	7		T9	19		T12	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T5	1		T95	1		T13	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T7	3		T25	1		T34	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T12	10		T76	1		T138	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T131	10		T22	5		T184	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T6	13		T7	10		T157	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T123	11		T27	4		T90	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T11	13		T95	1		T29	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T76	1		T123	8		T13	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T202	11		T13	11		T220	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1576	1			T2	1		T4	26		T26	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T3	2		T11	12		T183	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T26	13		T89	11		T93	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T7	11		T123	13		T128	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17408	1			T1	148		T3	101		T8	133
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T184	16		T188	3		T194	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T222	7		T279	1		T206	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T136	14		T280	12		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T3	1		T124	18		T186	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T11	2		T95	2		T187	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T125	6		T32	1		T228	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T45	3		T89	2		T136	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T3	4		T9	19		T12	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T95	10		T13	6		T125	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T7	9		T34	2		T29	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T12	5		T138	8		T281	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T22	9		T184	13		T140	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T7	11		T157	6		T93	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T90	13		T182	16		T132	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T11	10		T95	15		T31	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T182	3		T30	7		T134	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T13	8		T14	2		T141	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1014	1			T2	10		T26	10		T193	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T3	1		T11	11		T122	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T26	11		T89	6		T93	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T128	8		T90	12		T93	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T1	2		T3	3		T27	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T3	4		T124	19		T229	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T95	3		T187	12		T136	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T125	7		T32	2		T162	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T5	1		T183	1		T45	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T3	6		T9	20		T12	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T5	1		T95	11		T13	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T25	1		T34	3		T131	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T12	11		T76	1		T157	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T7	10		T90	14		T13	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	311	1			T6	1		T7	12		T11	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T123	1		T27	3		T182	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T95	16		T13	10		T29	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1331	1			T2	11		T4	2		T26	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T3	3		T183	1		T202	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T45	8		T93	2		T184	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T11	12		T123	1		T128	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T26	12		T89	7		T13	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T5	1		T7	1		T90	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T188	4		T29	1		T122	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T140	1		T138	1		T209	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17626	1			T1	150		T3	104		T8	133
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T11	3		T125	18		T129	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T3	1		T124	14		T270	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T187	11		T136	12		T207	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T32	1		T205	13		T282	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T183	6		T45	10		T89	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T3	5		T9	18		T34	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T13	7		T203	9		T264	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T34	8		T131	9		T22	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T12	4		T157	4		T232	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T7	2		T90	10		T140	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T6	12		T7	9		T11	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T123	10		T27	1		T182	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T13	9		T31	4		T133	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1300	1			T4	24		T26	10		T35	26
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T183	2		T202	10		T14	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T45	8		T184	13		T129	19
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T11	11		T123	12		T128	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T26	12		T89	10		T184	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T7	10		T90	12		T32	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T188	3		T122	1		T253	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T209	11		T222	8		T278	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T143	12		T283	25		T284	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T11	11		T129	10		T149	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T184	17		T188	4		T194	21
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T5	1		T140	1		T234	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T129	1		T136	15		T207	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T3	4		T124	19		T229	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T11	3		T95	3		T187	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T125	7		T32	2		T221	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T5	1		T183	1		T45	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T3	6		T9	20		T12	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T5	1		T95	11		T13	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T7	10		T25	1		T34	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T12	11		T76	1		T138	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T131	1		T22	10		T184	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T6	1		T7	12		T157	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T123	1		T27	3		T90	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T11	11		T95	16		T29	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T76	1		T123	1		T13	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T202	1		T13	10		T220	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1351	1			T2	11		T4	2		T26	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T3	3		T11	12		T183	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T26	12		T89	7		T93	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T7	1		T123	1		T128	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17524	1			T1	150		T3	104		T8	133
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T184	15		T188	3		T194	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T222	8		T206	12		T285	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T129	10		T136	12		T207	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T3	1		T124	14		T270	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T11	11		T187	11		T134	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T32	1		T228	7		T240	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T183	6		T45	10		T89	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T3	5		T9	18		T34	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T13	7		T203	9		T192	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T7	2		T34	8		T29	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T12	4		T232	8		T24	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T131	9		T22	4		T184	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T6	12		T7	9		T157	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T123	10		T27	1		T90	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T11	12		T31	4		T82	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T123	7		T13	3		T30	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T202	10		T13	9		T14	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1239	1			T4	24		T26	10		T35	26
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T11	11		T183	2		T122	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T26	12		T89	10		T208	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T7	10		T123	12		T128	5

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22589

1

T1

150

T2

11

T3

117

auto[1]

auto[0]

4191

1

T3

6

T4

24

T6

12