Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26780

1

T1

150

T2

11

T3

123

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23017

1

T1

150

T2

11

T3

123

auto[ADC_CTRL_FILTER_COND_OUT]

3763

1

T5

2

T6

13

T7

21

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20729

1

T1

150

T3

109

T5

1

auto[1]

6051

1

T2

11

T3

14

T4

26

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22677

1

T1

148

T2

1

T3

114

auto[1]

4103

1

T1

2

T2

10

T3

9

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	276	1			T76	1		T90	25		T93	12
values[0]	21	1			T26	21		-	-		-	-
values[1]	822	1			T7	21		T93	8		T95	16
values[2]	970	1			T5	2		T11	46		T12	2
values[3]	607	1			T7	11		T9	38		T123	8
values[4]	2925	1			T2	11		T4	26		T26	24
values[5]	697	1			T5	1		T123	13		T183	10
values[6]	721	1			T3	3		T25	1		T131	10
values[7]	670	1			T11	14		T76	1		T123	11
values[8]	584	1			T3	5		T6	13		T12	15
values[9]	963	1			T3	11		T7	12		T125	7
minimum	17524	1			T1	150		T3	104		T8	133

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	769	1			T5	2		T157	11		T93	8
values[1]	858	1			T11	46		T12	2		T34	18
values[2]	544	1			T7	11		T9	38		T26	24
values[3]	3011	1			T2	11		T4	26		T35	29
values[4]	699	1			T5	1		T123	13		T183	10
values[5]	717	1			T3	3		T25	1		T131	10
values[6]	702	1			T11	14		T76	1		T123	11
values[7]	645	1			T3	16		T6	13		T7	12
values[8]	882	1			T90	25		T93	12		T13	14
values[9]	95	1			T76	1		T187	23		T13	19
minimum	17858	1			T1	150		T3	104		T7	21

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22589

1

T1

150

T2

11

T3

117

auto[1]

4191

1

T3

6

T4

24

T6

12

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T5	1		T157	5		T93	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T5	1		T182	16		T32	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T12	1		T182	1		T125	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T11	25		T34	5		T129	20
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T7	11		T9	19		T45	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T26	13		T123	8		T202	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1631	1			T2	1		T4	26		T35	29
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T89	12		T13	1		T203	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T123	13		T183	3		T89	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T5	1		T183	7		T22	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T3	2		T93	1		T202	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T25	1		T131	10		T184	23
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T123	11		T124	15		T13	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T11	12		T76	1		T128	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T3	11		T7	3		T12	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T6	13		T34	9		T215	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T90	13		T132	1		T125	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T93	1		T13	8		T188	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T76	1		T187	12		T286	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T13	11		T271	1		T166	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17505	1			T1	148		T3	101		T8	133
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T7	10		T160	1		T127	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T157	6		T93	7		T95	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T182	16		T264	7		T148	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T12	1		T182	3		T125	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T11	21		T34	13		T264	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T9	19		T45	7		T89	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T26	11		T32	4		T122	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1054	1			T2	10		T193	12		T153	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T89	10		T203	8		T141	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T89	6		T90	13		T95	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T22	9		T45	3		T125	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T3	1		T93	1		T235	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T184	22		T136	14		T29	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T124	18		T184	16		T30	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T11	2		T128	8		T30	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T3	5		T7	9		T12	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T34	2		T215	13		T230	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T90	12		T132	12		T125	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T93	11		T13	6		T188	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T187	11		T287	5		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T13	8		T288	19		T289	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T1	2		T3	3		T26	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T7	11		T167	9		T180	20

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T76	1		T90	13		T187	12
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T93	1		T13	19		T290	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T26	11		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T93	1		T95	1		T194	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T7	10		T182	16		T160	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T5	1		T12	1		T157	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	325	1			T5	1		T11	25		T34	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T7	11		T9	19		T45	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T123	8		T202	11		T122	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1615	1			T2	1		T4	26		T35	29
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T26	13		T89	12		T13	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T123	13		T183	3		T90	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T5	1		T183	7		T22	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T3	2		T89	11		T93	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T25	1		T131	10		T129	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T123	11		T124	15		T202	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T11	12		T76	1		T128	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T3	4		T12	10		T27	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T6	13		T34	9		T141	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T3	7		T7	3		T125	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T188	4		T159	1		T29	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17408	1			T1	148		T3	101		T8	133
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T90	12		T187	11		T132	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T93	11		T13	14		T226	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T26	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T93	7		T95	15		T194	20
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T7	11		T182	16		T264	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T12	1		T157	6		T95	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T11	21		T34	13		T264	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T9	19		T45	7		T89	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T122	1		T148	10		T205	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1034	1			T2	10		T193	12		T153	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T26	11		T89	10		T203	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T90	13		T95	10		T134	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T22	9		T45	3		T125	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T3	1		T89	6		T93	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T136	14		T33	1		T185	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T124	18		T184	16		T30	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T11	2		T128	8		T184	22
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T3	1		T12	5		T32	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T34	2		T141	9		T215	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T3	4		T7	9		T125	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T188	3		T122	1		T209	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T1	2		T3	3		T27	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T5	1		T157	7		T93	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T5	1		T182	17		T32	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T12	2		T182	4		T125	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T11	23		T34	14		T129	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T7	1		T9	20		T45	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T26	12		T123	1		T202	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1409	1			T2	11		T4	2		T35	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T89	11		T13	1		T203	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T123	1		T183	1		T89	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T5	1		T183	1		T22	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T3	3		T93	2		T202	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T25	1		T131	1		T184	24
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T123	1		T124	19		T13	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T11	3		T76	1		T128	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T3	10		T7	10		T12	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T6	1		T34	3		T215	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T90	13		T132	13		T125	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	314	1			T93	12		T13	7		T188	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T76	1		T187	12		T286	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T13	10		T271	1		T166	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17628	1			T1	150		T3	104		T8	133
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T7	12		T160	1		T127	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T157	4		T194	16		T191	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T182	15		T32	1		T264	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T140	7		T133	15		T208	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T11	23		T34	4		T129	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T7	10		T9	18		T45	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T26	12		T123	7		T202	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1276	1			T4	24		T35	26		T163	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T89	11		T203	9		T126	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T123	12		T183	2		T89	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T183	6		T22	4		T45	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T202	9		T208	4		T235	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T131	9		T184	21		T129	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T123	10		T124	14		T184	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T11	11		T128	5		T30	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T3	6		T7	2		T12	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T6	12		T34	8		T215	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T90	12		T31	4		T223	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T13	7		T188	3		T207	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T187	11		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T13	9		T288	16		T289	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T26	10		T192	9		T236	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T7	9		T291	10		T167	5

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T76	1		T90	13		T187	12
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T93	12		T13	17		T290	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T26	11		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T93	8		T95	16		T194	21
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T7	12		T182	17		T160	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T5	1		T12	2		T157	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T5	1		T11	23		T34	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T7	1		T9	20		T45	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T123	1		T202	1		T122	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1384	1			T2	11		T4	2		T35	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T26	12		T89	11		T13	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T123	1		T183	1		T90	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T5	1		T183	1		T22	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T3	3		T89	7		T93	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T25	1		T131	1		T129	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T123	1		T124	19		T202	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T11	3		T76	1		T128	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T3	4		T12	11		T27	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T6	1		T34	3		T141	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T3	6		T7	10		T125	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T188	4		T159	1		T29	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17524	1			T1	150		T3	104		T8	133
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T90	12		T187	11		T292	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T13	16		T226	9		T293	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T26	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T194	16		T192	9		T236	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T7	9		T182	15		T32	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T157	4		T140	7		T133	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T11	23		T34	4		T129	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T7	10		T9	18		T45	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T123	7		T202	10		T122	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1265	1			T4	24		T35	26		T163	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T26	12		T89	11		T203	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T123	12		T183	2		T90	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T183	6		T22	4		T45	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T89	10		T208	4		T235	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T131	9		T129	10		T136	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T123	10		T124	14		T202	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T11	11		T128	5		T184	21
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T3	1		T12	4		T27	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T6	12		T34	8		T210	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T3	5		T7	2		T31	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T188	3		T207	12		T122	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22589

1

T1

150

T2

11

T3

117

auto[1]

auto[0]

4191

1

T3

6

T4

24

T6

12