Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26780

1

T1

150

T2

11

T3

123

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20884

1

T1

150

T3

123

T5

2

auto[ADC_CTRL_FILTER_COND_OUT]

5896

1

T2

11

T4

26

T5

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20752

1

T1

150

T3

115

T5

2

auto[1]

6028

1

T2

11

T3

8

T4

26

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22677

1

T1

148

T2

1

T3

114

auto[1]

4103

1

T1

2

T2

10

T3

9

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	269	1			T76	1		T183	7		T93	12
values[0]	44	1			T141	12		T211	12		T271	1
values[1]	628	1			T5	1		T26	24		T89	22
values[2]	670	1			T6	13		T123	13		T124	33
values[3]	701	1			T3	11		T11	37		T12	2
values[4]	760	1			T5	1		T7	11		T90	25
values[5]	612	1			T3	3		T7	21		T12	15
values[6]	740	1			T11	23		T123	8		T128	14
values[7]	851	1			T3	5		T9	38		T25	1
values[8]	633	1			T5	1		T34	29		T183	3
values[9]	3348	1			T2	11		T4	26		T7	12
minimum	17524	1			T1	150		T3	104		T8	133

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	755	1			T6	13		T26	24		T89	22
values[1]	2843	1			T2	11		T3	11		T4	26
values[2]	718	1			T7	11		T11	14		T12	2
values[3]	738	1			T5	1		T12	15		T22	14
values[4]	589	1			T3	3		T7	21		T11	23
values[5]	793	1			T25	1		T76	1		T123	8
values[6]	746	1			T3	5		T5	1		T9	38
values[7]	686	1			T7	12		T34	29		T183	3
values[8]	1053	1			T76	1		T157	11		T90	24
values[9]	152	1			T123	11		T183	7		T93	12
minimum	17707	1			T1	150		T3	104		T5	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22589

1

T1

150

T2

11

T3

117

auto[1]

4191

1

T3

6

T4

24

T6

12

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T26	13		T89	12		T182	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T6	13		T187	12		T125	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T3	7		T89	3		T184	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1566	1			T2	1		T4	26		T11	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T12	1		T90	13		T184	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T7	11		T11	12		T89	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T22	5		T32	2		T82	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T5	1		T12	10		T93	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T3	2		T7	10		T131	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T11	12		T27	4		T220	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T25	1		T76	1		T45	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T123	8		T128	6		T13	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T3	4		T5	1		T26	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T9	19		T95	1		T132	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T34	5		T183	3		T93	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T7	3		T34	9		T45	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T76	1		T95	1		T202	21
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T157	5		T90	11		T13	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T13	4		T294	1		T197	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T123	11		T183	7		T93	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17461	1			T1	148		T3	101		T5	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T136	8		T141	1		T211	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T26	11		T89	10		T182	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T187	11		T125	17		T14	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T3	4		T89	2		T184	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	936	1			T2	10		T11	10		T193	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T12	1		T90	12		T184	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T11	2		T89	6		T95	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T22	9		T133	4		T236	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T12	5		T93	7		T82	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T3	1		T7	11		T28	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T11	11		T138	8		T266	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T45	7		T136	14		T264	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T128	8		T13	8		T182	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T3	1		T26	10		T125	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T9	19		T95	10		T132	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T34	13		T93	1		T13	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T7	9		T34	2		T45	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T95	2		T29	4		T30	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T157	6		T90	13		T184	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T197	7		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T93	11		T141	9		T295	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T1	2		T3	3		T27	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T136	9		T141	11		T164	9

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T76	1		T13	4		T208	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T183	7		T93	1		T188	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T141	1		T211	12		T271	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T5	1		T26	13		T89	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T187	12		T136	8		T32	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T186	1		T223	11		T221	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T6	13		T123	13		T124	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T3	7		T12	1		T89	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T11	25		T89	11		T33	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T90	13		T32	2		T82	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T5	1		T7	11		T95	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T3	2		T7	10		T131	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T12	10		T27	4		T93	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T45	9		T129	14		T28	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T11	12		T123	8		T128	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T3	4		T25	1		T26	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T9	19		T95	1		T132	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T5	1		T34	5		T183	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T34	9		T45	11		T137	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T93	1		T95	1		T202	21
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1692	1			T2	1		T4	26		T7	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17408	1			T1	148		T3	101		T8	133
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T122	1		T195	14		T197	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T93	11		T188	3		T235	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T141	11		T164	9		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T26	11		T89	10		T182	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T187	11		T136	9		T264	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T186	5		T142	2		T230	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T124	18		T125	17		T31	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T3	4		T12	1		T89	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T11	12		T89	6		T33	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T90	12		T133	4		T236	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T95	15		T82	15		T134	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T3	1		T7	11		T22	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T12	5		T93	7		T192	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T45	7		T28	2		T161	28
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T11	11		T128	8		T13	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T3	1		T26	10		T125	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T9	19		T95	10		T132	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T34	13		T13	6		T186	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T34	2		T45	3		T215	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T93	1		T95	2		T29	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1157	1			T2	10		T7	9		T193	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T1	2		T3	3		T27	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T26	12		T89	11		T182	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T6	1		T187	12		T125	18
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T3	6		T89	3		T184	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1267	1			T2	11		T4	2		T11	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T12	2		T90	13		T184	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T7	1		T11	3		T89	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T22	10		T32	1		T82	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T5	1		T12	11		T93	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T3	3		T7	12		T131	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T11	12		T27	3		T220	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T25	1		T76	1		T45	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T123	1		T128	9		T13	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T3	4		T5	1		T26	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T9	20		T95	11		T132	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T34	14		T183	1		T93	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T7	10		T34	3		T45	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	306	1			T76	1		T95	3		T202	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	336	1			T157	7		T90	14		T13	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T13	1		T294	1		T197	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T123	1		T183	1		T93	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17547	1			T1	150		T3	104		T5	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T136	10		T141	12		T211	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T26	12		T89	11		T244	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T6	12		T187	11		T14	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T3	5		T89	2		T184	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1235	1			T4	24		T11	12		T35	26
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T90	12		T184	15		T203	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T7	10		T11	11		T89	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T22	4		T32	1		T82	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T12	4		T82	10		T207	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T7	9		T131	9		T28	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T11	11		T27	1		T266	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T45	8		T129	32		T136	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T123	7		T128	5		T13	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T3	1		T26	10		T140	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T9	18		T129	10		T134	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T34	4		T183	2		T13	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T7	2		T34	8		T45	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T202	19		T29	4		T30	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T157	4		T90	10		T184	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T13	3		T197	8		T292	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T123	10		T183	6		T295	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T174	15		T276	12		T296	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T136	7		T211	11		T145	13

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T76	1		T13	1		T208	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T183	1		T93	12		T188	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T141	12		T211	1		T271	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T5	1		T26	12		T89	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T187	12		T136	10		T32	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T186	6		T223	1		T221	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T6	1		T123	1		T124	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T3	6		T12	2		T89	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T11	14		T89	7		T33	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T90	13		T32	1		T82	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T5	1		T7	1		T95	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T3	3		T7	12		T131	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T12	11		T27	3		T93	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T45	8		T129	1		T28	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T11	12		T123	1		T128	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T3	4		T25	1		T26	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T9	20		T95	11		T132	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T5	1		T34	14		T183	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T34	3		T45	4		T137	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	308	1			T93	2		T95	3		T202	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1534	1			T2	11		T4	2		T7	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17524	1			T1	150		T3	104		T8	133
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T13	3		T208	9		T122	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T183	6		T188	3		T235	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T211	11		T164	8		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T26	12		T89	11		T244	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T187	11		T136	7		T126	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T223	10		T252	21		T226	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T6	12		T123	12		T124	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T3	5		T89	2		T184	28
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T11	23		T89	10		T33	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T90	12		T32	1		T82	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T7	10		T82	10		T134	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T7	9		T131	9		T22	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T12	4		T27	1		T207	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T45	8		T129	13		T28	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T11	11		T123	7		T128	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T3	1		T26	10		T129	19
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T9	18		T129	10		T134	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T34	4		T183	2		T13	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T34	8		T45	10		T215	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T202	19		T29	4		T30	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1315	1			T4	24		T7	2		T35	26

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22589

1

T1

150

T2

11

T3

117

auto[1]

auto[0]

4191

1

T3

6

T4

24

T6

12