Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.72 99.07 96.67 100.00 100.00 98.83 98.33 91.17


Total test records in report: 919
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
T795 /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.1370352851 Jul 21 05:41:57 PM PDT 24 Jul 21 05:54:50 PM PDT 24 417868363354 ps
T796 /workspace/coverage/default/18.adc_ctrl_alert_test.4042163176 Jul 21 05:40:44 PM PDT 24 Jul 21 05:40:45 PM PDT 24 299392138 ps
T797 /workspace/coverage/default/36.adc_ctrl_poweron_counter.1078727702 Jul 21 05:43:20 PM PDT 24 Jul 21 05:43:27 PM PDT 24 2760964272 ps
T302 /workspace/coverage/default/35.adc_ctrl_filters_wakeup.2602497802 Jul 21 05:43:08 PM PDT 24 Jul 21 05:58:06 PM PDT 24 365263180960 ps
T41 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.3980035918 Jul 21 05:39:20 PM PDT 24 Jul 21 05:39:27 PM PDT 24 2643122182 ps
T42 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.1452145119 Jul 21 05:39:15 PM PDT 24 Jul 21 05:39:19 PM PDT 24 2374401188 ps
T44 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.4221724789 Jul 21 05:39:19 PM PDT 24 Jul 21 05:39:23 PM PDT 24 2437274437 ps
T798 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.1439910100 Jul 21 05:39:28 PM PDT 24 Jul 21 05:39:30 PM PDT 24 519490149 ps
T799 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.3092865206 Jul 21 05:39:28 PM PDT 24 Jul 21 05:39:30 PM PDT 24 503615990 ps
T43 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.3903611532 Jul 21 05:39:18 PM PDT 24 Jul 21 05:39:48 PM PDT 24 26643151360 ps
T78 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.3871055340 Jul 21 05:39:29 PM PDT 24 Jul 21 05:39:31 PM PDT 24 658578660 ps
T46 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.522381326 Jul 21 05:39:35 PM PDT 24 Jul 21 05:39:43 PM PDT 24 4412164108 ps
T800 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.374352419 Jul 21 05:39:31 PM PDT 24 Jul 21 05:39:35 PM PDT 24 358041731 ps
T118 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.2977160474 Jul 21 05:39:25 PM PDT 24 Jul 21 05:39:26 PM PDT 24 470316386 ps
T49 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.2407921628 Jul 21 05:39:30 PM PDT 24 Jul 21 05:39:34 PM PDT 24 537133600 ps
T79 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.908402233 Jul 21 05:39:34 PM PDT 24 Jul 21 05:39:37 PM PDT 24 511006881 ps
T801 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.1966811595 Jul 21 05:39:33 PM PDT 24 Jul 21 05:39:35 PM PDT 24 432688290 ps
T97 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.1388599203 Jul 21 05:39:21 PM PDT 24 Jul 21 05:39:24 PM PDT 24 931756382 ps
T50 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.2794986684 Jul 21 05:39:29 PM PDT 24 Jul 21 05:39:33 PM PDT 24 450188211 ps
T802 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.584208005 Jul 21 05:39:36 PM PDT 24 Jul 21 05:39:38 PM PDT 24 461642222 ps
T55 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.2308327167 Jul 21 05:39:31 PM PDT 24 Jul 21 05:39:35 PM PDT 24 822571603 ps
T803 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.4180587636 Jul 21 05:39:35 PM PDT 24 Jul 21 05:39:38 PM PDT 24 507675315 ps
T111 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.3778102671 Jul 21 05:39:36 PM PDT 24 Jul 21 05:39:38 PM PDT 24 426758553 ps
T98 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.882012612 Jul 21 05:39:21 PM PDT 24 Jul 21 05:40:38 PM PDT 24 27096177585 ps
T47 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.2040180591 Jul 21 05:39:22 PM PDT 24 Jul 21 05:39:26 PM PDT 24 4205817552 ps
T48 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.2042709954 Jul 21 05:39:23 PM PDT 24 Jul 21 05:39:26 PM PDT 24 4903597622 ps
T804 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.2650686223 Jul 21 05:39:25 PM PDT 24 Jul 21 05:39:27 PM PDT 24 516247757 ps
T805 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.2615649926 Jul 21 05:39:35 PM PDT 24 Jul 21 05:39:38 PM PDT 24 530978061 ps
T112 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.3893218421 Jul 21 05:39:30 PM PDT 24 Jul 21 05:39:35 PM PDT 24 4452951772 ps
T113 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.1687116492 Jul 21 05:39:23 PM PDT 24 Jul 21 05:39:27 PM PDT 24 3843854808 ps
T80 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.4092700198 Jul 21 05:39:15 PM PDT 24 Jul 21 05:39:18 PM PDT 24 541523951 ps
T51 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.115162364 Jul 21 05:39:27 PM PDT 24 Jul 21 05:39:35 PM PDT 24 8067603630 ps
T56 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.2273882779 Jul 21 05:39:34 PM PDT 24 Jul 21 05:39:46 PM PDT 24 4285322576 ps
T806 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.2917575114 Jul 21 05:39:36 PM PDT 24 Jul 21 05:39:39 PM PDT 24 312781982 ps
T99 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.1005980680 Jul 21 05:39:36 PM PDT 24 Jul 21 05:39:38 PM PDT 24 337898338 ps
T57 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.2957179719 Jul 21 05:39:30 PM PDT 24 Jul 21 05:39:33 PM PDT 24 667379042 ps
T114 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.3075782566 Jul 21 05:39:30 PM PDT 24 Jul 21 05:39:47 PM PDT 24 4596448051 ps
T807 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.3861849896 Jul 21 05:39:32 PM PDT 24 Jul 21 05:39:34 PM PDT 24 549104613 ps
T115 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.3659453862 Jul 21 05:39:29 PM PDT 24 Jul 21 05:39:30 PM PDT 24 442757323 ps
T88 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.1400276392 Jul 21 05:39:32 PM PDT 24 Jul 21 05:39:35 PM PDT 24 519197911 ps
T808 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.1916593843 Jul 21 05:39:31 PM PDT 24 Jul 21 05:39:34 PM PDT 24 476329111 ps
T809 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.3929686467 Jul 21 05:39:30 PM PDT 24 Jul 21 05:39:33 PM PDT 24 534225320 ps
T810 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.2930889297 Jul 21 05:39:45 PM PDT 24 Jul 21 05:39:48 PM PDT 24 309150519 ps
T100 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.3361599830 Jul 21 05:39:29 PM PDT 24 Jul 21 05:39:31 PM PDT 24 403366116 ps
T811 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.4019495348 Jul 21 05:39:36 PM PDT 24 Jul 21 05:39:39 PM PDT 24 390706262 ps
T58 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.2792067359 Jul 21 05:39:16 PM PDT 24 Jul 21 05:39:19 PM PDT 24 726265175 ps
T116 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.3824444350 Jul 21 05:39:30 PM PDT 24 Jul 21 05:39:36 PM PDT 24 5386317694 ps
T101 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.2281376321 Jul 21 05:39:20 PM PDT 24 Jul 21 05:39:25 PM PDT 24 886615478 ps
T117 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.1212146698 Jul 21 05:39:29 PM PDT 24 Jul 21 05:39:36 PM PDT 24 4406773245 ps
T64 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.1316551413 Jul 21 05:39:18 PM PDT 24 Jul 21 05:39:41 PM PDT 24 9046737748 ps
T812 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.2845904034 Jul 21 05:39:45 PM PDT 24 Jul 21 05:39:48 PM PDT 24 498830839 ps
T813 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.197156891 Jul 21 05:39:36 PM PDT 24 Jul 21 05:39:38 PM PDT 24 390144977 ps
T63 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.3303835410 Jul 21 05:39:21 PM PDT 24 Jul 21 05:39:34 PM PDT 24 8810763519 ps
T814 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.4108967297 Jul 21 05:39:33 PM PDT 24 Jul 21 05:39:36 PM PDT 24 469964664 ps
T815 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.3803130011 Jul 21 05:39:24 PM PDT 24 Jul 21 05:39:28 PM PDT 24 4571377895 ps
T816 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.1554312180 Jul 21 05:39:30 PM PDT 24 Jul 21 05:39:34 PM PDT 24 4319125862 ps
T102 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.4290589909 Jul 21 05:39:31 PM PDT 24 Jul 21 05:39:33 PM PDT 24 443700052 ps
T817 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.2718295221 Jul 21 05:39:28 PM PDT 24 Jul 21 05:39:32 PM PDT 24 559424407 ps
T818 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.2003526533 Jul 21 05:39:30 PM PDT 24 Jul 21 05:39:31 PM PDT 24 437012006 ps
T819 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.1057679815 Jul 21 05:39:29 PM PDT 24 Jul 21 05:39:32 PM PDT 24 489236624 ps
T820 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.327607401 Jul 21 05:39:30 PM PDT 24 Jul 21 05:39:32 PM PDT 24 359028726 ps
T59 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.2018378920 Jul 21 05:39:34 PM PDT 24 Jul 21 05:39:37 PM PDT 24 814022371 ps
T821 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.3367461824 Jul 21 05:39:36 PM PDT 24 Jul 21 05:39:39 PM PDT 24 377050751 ps
T822 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.3658287403 Jul 21 05:39:31 PM PDT 24 Jul 21 05:39:34 PM PDT 24 504462910 ps
T823 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.2542784212 Jul 21 05:39:29 PM PDT 24 Jul 21 05:39:31 PM PDT 24 534901328 ps
T824 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.948854415 Jul 21 05:39:28 PM PDT 24 Jul 21 05:39:31 PM PDT 24 596068851 ps
T103 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.3284651717 Jul 21 05:39:32 PM PDT 24 Jul 21 05:39:36 PM PDT 24 446894621 ps
T825 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.1545604171 Jul 21 05:39:45 PM PDT 24 Jul 21 05:39:47 PM PDT 24 504233091 ps
T104 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.2957592287 Jul 21 05:39:27 PM PDT 24 Jul 21 05:40:10 PM PDT 24 43384959944 ps
T826 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.1946601413 Jul 21 05:39:34 PM PDT 24 Jul 21 05:39:36 PM PDT 24 374938331 ps
T105 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.1749991656 Jul 21 05:39:31 PM PDT 24 Jul 21 05:39:34 PM PDT 24 512184388 ps
T827 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.3366942390 Jul 21 05:39:35 PM PDT 24 Jul 21 05:39:38 PM PDT 24 522905260 ps
T828 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.385354138 Jul 21 05:39:11 PM PDT 24 Jul 21 05:39:13 PM PDT 24 295544701 ps
T829 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.2057435612 Jul 21 05:39:45 PM PDT 24 Jul 21 05:39:48 PM PDT 24 373279667 ps
T830 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.1418202239 Jul 21 05:39:39 PM PDT 24 Jul 21 05:39:41 PM PDT 24 476326054 ps
T831 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.1485862548 Jul 21 05:39:31 PM PDT 24 Jul 21 05:39:34 PM PDT 24 603647756 ps
T832 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.689399646 Jul 21 05:39:20 PM PDT 24 Jul 21 05:39:22 PM PDT 24 341501504 ps
T833 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.3019968648 Jul 21 05:39:37 PM PDT 24 Jul 21 05:39:39 PM PDT 24 503245992 ps
T834 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.4280136587 Jul 21 05:39:42 PM PDT 24 Jul 21 05:39:46 PM PDT 24 524287130 ps
T835 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.206748322 Jul 21 05:39:28 PM PDT 24 Jul 21 05:39:31 PM PDT 24 848516021 ps
T836 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.2263104448 Jul 21 05:39:27 PM PDT 24 Jul 21 05:39:28 PM PDT 24 524895556 ps
T837 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.2464430297 Jul 21 05:39:32 PM PDT 24 Jul 21 05:39:39 PM PDT 24 2963467631 ps
T106 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.1969535815 Jul 21 05:39:23 PM PDT 24 Jul 21 05:39:25 PM PDT 24 377399171 ps
T838 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.1601880951 Jul 21 05:39:44 PM PDT 24 Jul 21 05:39:46 PM PDT 24 473967377 ps
T839 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.2878904169 Jul 21 05:39:31 PM PDT 24 Jul 21 05:39:40 PM PDT 24 8885726429 ps
T108 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.634125211 Jul 21 05:39:26 PM PDT 24 Jul 21 05:39:28 PM PDT 24 875496085 ps
T840 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.1617853788 Jul 21 05:39:29 PM PDT 24 Jul 21 05:39:32 PM PDT 24 392743697 ps
T841 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.3333048998 Jul 21 05:39:35 PM PDT 24 Jul 21 05:39:39 PM PDT 24 562441828 ps
T842 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.1926676274 Jul 21 05:39:35 PM PDT 24 Jul 21 05:39:37 PM PDT 24 382976201 ps
T843 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.1207295690 Jul 21 05:39:37 PM PDT 24 Jul 21 05:39:45 PM PDT 24 7890974509 ps
T844 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.1727875082 Jul 21 05:39:37 PM PDT 24 Jul 21 05:39:41 PM PDT 24 694407981 ps
T845 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.3154900608 Jul 21 05:39:23 PM PDT 24 Jul 21 05:39:27 PM PDT 24 904151824 ps
T846 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.1931581274 Jul 21 05:39:30 PM PDT 24 Jul 21 05:39:33 PM PDT 24 445613996 ps
T847 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.526473725 Jul 21 05:39:28 PM PDT 24 Jul 21 05:39:30 PM PDT 24 574944860 ps
T848 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.2020220597 Jul 21 05:39:36 PM PDT 24 Jul 21 05:39:40 PM PDT 24 465032468 ps
T849 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.3171797345 Jul 21 05:39:33 PM PDT 24 Jul 21 05:39:35 PM PDT 24 481190462 ps
T850 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.3240338064 Jul 21 05:39:33 PM PDT 24 Jul 21 05:39:39 PM PDT 24 2108962688 ps
T107 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.1313788965 Jul 21 05:39:31 PM PDT 24 Jul 21 05:39:37 PM PDT 24 1000566742 ps
T851 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.3683929720 Jul 21 05:39:35 PM PDT 24 Jul 21 05:39:43 PM PDT 24 8610269986 ps
T852 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.169670602 Jul 21 05:39:24 PM PDT 24 Jul 21 05:39:26 PM PDT 24 512537286 ps
T853 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.1482922013 Jul 21 05:39:34 PM PDT 24 Jul 21 05:39:36 PM PDT 24 462014833 ps
T854 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.3426873666 Jul 21 05:39:29 PM PDT 24 Jul 21 05:39:40 PM PDT 24 4002709153 ps
T855 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.864704148 Jul 21 05:39:23 PM PDT 24 Jul 21 05:39:26 PM PDT 24 508159491 ps
T856 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.243048075 Jul 21 05:39:23 PM PDT 24 Jul 21 05:39:25 PM PDT 24 310314258 ps
T857 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.2788538007 Jul 21 05:39:35 PM PDT 24 Jul 21 05:39:38 PM PDT 24 575684218 ps
T858 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.1192501931 Jul 21 05:39:20 PM PDT 24 Jul 21 05:39:56 PM PDT 24 26882518693 ps
T859 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.109222450 Jul 21 05:39:11 PM PDT 24 Jul 21 05:39:33 PM PDT 24 8563180804 ps
T860 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.1347144766 Jul 21 05:39:37 PM PDT 24 Jul 21 05:39:52 PM PDT 24 8494117135 ps
T861 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.265063714 Jul 21 05:39:38 PM PDT 24 Jul 21 05:39:47 PM PDT 24 8285939135 ps
T862 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.4028500000 Jul 21 05:39:35 PM PDT 24 Jul 21 05:39:37 PM PDT 24 712382802 ps
T863 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.741348799 Jul 21 05:39:29 PM PDT 24 Jul 21 05:39:38 PM PDT 24 8940994919 ps
T864 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.103827379 Jul 21 05:39:46 PM PDT 24 Jul 21 05:39:48 PM PDT 24 308654947 ps
T109 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.674586862 Jul 21 05:39:19 PM PDT 24 Jul 21 05:40:35 PM PDT 24 30690089929 ps
T865 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.1651466733 Jul 21 05:39:35 PM PDT 24 Jul 21 05:39:41 PM PDT 24 2582945834 ps
T866 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.2739676193 Jul 21 05:39:29 PM PDT 24 Jul 21 05:39:50 PM PDT 24 7912370745 ps
T867 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.1993695949 Jul 21 05:39:27 PM PDT 24 Jul 21 05:39:29 PM PDT 24 478732047 ps
T868 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.684230486 Jul 21 05:39:39 PM PDT 24 Jul 21 05:39:43 PM PDT 24 364528644 ps
T869 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.1617384710 Jul 21 05:39:36 PM PDT 24 Jul 21 05:39:38 PM PDT 24 423690784 ps
T870 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.3941083156 Jul 21 05:39:34 PM PDT 24 Jul 21 05:39:36 PM PDT 24 523648868 ps
T871 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.1331010034 Jul 21 05:39:37 PM PDT 24 Jul 21 05:39:41 PM PDT 24 325433007 ps
T872 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.2420383709 Jul 21 05:39:29 PM PDT 24 Jul 21 05:39:50 PM PDT 24 8391213638 ps
T873 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.3699358863 Jul 21 05:39:38 PM PDT 24 Jul 21 05:39:43 PM PDT 24 459097542 ps
T874 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.33499070 Jul 21 05:39:41 PM PDT 24 Jul 21 05:39:42 PM PDT 24 513264439 ps
T875 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.1531515239 Jul 21 05:39:31 PM PDT 24 Jul 21 05:39:47 PM PDT 24 4302204744 ps
T876 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.145734251 Jul 21 05:39:36 PM PDT 24 Jul 21 05:39:43 PM PDT 24 2584027395 ps
T877 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.3714513553 Jul 21 05:39:37 PM PDT 24 Jul 21 05:39:40 PM PDT 24 357758420 ps
T878 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.550414165 Jul 21 05:39:22 PM PDT 24 Jul 21 05:39:24 PM PDT 24 725690615 ps
T110 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.3380180929 Jul 21 05:39:23 PM PDT 24 Jul 21 05:39:27 PM PDT 24 1045056798 ps
T879 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.33714052 Jul 21 05:39:38 PM PDT 24 Jul 21 05:39:41 PM PDT 24 464585070 ps
T880 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.2301825069 Jul 21 05:39:33 PM PDT 24 Jul 21 05:39:46 PM PDT 24 7882016799 ps
T881 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.1885904466 Jul 21 05:39:24 PM PDT 24 Jul 21 05:39:45 PM PDT 24 8207590234 ps
T882 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.3932439882 Jul 21 05:39:31 PM PDT 24 Jul 21 05:39:33 PM PDT 24 452590601 ps
T883 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.1682755396 Jul 21 05:39:20 PM PDT 24 Jul 21 05:39:25 PM PDT 24 893736422 ps
T884 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.1286681728 Jul 21 05:39:46 PM PDT 24 Jul 21 05:39:49 PM PDT 24 377279192 ps
T885 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.25598458 Jul 21 05:39:24 PM PDT 24 Jul 21 05:39:27 PM PDT 24 402863127 ps
T886 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.1968335583 Jul 21 05:39:27 PM PDT 24 Jul 21 05:39:30 PM PDT 24 523766965 ps
T887 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.2052770229 Jul 21 05:39:42 PM PDT 24 Jul 21 05:39:44 PM PDT 24 399839827 ps
T888 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.2298973825 Jul 21 05:39:32 PM PDT 24 Jul 21 05:39:45 PM PDT 24 4679228553 ps
T889 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.2126039547 Jul 21 05:39:23 PM PDT 24 Jul 21 05:39:24 PM PDT 24 471953834 ps
T890 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.2812172292 Jul 21 05:39:39 PM PDT 24 Jul 21 05:39:41 PM PDT 24 401181375 ps
T891 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.3105857131 Jul 21 05:39:27 PM PDT 24 Jul 21 05:39:30 PM PDT 24 553560208 ps
T892 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.1276197011 Jul 21 05:39:39 PM PDT 24 Jul 21 05:39:42 PM PDT 24 500013281 ps
T893 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.3140696249 Jul 21 05:39:25 PM PDT 24 Jul 21 05:39:28 PM PDT 24 2630851547 ps
T894 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.2676009742 Jul 21 05:39:28 PM PDT 24 Jul 21 05:39:31 PM PDT 24 384638429 ps
T895 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.759961189 Jul 21 05:39:20 PM PDT 24 Jul 21 05:39:24 PM PDT 24 953453645 ps
T896 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.2235688497 Jul 21 05:39:31 PM PDT 24 Jul 21 05:39:36 PM PDT 24 4457333189 ps
T897 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.2445124671 Jul 21 05:39:23 PM PDT 24 Jul 21 05:39:25 PM PDT 24 394248293 ps
T898 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.3666085617 Jul 21 05:39:46 PM PDT 24 Jul 21 05:39:48 PM PDT 24 320097678 ps
T899 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.1179741922 Jul 21 05:39:38 PM PDT 24 Jul 21 05:39:40 PM PDT 24 429241576 ps
T900 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.987750071 Jul 21 05:39:29 PM PDT 24 Jul 21 05:39:31 PM PDT 24 455698682 ps
T901 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.2398533653 Jul 21 05:39:31 PM PDT 24 Jul 21 05:39:34 PM PDT 24 394382072 ps
T902 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.3600892471 Jul 21 05:39:27 PM PDT 24 Jul 21 05:39:30 PM PDT 24 566927936 ps
T903 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.3017004245 Jul 21 05:39:28 PM PDT 24 Jul 21 05:39:31 PM PDT 24 429044724 ps
T904 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.2401053737 Jul 21 05:39:28 PM PDT 24 Jul 21 05:39:38 PM PDT 24 8053571017 ps
T905 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.1123618334 Jul 21 05:39:32 PM PDT 24 Jul 21 05:39:34 PM PDT 24 516243373 ps
T906 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.1998575432 Jul 21 05:39:25 PM PDT 24 Jul 21 05:39:28 PM PDT 24 783274885 ps
T907 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.3980491342 Jul 21 05:39:35 PM PDT 24 Jul 21 05:39:39 PM PDT 24 537136456 ps
T908 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.3821906042 Jul 21 05:39:31 PM PDT 24 Jul 21 05:39:38 PM PDT 24 2225309198 ps
T909 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.629773018 Jul 21 05:39:11 PM PDT 24 Jul 21 05:39:14 PM PDT 24 307715460 ps
T910 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.492575428 Jul 21 05:39:38 PM PDT 24 Jul 21 05:39:41 PM PDT 24 301588473 ps
T911 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.1919033610 Jul 21 05:39:38 PM PDT 24 Jul 21 05:39:52 PM PDT 24 4757481360 ps
T912 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.3055732787 Jul 21 05:39:38 PM PDT 24 Jul 21 05:39:42 PM PDT 24 408969552 ps
T913 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.2508053833 Jul 21 05:39:20 PM PDT 24 Jul 21 05:39:23 PM PDT 24 499939953 ps
T914 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.995206321 Jul 21 05:39:33 PM PDT 24 Jul 21 05:39:35 PM PDT 24 409705499 ps
T915 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.75727912 Jul 21 05:39:21 PM PDT 24 Jul 21 05:39:24 PM PDT 24 625906033 ps
T916 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.3533990162 Jul 21 05:39:33 PM PDT 24 Jul 21 05:39:35 PM PDT 24 364009535 ps
T917 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.2778915635 Jul 21 05:39:34 PM PDT 24 Jul 21 05:39:36 PM PDT 24 321957700 ps
T918 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.3233608685 Jul 21 05:39:30 PM PDT 24 Jul 21 05:39:33 PM PDT 24 347048752 ps
T919 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.4276428888 Jul 21 05:39:26 PM PDT 24 Jul 21 05:39:27 PM PDT 24 352972814 ps

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.2317185103
Short name T3
Test name
Test status
Simulation time 581109893140 ps
CPU time 308.99 seconds
Started Jul 21 05:43:57 PM PDT 24
Finished Jul 21 05:49:07 PM PDT 24
Peak memory 210620 kb
Host smart-f7ade5e4-f4cc-4b66-9f26-f81dd6b669f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317185103 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.2317185103
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.880586532
Short name T13
Test name
Test status
Simulation time 1259353922474 ps
CPU time 731.35 seconds
Started Jul 21 05:44:16 PM PDT 24
Finished Jul 21 05:56:28 PM PDT 24
Peak memory 210448 kb
Host smart-d3ea15c6-3978-4253-bcf8-f1b40e8fc607
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880586532 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.880586532
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.1744737583
Short name T11
Test name
Test status
Simulation time 496677232460 ps
CPU time 100.03 seconds
Started Jul 21 05:42:16 PM PDT 24
Finished Jul 21 05:43:57 PM PDT 24
Peak memory 201744 kb
Host smart-d231ca84-7931-4d98-9474-0c11b60141e3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744737583 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gat
ing.1744737583
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.2127102086
Short name T30
Test name
Test status
Simulation time 349717876074 ps
CPU time 240.91 seconds
Started Jul 21 05:40:42 PM PDT 24
Finished Jul 21 05:44:43 PM PDT 24
Peak memory 218584 kb
Host smart-f37bffe1-4986-432c-8bcc-1039aab591c2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127102086 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.2127102086
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.924145686
Short name T122
Test name
Test status
Simulation time 573912521452 ps
CPU time 122.22 seconds
Started Jul 21 05:43:03 PM PDT 24
Finished Jul 21 05:45:06 PM PDT 24
Peak memory 210044 kb
Host smart-214cad35-c48c-4805-a455-e920f6608f24
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924145686 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.924145686
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.2001124823
Short name T134
Test name
Test status
Simulation time 543157405453 ps
CPU time 160.64 seconds
Started Jul 21 05:42:51 PM PDT 24
Finished Jul 21 05:45:32 PM PDT 24
Peak memory 201732 kb
Host smart-2593bd21-6c0f-4f44-9326-a880493d8615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001124823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.2001124823
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.2994302953
Short name T45
Test name
Test status
Simulation time 400071730954 ps
CPU time 143.81 seconds
Started Jul 21 05:43:49 PM PDT 24
Finished Jul 21 05:46:13 PM PDT 24
Peak memory 201624 kb
Host smart-81881520-8ded-42d9-8546-a04403caee43
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994302953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gat
ing.2994302953
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.3099991855
Short name T236
Test name
Test status
Simulation time 715168704480 ps
CPU time 891.25 seconds
Started Jul 21 05:40:34 PM PDT 24
Finished Jul 21 05:55:26 PM PDT 24
Peak memory 201788 kb
Host smart-9f5b17d7-2dac-41ab-a487-84d278803443
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099991855 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all
.3099991855
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.3056979114
Short name T26
Test name
Test status
Simulation time 344670928578 ps
CPU time 784.37 seconds
Started Jul 21 05:41:57 PM PDT 24
Finished Jul 21 05:55:01 PM PDT 24
Peak memory 201752 kb
Host smart-7a308094-2d57-4089-ac48-7be794db3351
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056979114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gat
ing.3056979114
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.2035243686
Short name T7
Test name
Test status
Simulation time 502213131100 ps
CPU time 1202.26 seconds
Started Jul 21 05:44:43 PM PDT 24
Finished Jul 21 06:04:45 PM PDT 24
Peak memory 201712 kb
Host smart-57672f6c-3f7a-44ce-b333-0fcc5e2d5b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035243686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.2035243686
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.3999206740
Short name T125
Test name
Test status
Simulation time 489513494666 ps
CPU time 488.49 seconds
Started Jul 21 05:40:33 PM PDT 24
Finished Jul 21 05:48:42 PM PDT 24
Peak memory 201780 kb
Host smart-67f0aaa8-d1b4-4ca1-8d6d-25bb9d9f49d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999206740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.3999206740
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.1428776135
Short name T81
Test name
Test status
Simulation time 398326480 ps
CPU time 1.25 seconds
Started Jul 21 05:40:03 PM PDT 24
Finished Jul 21 05:40:05 PM PDT 24
Peak memory 201464 kb
Host smart-db8b9bd0-3619-41a3-a3e3-f225992702ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428776135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.1428776135
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.3318472911
Short name T222
Test name
Test status
Simulation time 524733610164 ps
CPU time 299.05 seconds
Started Jul 21 05:40:11 PM PDT 24
Finished Jul 21 05:45:11 PM PDT 24
Peak memory 201716 kb
Host smart-9ead3ee5-ca1a-4133-85cf-c90ed9f256a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318472911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.3318472911
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.882012612
Short name T98
Test name
Test status
Simulation time 27096177585 ps
CPU time 76.59 seconds
Started Jul 21 05:39:21 PM PDT 24
Finished Jul 21 05:40:38 PM PDT 24
Peak memory 201736 kb
Host smart-5e604e41-aaeb-4bdb-ba09-e20602089c30
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882012612 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_b
ash.882012612
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.2782413717
Short name T142
Test name
Test status
Simulation time 501883112258 ps
CPU time 166.95 seconds
Started Jul 21 05:42:01 PM PDT 24
Finished Jul 21 05:44:48 PM PDT 24
Peak memory 201784 kb
Host smart-1b7b9a44-45c2-49b6-9eb2-78945d039c73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782413717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.2782413717
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.115162364
Short name T51
Test name
Test status
Simulation time 8067603630 ps
CPU time 7.07 seconds
Started Jul 21 05:39:27 PM PDT 24
Finished Jul 21 05:39:35 PM PDT 24
Peak memory 201776 kb
Host smart-f5a6d740-36ff-4648-9e68-1bfa3bb438ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115162364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_int
g_err.115162364
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.4198774190
Short name T148
Test name
Test status
Simulation time 501431817149 ps
CPU time 131.95 seconds
Started Jul 21 05:40:21 PM PDT 24
Finished Jul 21 05:42:34 PM PDT 24
Peak memory 201620 kb
Host smart-792efda5-822b-4f66-9572-9dc05b48da92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198774190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.4198774190
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.2276410980
Short name T35
Test name
Test status
Simulation time 591759008100 ps
CPU time 516.18 seconds
Started Jul 21 05:40:59 PM PDT 24
Finished Jul 21 05:49:36 PM PDT 24
Peak memory 201732 kb
Host smart-9f8710dc-b72b-41dd-8f41-1d90160345f4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276410980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.adc_ctrl_filters_wakeup_fixed.2276410980
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.2308327167
Short name T55
Test name
Test status
Simulation time 822571603 ps
CPU time 2.7 seconds
Started Jul 21 05:39:31 PM PDT 24
Finished Jul 21 05:39:35 PM PDT 24
Peak memory 201756 kb
Host smart-f3eaedba-471d-4a81-b67f-cc5969686297
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308327167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.2308327167
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.2033472100
Short name T136
Test name
Test status
Simulation time 360489904428 ps
CPU time 861.12 seconds
Started Jul 21 05:40:22 PM PDT 24
Finished Jul 21 05:54:44 PM PDT 24
Peak memory 201684 kb
Host smart-01e2ced3-9455-4aaa-996f-f076446a6dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033472100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.2033472100
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.1518908085
Short name T184
Test name
Test status
Simulation time 540110581608 ps
CPU time 1146.6 seconds
Started Jul 21 05:40:41 PM PDT 24
Finished Jul 21 05:59:48 PM PDT 24
Peak memory 201772 kb
Host smart-aca9fe9c-8773-4461-81d5-232f97eb5994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518908085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.1518908085
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.3476242892
Short name T89
Test name
Test status
Simulation time 496748009337 ps
CPU time 708.43 seconds
Started Jul 21 05:40:13 PM PDT 24
Finished Jul 21 05:52:03 PM PDT 24
Peak memory 201728 kb
Host smart-d5438aba-482b-4714-aaaa-3923606e245d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476242892 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.3476242892
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.2092781306
Short name T209
Test name
Test status
Simulation time 373552573335 ps
CPU time 322.87 seconds
Started Jul 21 05:40:08 PM PDT 24
Finished Jul 21 05:45:31 PM PDT 24
Peak memory 201776 kb
Host smart-11056cff-bcbe-43d7-9ef0-ba46666884d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092781306 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.
2092781306
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.1572984858
Short name T197
Test name
Test status
Simulation time 496196391399 ps
CPU time 1176.27 seconds
Started Jul 21 05:42:59 PM PDT 24
Finished Jul 21 06:02:35 PM PDT 24
Peak memory 201676 kb
Host smart-cb711a32-bfcf-42e5-bbc5-89d86c3627f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572984858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.1572984858
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.1246686666
Short name T141
Test name
Test status
Simulation time 491971938234 ps
CPU time 93.81 seconds
Started Jul 21 05:43:00 PM PDT 24
Finished Jul 21 05:44:34 PM PDT 24
Peak memory 201804 kb
Host smart-a5e59b0f-fe6a-4291-aed7-58ba5f83d362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246686666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.1246686666
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.1477252087
Short name T157
Test name
Test status
Simulation time 176614129930 ps
CPU time 399.44 seconds
Started Jul 21 05:42:17 PM PDT 24
Finished Jul 21 05:48:57 PM PDT 24
Peak memory 201764 kb
Host smart-45c133c4-bcfd-4cb8-bf65-e605e661aea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477252087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.1477252087
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.1712410079
Short name T65
Test name
Test status
Simulation time 4276103826 ps
CPU time 3.88 seconds
Started Jul 21 05:40:03 PM PDT 24
Finished Jul 21 05:40:07 PM PDT 24
Peak memory 217292 kb
Host smart-39bfba11-c95d-4627-8558-0d0e2b408d22
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712410079 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.1712410079
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.83901131
Short name T90
Test name
Test status
Simulation time 363470474571 ps
CPU time 807.83 seconds
Started Jul 21 05:41:41 PM PDT 24
Finished Jul 21 05:55:09 PM PDT 24
Peak memory 201776 kb
Host smart-06c7ee17-e5b8-4ce1-ae8a-cb5461b8a60e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83901131 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.83901131
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.589776981
Short name T249
Test name
Test status
Simulation time 354344896733 ps
CPU time 77.97 seconds
Started Jul 21 05:40:50 PM PDT 24
Finished Jul 21 05:42:08 PM PDT 24
Peak memory 201724 kb
Host smart-00c8c234-7eb3-41ea-ba47-bee8837927ef
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589776981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_
wakeup.589776981
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.475242284
Short name T77
Test name
Test status
Simulation time 33743979820 ps
CPU time 8.07 seconds
Started Jul 21 05:45:07 PM PDT 24
Finished Jul 21 05:45:16 PM PDT 24
Peak memory 201880 kb
Host smart-425c8b7d-f360-4c8d-ad04-49a05d54c40b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475242284 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.475242284
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.120967696
Short name T214
Test name
Test status
Simulation time 525407176602 ps
CPU time 1092.84 seconds
Started Jul 21 05:45:27 PM PDT 24
Finished Jul 21 06:03:40 PM PDT 24
Peak memory 201736 kb
Host smart-f97a346e-a03e-4e9f-8d4a-14b01a8019ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120967696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all.
120967696
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.1518034128
Short name T180
Test name
Test status
Simulation time 517216291165 ps
CPU time 290.72 seconds
Started Jul 21 05:40:59 PM PDT 24
Finished Jul 21 05:45:50 PM PDT 24
Peak memory 201732 kb
Host smart-5cec643d-780f-4841-a62d-5c86ac47ac20
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518034128 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gat
ing.1518034128
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.1088572317
Short name T187
Test name
Test status
Simulation time 160616961792 ps
CPU time 353.99 seconds
Started Jul 21 05:40:27 PM PDT 24
Finished Jul 21 05:46:22 PM PDT 24
Peak memory 201640 kb
Host smart-317cc34f-e7ab-4b1c-89e1-41a94a627308
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088572317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gat
ing.1088572317
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.1583972106
Short name T29
Test name
Test status
Simulation time 436818184018 ps
CPU time 595.33 seconds
Started Jul 21 05:45:41 PM PDT 24
Finished Jul 21 05:55:37 PM PDT 24
Peak memory 210504 kb
Host smart-b0a51bd1-7534-48a0-bbc7-9f96aea821c3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583972106 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.1583972106
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.749283925
Short name T257
Test name
Test status
Simulation time 184158575777 ps
CPU time 115.09 seconds
Started Jul 21 05:40:20 PM PDT 24
Finished Jul 21 05:42:16 PM PDT 24
Peak memory 201664 kb
Host smart-716863b8-95f3-4697-823e-da9efede13c5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749283925 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_w
akeup.749283925
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.3511968789
Short name T12
Test name
Test status
Simulation time 137084994270 ps
CPU time 195.44 seconds
Started Jul 21 05:42:21 PM PDT 24
Finished Jul 21 05:45:36 PM PDT 24
Peak memory 210432 kb
Host smart-de84a3c9-3b06-4eba-bc72-b22fa3e79a0c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511968789 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.3511968789
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.3222167420
Short name T31
Test name
Test status
Simulation time 468328737587 ps
CPU time 813.56 seconds
Started Jul 21 05:40:27 PM PDT 24
Finished Jul 21 05:54:02 PM PDT 24
Peak memory 210332 kb
Host smart-fa18665f-7def-4588-ac74-f3d9665486ce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222167420 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.3222167420
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.2927996632
Short name T223
Test name
Test status
Simulation time 178826780043 ps
CPU time 114.7 seconds
Started Jul 21 05:41:03 PM PDT 24
Finished Jul 21 05:42:58 PM PDT 24
Peak memory 201748 kb
Host smart-0e4c0298-64a2-44ce-bfa7-674a71818a06
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927996632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters
_wakeup.2927996632
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.3586726548
Short name T144
Test name
Test status
Simulation time 489875178137 ps
CPU time 238.38 seconds
Started Jul 21 05:41:22 PM PDT 24
Finished Jul 21 05:45:21 PM PDT 24
Peak memory 201688 kb
Host smart-d35c1a3c-0543-4fc4-8e0b-1d7f584fb3e7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586726548 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gat
ing.3586726548
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.3980035918
Short name T41
Test name
Test status
Simulation time 2643122182 ps
CPU time 6.52 seconds
Started Jul 21 05:39:20 PM PDT 24
Finished Jul 21 05:39:27 PM PDT 24
Peak memory 201504 kb
Host smart-3c3bfbb9-f4e6-41de-b6b9-b4a7e292750b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980035918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_c
trl_same_csr_outstanding.3980035918
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.4003858026
Short name T322
Test name
Test status
Simulation time 202130774331 ps
CPU time 6.28 seconds
Started Jul 21 05:40:52 PM PDT 24
Finished Jul 21 05:40:59 PM PDT 24
Peak memory 201748 kb
Host smart-7f166d8b-a9a4-4123-bf7a-78a3bb605d63
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003858026 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gat
ing.4003858026
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.3992205025
Short name T167
Test name
Test status
Simulation time 446386690156 ps
CPU time 373.91 seconds
Started Jul 21 05:42:03 PM PDT 24
Finished Jul 21 05:48:17 PM PDT 24
Peak memory 210484 kb
Host smart-aab124ea-d67d-4fde-8e35-46fd1dbbdce9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992205025 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.3992205025
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.2967570210
Short name T68
Test name
Test status
Simulation time 122275662297 ps
CPU time 154.35 seconds
Started Jul 21 05:40:12 PM PDT 24
Finished Jul 21 05:42:47 PM PDT 24
Peak memory 201912 kb
Host smart-06f2e553-a94a-4517-b128-7873109b9068
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967570210 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.2967570210
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.830976878
Short name T188
Test name
Test status
Simulation time 180735486342 ps
CPU time 347.55 seconds
Started Jul 21 05:45:32 PM PDT 24
Finished Jul 21 05:51:20 PM PDT 24
Peak memory 201560 kb
Host smart-af9377d2-1f9d-45ad-94ed-663a92238163
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830976878 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gati
ng.830976878
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.2972839166
Short name T378
Test name
Test status
Simulation time 163753282050 ps
CPU time 96.84 seconds
Started Jul 21 05:40:29 PM PDT 24
Finished Jul 21 05:42:07 PM PDT 24
Peak memory 201612 kb
Host smart-1e630170-d8e4-4a8d-bd89-8c849b334112
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972839166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interru
pt_fixed.2972839166
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.1664096066
Short name T217
Test name
Test status
Simulation time 542251732508 ps
CPU time 327.85 seconds
Started Jul 21 05:40:32 PM PDT 24
Finished Jul 21 05:46:00 PM PDT 24
Peak memory 201760 kb
Host smart-53036485-9389-456e-8d7c-42d6a2c79ca0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664096066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters
_wakeup.1664096066
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.3394222365
Short name T218
Test name
Test status
Simulation time 549887010576 ps
CPU time 419.18 seconds
Started Jul 21 05:41:13 PM PDT 24
Finished Jul 21 05:48:13 PM PDT 24
Peak memory 201664 kb
Host smart-cf0ed228-fcab-4414-b113-3d72e77291d6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394222365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gat
ing.3394222365
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.890383991
Short name T328
Test name
Test status
Simulation time 331270418285 ps
CPU time 720.48 seconds
Started Jul 21 05:42:24 PM PDT 24
Finished Jul 21 05:54:25 PM PDT 24
Peak memory 201684 kb
Host smart-e356d438-b387-48cc-97b0-00c1b2748db9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890383991 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gati
ng.890383991
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.2510138551
Short name T261
Test name
Test status
Simulation time 513652332655 ps
CPU time 113.43 seconds
Started Jul 21 05:40:33 PM PDT 24
Finished Jul 21 05:42:27 PM PDT 24
Peak memory 201736 kb
Host smart-695a0491-6507-4619-97c9-2a68bd7d3515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510138551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.2510138551
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.2792067359
Short name T58
Test name
Test status
Simulation time 726265175 ps
CPU time 2.65 seconds
Started Jul 21 05:39:16 PM PDT 24
Finished Jul 21 05:39:19 PM PDT 24
Peak memory 218136 kb
Host smart-7fb309c9-749b-4693-a145-97a56ac95d51
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792067359 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.2792067359
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.4023560228
Short name T298
Test name
Test status
Simulation time 359540110827 ps
CPU time 781.95 seconds
Started Jul 21 05:40:08 PM PDT 24
Finished Jul 21 05:53:11 PM PDT 24
Peak memory 201708 kb
Host smart-6a27b466-a4e0-426b-8ad9-8f12720a795b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023560228 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gati
ng.4023560228
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.39545614
Short name T263
Test name
Test status
Simulation time 201298111379 ps
CPU time 475.98 seconds
Started Jul 21 05:40:28 PM PDT 24
Finished Jul 21 05:48:25 PM PDT 24
Peak memory 201724 kb
Host smart-424e7ea0-77fc-4d37-b6ad-4a8192f44bc1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39545614 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all.39545614
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.3320425712
Short name T462
Test name
Test status
Simulation time 515814684800 ps
CPU time 223.85 seconds
Started Jul 21 05:40:44 PM PDT 24
Finished Jul 21 05:44:28 PM PDT 24
Peak memory 201716 kb
Host smart-ea4406d3-a404-4a9c-93f2-1f91bb3e1e80
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320425712 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gat
ing.3320425712
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.4201828966
Short name T36
Test name
Test status
Simulation time 115497526267 ps
CPU time 356.03 seconds
Started Jul 21 05:41:18 PM PDT 24
Finished Jul 21 05:47:14 PM PDT 24
Peak memory 202088 kb
Host smart-89a41435-ff06-4383-b041-861fcf2d1813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201828966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.4201828966
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.3576277041
Short name T198
Test name
Test status
Simulation time 500002647207 ps
CPU time 1153.18 seconds
Started Jul 21 05:45:07 PM PDT 24
Finished Jul 21 06:04:20 PM PDT 24
Peak memory 201732 kb
Host smart-48f75c31-eab6-4bf6-b946-93afa559cfbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576277041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.3576277041
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.3124373992
Short name T206
Test name
Test status
Simulation time 369524247028 ps
CPU time 207.56 seconds
Started Jul 21 05:40:16 PM PDT 24
Finished Jul 21 05:43:44 PM PDT 24
Peak memory 201752 kb
Host smart-8d9ab2a3-f593-4d4e-9546-bef0eee48c0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124373992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.3124373992
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.2830074226
Short name T179
Test name
Test status
Simulation time 329843818738 ps
CPU time 196.68 seconds
Started Jul 21 05:40:02 PM PDT 24
Finished Jul 21 05:43:19 PM PDT 24
Peak memory 201736 kb
Host smart-ae22c501-2237-4949-a614-2937059a9d2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830074226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.2830074226
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.3702915164
Short name T245
Test name
Test status
Simulation time 496599270670 ps
CPU time 607.14 seconds
Started Jul 21 05:40:32 PM PDT 24
Finished Jul 21 05:50:40 PM PDT 24
Peak memory 201768 kb
Host smart-a54bf8c3-5e18-4327-8eea-2216e11a8cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702915164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.3702915164
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.2238286736
Short name T304
Test name
Test status
Simulation time 492289636335 ps
CPU time 1175.61 seconds
Started Jul 21 05:40:44 PM PDT 24
Finished Jul 21 06:00:20 PM PDT 24
Peak memory 201636 kb
Host smart-9276e039-2165-494b-930a-4bbf01d53af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238286736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.2238286736
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.2633594787
Short name T174
Test name
Test status
Simulation time 967152453142 ps
CPU time 847.72 seconds
Started Jul 21 05:41:10 PM PDT 24
Finished Jul 21 05:55:18 PM PDT 24
Peak memory 218364 kb
Host smart-4702e03f-9bb4-49d8-a5ef-882a91a8dd79
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633594787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all
.2633594787
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.288001009
Short name T312
Test name
Test status
Simulation time 297524023022 ps
CPU time 976.37 seconds
Started Jul 21 05:42:53 PM PDT 24
Finished Jul 21 05:59:10 PM PDT 24
Peak memory 210224 kb
Host smart-08b42e16-1590-41d2-bb9d-028ea53ef437
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288001009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all.
288001009
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.2282966124
Short name T129
Test name
Test status
Simulation time 563691642775 ps
CPU time 1374.12 seconds
Started Jul 21 05:44:29 PM PDT 24
Finished Jul 21 06:07:23 PM PDT 24
Peak memory 201820 kb
Host smart-1876aea4-8d9e-4e5b-8b43-e15888942368
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282966124 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters
_wakeup.2282966124
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.3445513468
Short name T254
Test name
Test status
Simulation time 165001248035 ps
CPU time 384.21 seconds
Started Jul 21 05:45:59 PM PDT 24
Finished Jul 21 05:52:24 PM PDT 24
Peak memory 201752 kb
Host smart-41954e62-089e-435e-93a2-e176767fe9da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445513468 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.3445513468
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.2291327788
Short name T149
Test name
Test status
Simulation time 369080506261 ps
CPU time 94.33 seconds
Started Jul 21 05:40:04 PM PDT 24
Finished Jul 21 05:41:39 PM PDT 24
Peak memory 201636 kb
Host smart-38b3b28e-3919-4aa8-af7b-c775ba7ab7b8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291327788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_
wakeup.2291327788
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.3068217276
Short name T324
Test name
Test status
Simulation time 203618868227 ps
CPU time 119.06 seconds
Started Jul 21 05:40:32 PM PDT 24
Finished Jul 21 05:42:31 PM PDT 24
Peak memory 201600 kb
Host smart-ed73bd95-ac56-4c36-a6ac-35f23252730c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068217276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all
.3068217276
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.4269718207
Short name T226
Test name
Test status
Simulation time 539396562319 ps
CPU time 1177.44 seconds
Started Jul 21 05:41:00 PM PDT 24
Finished Jul 21 06:00:38 PM PDT 24
Peak memory 201804 kb
Host smart-7d79d5cf-dac9-4c88-b198-31a5c6daef4f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269718207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gat
ing.4269718207
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.4203869964
Short name T307
Test name
Test status
Simulation time 160810686943 ps
CPU time 100.95 seconds
Started Jul 21 05:40:59 PM PDT 24
Finished Jul 21 05:42:40 PM PDT 24
Peak memory 201736 kb
Host smart-c2700225-967a-465a-abe8-19a890212961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203869964 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.4203869964
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.1273324202
Short name T297
Test name
Test status
Simulation time 326571428165 ps
CPU time 183.19 seconds
Started Jul 21 05:42:24 PM PDT 24
Finished Jul 21 05:45:28 PM PDT 24
Peak memory 201696 kb
Host smart-f0f4c3a4-e0f5-4030-bba6-fbedbc560f9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273324202 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.1273324202
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.4063888798
Short name T137
Test name
Test status
Simulation time 334755320068 ps
CPU time 770.82 seconds
Started Jul 21 05:43:08 PM PDT 24
Finished Jul 21 05:55:59 PM PDT 24
Peak memory 201692 kb
Host smart-6deba982-2e97-440f-a12d-84d2389ccbd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063888798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.4063888798
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.358008229
Short name T323
Test name
Test status
Simulation time 165156957457 ps
CPU time 397.9 seconds
Started Jul 21 05:45:21 PM PDT 24
Finished Jul 21 05:51:59 PM PDT 24
Peak memory 201828 kb
Host smart-93fbfd4b-9a4f-4fc3-9977-4c02534095e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358008229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.358008229
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.1853837347
Short name T176
Test name
Test status
Simulation time 123207348187 ps
CPU time 544.36 seconds
Started Jul 21 05:46:05 PM PDT 24
Finished Jul 21 05:55:09 PM PDT 24
Peak memory 202096 kb
Host smart-ee998277-f72a-479a-bd85-d42149816bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853837347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.1853837347
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.1211111356
Short name T299
Test name
Test status
Simulation time 397779301477 ps
CPU time 1173.68 seconds
Started Jul 21 05:40:45 PM PDT 24
Finished Jul 21 06:00:19 PM PDT 24
Peak memory 212572 kb
Host smart-c3acccf6-8834-4160-9e32-83926de4a8c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211111356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.
1211111356
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.1316551413
Short name T64
Test name
Test status
Simulation time 9046737748 ps
CPU time 23.09 seconds
Started Jul 21 05:39:18 PM PDT 24
Finished Jul 21 05:39:41 PM PDT 24
Peak memory 201740 kb
Host smart-aaf1fb3f-225b-4b77-9cdb-6bcb6da086d8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316551413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_in
tg_err.1316551413
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.543406384
Short name T211
Test name
Test status
Simulation time 347259012697 ps
CPU time 194.9 seconds
Started Jul 21 05:40:08 PM PDT 24
Finished Jul 21 05:43:23 PM PDT 24
Peak memory 201716 kb
Host smart-5bed5388-7b2f-43af-93a1-c92b232f8ddc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543406384 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_w
akeup.543406384
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.1643091426
Short name T335
Test name
Test status
Simulation time 15056505917 ps
CPU time 71.37 seconds
Started Jul 21 05:40:13 PM PDT 24
Finished Jul 21 05:41:25 PM PDT 24
Peak memory 210480 kb
Host smart-2b503f9b-81d5-4d60-96d2-7ae08a5da22c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643091426 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.1643091426
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.242284145
Short name T790
Test name
Test status
Simulation time 82502090267 ps
CPU time 120.57 seconds
Started Jul 21 05:40:27 PM PDT 24
Finished Jul 21 05:42:28 PM PDT 24
Peak memory 210384 kb
Host smart-b108b676-1f22-476f-9ba7-5452605fa552
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242284145 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.242284145
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.1942257972
Short name T250
Test name
Test status
Simulation time 331124119902 ps
CPU time 824.97 seconds
Started Jul 21 05:40:41 PM PDT 24
Finished Jul 21 05:54:27 PM PDT 24
Peak memory 201732 kb
Host smart-f10dc286-1ce4-4206-b5a9-31fa814b4e39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942257972 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.1942257972
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.4116705736
Short name T283
Test name
Test status
Simulation time 573688151314 ps
CPU time 235.18 seconds
Started Jul 21 05:40:38 PM PDT 24
Finished Jul 21 05:44:34 PM PDT 24
Peak memory 210020 kb
Host smart-cc0e92b7-a95b-4dfb-8548-e7a5dcee82d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116705736 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.4116705736
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.3859196927
Short name T306
Test name
Test status
Simulation time 332009415445 ps
CPU time 215.34 seconds
Started Jul 21 05:40:39 PM PDT 24
Finished Jul 21 05:44:14 PM PDT 24
Peak memory 201748 kb
Host smart-5456b347-c279-4b36-b5c2-ca268a406b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859196927 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.3859196927
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.2874238030
Short name T340
Test name
Test status
Simulation time 263698274238 ps
CPU time 601.95 seconds
Started Jul 21 05:41:01 PM PDT 24
Finished Jul 21 05:51:03 PM PDT 24
Peak memory 210544 kb
Host smart-e21b2973-ea32-491f-8587-ffa02733cc48
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874238030 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.2874238030
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.1645738408
Short name T273
Test name
Test status
Simulation time 491690436822 ps
CPU time 167.58 seconds
Started Jul 21 05:40:58 PM PDT 24
Finished Jul 21 05:43:46 PM PDT 24
Peak memory 201672 kb
Host smart-cff1ae08-783f-4e3a-8dd6-3abd21d082d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645738408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.1645738408
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.3290469623
Short name T339
Test name
Test status
Simulation time 104514165619 ps
CPU time 387.06 seconds
Started Jul 21 05:41:12 PM PDT 24
Finished Jul 21 05:47:39 PM PDT 24
Peak memory 202164 kb
Host smart-c7bc9560-bac9-430b-a2cd-dc46d9a548fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290469623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.3290469623
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.3054871775
Short name T314
Test name
Test status
Simulation time 329713357337 ps
CPU time 772.59 seconds
Started Jul 21 05:41:42 PM PDT 24
Finished Jul 21 05:54:35 PM PDT 24
Peak memory 201668 kb
Host smart-66ab4bc9-2093-4f6b-b914-51ec3cef97b4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054871775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gat
ing.3054871775
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.188997487
Short name T216
Test name
Test status
Simulation time 486380545589 ps
CPU time 607.02 seconds
Started Jul 21 05:42:11 PM PDT 24
Finished Jul 21 05:52:19 PM PDT 24
Peak memory 201884 kb
Host smart-38cca901-93f4-40bf-9ed2-d60035457e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188997487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.188997487
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.271024512
Short name T175
Test name
Test status
Simulation time 107350844515 ps
CPU time 509.23 seconds
Started Jul 21 05:40:11 PM PDT 24
Finished Jul 21 05:48:41 PM PDT 24
Peak memory 202128 kb
Host smart-4862bddf-c1bf-44c2-90e2-9feac3d6735e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271024512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.271024512
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.1370734141
Short name T151
Test name
Test status
Simulation time 489962173443 ps
CPU time 88 seconds
Started Jul 21 05:45:09 PM PDT 24
Finished Jul 21 05:46:38 PM PDT 24
Peak memory 201908 kb
Host smart-4aa774e7-4dd8-4dbb-a3d8-f0d66bfdc95e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370734141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.1370734141
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.2021247556
Short name T303
Test name
Test status
Simulation time 541728055114 ps
CPU time 243.99 seconds
Started Jul 21 05:45:18 PM PDT 24
Finished Jul 21 05:49:22 PM PDT 24
Peak memory 201664 kb
Host smart-f42f9e72-4ef7-4ee4-a223-6eeb3fe63a95
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021247556 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all
.2021247556
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.2842649781
Short name T321
Test name
Test status
Simulation time 358526514057 ps
CPU time 176.25 seconds
Started Jul 21 05:45:45 PM PDT 24
Finished Jul 21 05:48:42 PM PDT 24
Peak memory 201764 kb
Host smart-5e4080b6-37c5-46d0-b268-2572072ad48d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842649781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gat
ing.2842649781
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.2788567944
Short name T95
Test name
Test status
Simulation time 493144406299 ps
CPU time 257.32 seconds
Started Jul 21 05:40:18 PM PDT 24
Finished Jul 21 05:44:36 PM PDT 24
Peak memory 201788 kb
Host smart-39ac0619-32a5-4a01-b11e-c53e378ee975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788567944 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.2788567944
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.2281376321
Short name T101
Test name
Test status
Simulation time 886615478 ps
CPU time 4.38 seconds
Started Jul 21 05:39:20 PM PDT 24
Finished Jul 21 05:39:25 PM PDT 24
Peak memory 201628 kb
Host smart-39709241-14b0-4d61-9e88-8f6da9b573c0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281376321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alia
sing.2281376321
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.1192501931
Short name T858
Test name
Test status
Simulation time 26882518693 ps
CPU time 34.88 seconds
Started Jul 21 05:39:20 PM PDT 24
Finished Jul 21 05:39:56 PM PDT 24
Peak memory 201712 kb
Host smart-2d6491be-bd19-4633-82aa-062ce94d7a6f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192501931 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_
bash.1192501931
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.550414165
Short name T878
Test name
Test status
Simulation time 725690615 ps
CPU time 1.41 seconds
Started Jul 21 05:39:22 PM PDT 24
Finished Jul 21 05:39:24 PM PDT 24
Peak memory 201516 kb
Host smart-b8185a66-e10f-4bce-8d44-19494fd37d6a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550414165 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_re
set.550414165
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.4092700198
Short name T80
Test name
Test status
Simulation time 541523951 ps
CPU time 2.17 seconds
Started Jul 21 05:39:15 PM PDT 24
Finished Jul 21 05:39:18 PM PDT 24
Peak memory 201556 kb
Host smart-3a1dc56b-17a6-46ff-8a2a-02c5d1c5c7ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092700198 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.4092700198
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.385354138
Short name T828
Test name
Test status
Simulation time 295544701 ps
CPU time 1.41 seconds
Started Jul 21 05:39:11 PM PDT 24
Finished Jul 21 05:39:13 PM PDT 24
Peak memory 201400 kb
Host smart-2e2930b9-b0f9-4bac-bf0f-4920acf913b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385354138 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.385354138
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.243048075
Short name T856
Test name
Test status
Simulation time 310314258 ps
CPU time 1.4 seconds
Started Jul 21 05:39:23 PM PDT 24
Finished Jul 21 05:39:25 PM PDT 24
Peak memory 201456 kb
Host smart-6590f886-4adc-49c9-ba5a-79c1ed8ee1cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243048075 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.243048075
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.109222450
Short name T859
Test name
Test status
Simulation time 8563180804 ps
CPU time 21.3 seconds
Started Jul 21 05:39:11 PM PDT 24
Finished Jul 21 05:39:33 PM PDT 24
Peak memory 201788 kb
Host smart-87903825-f66f-4d6e-987a-559bcb50536f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109222450 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_int
g_err.109222450
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.1388599203
Short name T97
Test name
Test status
Simulation time 931756382 ps
CPU time 2.03 seconds
Started Jul 21 05:39:21 PM PDT 24
Finished Jul 21 05:39:24 PM PDT 24
Peak memory 201608 kb
Host smart-c1152925-ecd8-4cca-a5c3-aeb0f6612777
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388599203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alia
sing.1388599203
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.759961189
Short name T895
Test name
Test status
Simulation time 953453645 ps
CPU time 3.08 seconds
Started Jul 21 05:39:20 PM PDT 24
Finished Jul 21 05:39:24 PM PDT 24
Peak memory 201448 kb
Host smart-9a3f32dd-ed5c-40f5-86b5-681ea8b255bd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759961189 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_re
set.759961189
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.3871055340
Short name T78
Test name
Test status
Simulation time 658578660 ps
CPU time 0.91 seconds
Started Jul 21 05:39:29 PM PDT 24
Finished Jul 21 05:39:31 PM PDT 24
Peak memory 201524 kb
Host smart-91072cb4-49b6-438b-b7d5-a69043292bf6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871055340 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.3871055340
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.2508053833
Short name T913
Test name
Test status
Simulation time 499939953 ps
CPU time 2.06 seconds
Started Jul 21 05:39:20 PM PDT 24
Finished Jul 21 05:39:23 PM PDT 24
Peak memory 201468 kb
Host smart-792fbd06-16ef-4a62-ad8a-731d3cbfeda0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508053833 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.2508053833
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.689399646
Short name T832
Test name
Test status
Simulation time 341501504 ps
CPU time 0.86 seconds
Started Jul 21 05:39:20 PM PDT 24
Finished Jul 21 05:39:22 PM PDT 24
Peak memory 201496 kb
Host smart-f07fb872-86a1-414d-a6e8-999e2c73ba0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689399646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.689399646
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.1452145119
Short name T42
Test name
Test status
Simulation time 2374401188 ps
CPU time 3.24 seconds
Started Jul 21 05:39:15 PM PDT 24
Finished Jul 21 05:39:19 PM PDT 24
Peak memory 201560 kb
Host smart-78d1ad01-2196-4f80-aad3-6810ede7ed5f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452145119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_c
trl_same_csr_outstanding.1452145119
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.629773018
Short name T909
Test name
Test status
Simulation time 307715460 ps
CPU time 2.42 seconds
Started Jul 21 05:39:11 PM PDT 24
Finished Jul 21 05:39:14 PM PDT 24
Peak memory 201780 kb
Host smart-af149d63-c1e4-4b3b-aa23-04075d571dfb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629773018 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.629773018
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.2042709954
Short name T48
Test name
Test status
Simulation time 4903597622 ps
CPU time 3.18 seconds
Started Jul 21 05:39:23 PM PDT 24
Finished Jul 21 05:39:26 PM PDT 24
Peak memory 201780 kb
Host smart-ef373a19-34d8-423c-a4cd-0c7f313a00ff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042709954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_in
tg_err.2042709954
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.1617853788
Short name T840
Test name
Test status
Simulation time 392743697 ps
CPU time 1.65 seconds
Started Jul 21 05:39:29 PM PDT 24
Finished Jul 21 05:39:32 PM PDT 24
Peak memory 201616 kb
Host smart-f867267d-b1a3-4e8f-beb8-bf6797676e83
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617853788 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.1617853788
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.2398533653
Short name T901
Test name
Test status
Simulation time 394382072 ps
CPU time 1.61 seconds
Started Jul 21 05:39:31 PM PDT 24
Finished Jul 21 05:39:34 PM PDT 24
Peak memory 201460 kb
Host smart-c79ef123-70cc-47af-809f-a0f95525a99d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398533653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.2398533653
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.1931581274
Short name T846
Test name
Test status
Simulation time 445613996 ps
CPU time 0.75 seconds
Started Jul 21 05:39:30 PM PDT 24
Finished Jul 21 05:39:33 PM PDT 24
Peak memory 201460 kb
Host smart-01f559e6-a2a2-4552-bb86-f2e5cd3ebb89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931581274 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.1931581274
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.3824444350
Short name T116
Test name
Test status
Simulation time 5386317694 ps
CPU time 4.63 seconds
Started Jul 21 05:39:30 PM PDT 24
Finished Jul 21 05:39:36 PM PDT 24
Peak memory 201764 kb
Host smart-3094e6c8-68b2-4256-ab98-dab863f54433
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824444350 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_
ctrl_same_csr_outstanding.3824444350
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.2794986684
Short name T50
Test name
Test status
Simulation time 450188211 ps
CPU time 2.76 seconds
Started Jul 21 05:39:29 PM PDT 24
Finished Jul 21 05:39:33 PM PDT 24
Peak memory 201772 kb
Host smart-30fcc654-3b76-460f-adcf-d0ba23abcc45
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794986684 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.2794986684
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.2401053737
Short name T904
Test name
Test status
Simulation time 8053571017 ps
CPU time 9.63 seconds
Started Jul 21 05:39:28 PM PDT 24
Finished Jul 21 05:39:38 PM PDT 24
Peak memory 201824 kb
Host smart-83c1f685-5005-4540-a3fe-a604827b41a2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401053737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_i
ntg_err.2401053737
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.1400276392
Short name T88
Test name
Test status
Simulation time 519197911 ps
CPU time 2.15 seconds
Started Jul 21 05:39:32 PM PDT 24
Finished Jul 21 05:39:35 PM PDT 24
Peak memory 201500 kb
Host smart-fa02fdde-c575-4ce0-8666-44251f2bd017
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400276392 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.1400276392
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.3659453862
Short name T115
Test name
Test status
Simulation time 442757323 ps
CPU time 0.91 seconds
Started Jul 21 05:39:29 PM PDT 24
Finished Jul 21 05:39:30 PM PDT 24
Peak memory 201372 kb
Host smart-089755b9-c155-4532-8d6d-014928ab194f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659453862 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.3659453862
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.1179741922
Short name T899
Test name
Test status
Simulation time 429241576 ps
CPU time 0.82 seconds
Started Jul 21 05:39:38 PM PDT 24
Finished Jul 21 05:39:40 PM PDT 24
Peak memory 201360 kb
Host smart-bf9daa20-de89-4904-b3ec-5ad9c9398cae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179741922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.1179741922
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.2235688497
Short name T896
Test name
Test status
Simulation time 4457333189 ps
CPU time 3.3 seconds
Started Jul 21 05:39:31 PM PDT 24
Finished Jul 21 05:39:36 PM PDT 24
Peak memory 201656 kb
Host smart-7e41da5c-a04b-4f99-8657-407fec2a98b0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235688497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_
ctrl_same_csr_outstanding.2235688497
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.1057679815
Short name T819
Test name
Test status
Simulation time 489236624 ps
CPU time 2.02 seconds
Started Jul 21 05:39:29 PM PDT 24
Finished Jul 21 05:39:32 PM PDT 24
Peak memory 201840 kb
Host smart-1fa451b2-d502-4220-9cd9-fd919ee3e12f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057679815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.1057679815
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.2878904169
Short name T839
Test name
Test status
Simulation time 8885726429 ps
CPU time 7.44 seconds
Started Jul 21 05:39:31 PM PDT 24
Finished Jul 21 05:39:40 PM PDT 24
Peak memory 201736 kb
Host smart-709f85a5-200b-429a-b8d1-dd0d18785045
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878904169 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_i
ntg_err.2878904169
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.1727875082
Short name T844
Test name
Test status
Simulation time 694407981 ps
CPU time 1.35 seconds
Started Jul 21 05:39:37 PM PDT 24
Finished Jul 21 05:39:41 PM PDT 24
Peak memory 201512 kb
Host smart-fcb562db-bf18-4539-92de-b7e884c41c0f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727875082 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.1727875082
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.1749991656
Short name T105
Test name
Test status
Simulation time 512184388 ps
CPU time 1.86 seconds
Started Jul 21 05:39:31 PM PDT 24
Finished Jul 21 05:39:34 PM PDT 24
Peak memory 201416 kb
Host smart-ac8a9c46-c388-4bbd-ae78-60a26034fecb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749991656 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.1749991656
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.1123618334
Short name T905
Test name
Test status
Simulation time 516243373 ps
CPU time 1.5 seconds
Started Jul 21 05:39:32 PM PDT 24
Finished Jul 21 05:39:34 PM PDT 24
Peak memory 201456 kb
Host smart-fa82078e-f1b0-4797-9ac9-7fa1a25ca97f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123618334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.1123618334
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.2298973825
Short name T888
Test name
Test status
Simulation time 4679228553 ps
CPU time 11.24 seconds
Started Jul 21 05:39:32 PM PDT 24
Finished Jul 21 05:39:45 PM PDT 24
Peak memory 201780 kb
Host smart-07b02108-785a-4503-8443-f59ae81f5ac7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298973825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_
ctrl_same_csr_outstanding.2298973825
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.2788538007
Short name T857
Test name
Test status
Simulation time 575684218 ps
CPU time 2.42 seconds
Started Jul 21 05:39:35 PM PDT 24
Finished Jul 21 05:39:38 PM PDT 24
Peak memory 201800 kb
Host smart-8104b71d-96fa-43e3-82af-55e5bbe073e2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788538007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.2788538007
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.265063714
Short name T861
Test name
Test status
Simulation time 8285939135 ps
CPU time 6.9 seconds
Started Jul 21 05:39:38 PM PDT 24
Finished Jul 21 05:39:47 PM PDT 24
Peak memory 201768 kb
Host smart-b93a0998-ebc8-40b8-b933-6e0de977ed22
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265063714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_in
tg_err.265063714
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.3929686467
Short name T809
Test name
Test status
Simulation time 534225320 ps
CPU time 1.51 seconds
Started Jul 21 05:39:30 PM PDT 24
Finished Jul 21 05:39:33 PM PDT 24
Peak memory 201576 kb
Host smart-c5c20f62-b28a-4ac7-ad0e-39a31fabcecc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929686467 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.3929686467
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.3861849896
Short name T807
Test name
Test status
Simulation time 549104613 ps
CPU time 0.89 seconds
Started Jul 21 05:39:32 PM PDT 24
Finished Jul 21 05:39:34 PM PDT 24
Peak memory 201436 kb
Host smart-4d5242a0-7a4c-4118-ae17-41080c326041
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861849896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.3861849896
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.1916593843
Short name T808
Test name
Test status
Simulation time 476329111 ps
CPU time 1.75 seconds
Started Jul 21 05:39:31 PM PDT 24
Finished Jul 21 05:39:34 PM PDT 24
Peak memory 201412 kb
Host smart-5ace1cc2-434c-404c-9f97-d26b7c488c18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916593843 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.1916593843
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.3075782566
Short name T114
Test name
Test status
Simulation time 4596448051 ps
CPU time 15.23 seconds
Started Jul 21 05:39:30 PM PDT 24
Finished Jul 21 05:39:47 PM PDT 24
Peak memory 201896 kb
Host smart-253e1371-8e6c-4cd6-8cae-f24aada96671
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075782566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_
ctrl_same_csr_outstanding.3075782566
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.3980491342
Short name T907
Test name
Test status
Simulation time 537136456 ps
CPU time 2.53 seconds
Started Jul 21 05:39:35 PM PDT 24
Finished Jul 21 05:39:39 PM PDT 24
Peak memory 201804 kb
Host smart-f82a8bee-8a1e-462c-997c-60a576968577
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980491342 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.3980491342
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.3683929720
Short name T851
Test name
Test status
Simulation time 8610269986 ps
CPU time 6.14 seconds
Started Jul 21 05:39:35 PM PDT 24
Finished Jul 21 05:39:43 PM PDT 24
Peak memory 201700 kb
Host smart-021ca2b0-83ec-4741-8050-0659a50c9ae5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683929720 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_i
ntg_err.3683929720
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.3333048998
Short name T841
Test name
Test status
Simulation time 562441828 ps
CPU time 2.04 seconds
Started Jul 21 05:39:35 PM PDT 24
Finished Jul 21 05:39:39 PM PDT 24
Peak memory 201580 kb
Host smart-62ab7f5d-6149-4796-b0c9-d09a6444e656
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333048998 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.3333048998
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.2003526533
Short name T818
Test name
Test status
Simulation time 437012006 ps
CPU time 0.97 seconds
Started Jul 21 05:39:30 PM PDT 24
Finished Jul 21 05:39:31 PM PDT 24
Peak memory 201456 kb
Host smart-9533794f-5e0b-4738-abf4-369017b4f4c8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003526533 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.2003526533
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.3533990162
Short name T916
Test name
Test status
Simulation time 364009535 ps
CPU time 1.5 seconds
Started Jul 21 05:39:33 PM PDT 24
Finished Jul 21 05:39:35 PM PDT 24
Peak memory 201444 kb
Host smart-b21a7a31-4d6c-42b8-b317-bb374ddb58d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533990162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.3533990162
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.1919033610
Short name T911
Test name
Test status
Simulation time 4757481360 ps
CPU time 11.58 seconds
Started Jul 21 05:39:38 PM PDT 24
Finished Jul 21 05:39:52 PM PDT 24
Peak memory 201748 kb
Host smart-2807c52e-937b-452e-8453-6803a705cf2e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919033610 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_
ctrl_same_csr_outstanding.1919033610
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.2957179719
Short name T57
Test name
Test status
Simulation time 667379042 ps
CPU time 2.25 seconds
Started Jul 21 05:39:30 PM PDT 24
Finished Jul 21 05:39:33 PM PDT 24
Peak memory 201780 kb
Host smart-da3cd396-7707-4edc-bb96-bdfff69e03ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957179719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.2957179719
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.3426873666
Short name T854
Test name
Test status
Simulation time 4002709153 ps
CPU time 9.98 seconds
Started Jul 21 05:39:29 PM PDT 24
Finished Jul 21 05:39:40 PM PDT 24
Peak memory 201836 kb
Host smart-969e9607-6f27-418d-bd90-0987b76a0895
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426873666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_i
ntg_err.3426873666
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.908402233
Short name T79
Test name
Test status
Simulation time 511006881 ps
CPU time 1.89 seconds
Started Jul 21 05:39:34 PM PDT 24
Finished Jul 21 05:39:37 PM PDT 24
Peak memory 201580 kb
Host smart-17a00c23-6e3d-4b32-8469-8ec342a202d4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908402233 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.908402233
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.3778102671
Short name T111
Test name
Test status
Simulation time 426758553 ps
CPU time 1.17 seconds
Started Jul 21 05:39:36 PM PDT 24
Finished Jul 21 05:39:38 PM PDT 24
Peak memory 201436 kb
Host smart-3d55e312-4f8a-43d6-bbf8-09d6f523d7c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778102671 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.3778102671
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.1966811595
Short name T801
Test name
Test status
Simulation time 432688290 ps
CPU time 0.87 seconds
Started Jul 21 05:39:33 PM PDT 24
Finished Jul 21 05:39:35 PM PDT 24
Peak memory 201352 kb
Host smart-b0b72e2c-b7fa-4ae4-a1ee-f6a7ab7c67a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966811595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.1966811595
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.1554312180
Short name T816
Test name
Test status
Simulation time 4319125862 ps
CPU time 3.28 seconds
Started Jul 21 05:39:30 PM PDT 24
Finished Jul 21 05:39:34 PM PDT 24
Peak memory 201836 kb
Host smart-63373c2b-d94a-443e-971a-5ea1a6669fcf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554312180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_
ctrl_same_csr_outstanding.1554312180
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.3699358863
Short name T873
Test name
Test status
Simulation time 459097542 ps
CPU time 3.44 seconds
Started Jul 21 05:39:38 PM PDT 24
Finished Jul 21 05:39:43 PM PDT 24
Peak memory 201824 kb
Host smart-19821b76-d5f1-40b1-a1f5-4018ed4df320
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699358863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.3699358863
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.522381326
Short name T46
Test name
Test status
Simulation time 4412164108 ps
CPU time 6.48 seconds
Started Jul 21 05:39:35 PM PDT 24
Finished Jul 21 05:39:43 PM PDT 24
Peak memory 201724 kb
Host smart-380ee8bf-a4e6-4579-ba81-749769593148
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522381326 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_in
tg_err.522381326
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.1617384710
Short name T869
Test name
Test status
Simulation time 423690784 ps
CPU time 1.28 seconds
Started Jul 21 05:39:36 PM PDT 24
Finished Jul 21 05:39:38 PM PDT 24
Peak memory 201560 kb
Host smart-8fad29fb-d878-4639-83e6-8c58817a06d6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617384710 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.1617384710
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.3941083156
Short name T870
Test name
Test status
Simulation time 523648868 ps
CPU time 0.98 seconds
Started Jul 21 05:39:34 PM PDT 24
Finished Jul 21 05:39:36 PM PDT 24
Peak memory 201460 kb
Host smart-d43d74b3-42df-4334-bee6-5d3c2b4850a3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941083156 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.3941083156
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.3658287403
Short name T822
Test name
Test status
Simulation time 504462910 ps
CPU time 0.9 seconds
Started Jul 21 05:39:31 PM PDT 24
Finished Jul 21 05:39:34 PM PDT 24
Peak memory 201436 kb
Host smart-1d544f22-e664-4a00-855d-f042b8409e76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658287403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.3658287403
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.3240338064
Short name T850
Test name
Test status
Simulation time 2108962688 ps
CPU time 4.73 seconds
Started Jul 21 05:39:33 PM PDT 24
Finished Jul 21 05:39:39 PM PDT 24
Peak memory 201468 kb
Host smart-43f526af-4566-495f-b6af-dbb211a5b1a0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240338064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_
ctrl_same_csr_outstanding.3240338064
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.1207295690
Short name T843
Test name
Test status
Simulation time 7890974509 ps
CPU time 6.41 seconds
Started Jul 21 05:39:37 PM PDT 24
Finished Jul 21 05:39:45 PM PDT 24
Peak memory 201672 kb
Host smart-9b0537c5-f738-4772-9e2e-a44ab16260a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207295690 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_i
ntg_err.1207295690
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.1485862548
Short name T831
Test name
Test status
Simulation time 603647756 ps
CPU time 1.14 seconds
Started Jul 21 05:39:31 PM PDT 24
Finished Jul 21 05:39:34 PM PDT 24
Peak memory 201576 kb
Host smart-afa2c905-ad37-418f-b1ab-8d2e51781cce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485862548 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.1485862548
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.3171797345
Short name T849
Test name
Test status
Simulation time 481190462 ps
CPU time 1.1 seconds
Started Jul 21 05:39:33 PM PDT 24
Finished Jul 21 05:39:35 PM PDT 24
Peak memory 201448 kb
Host smart-fc34cbc8-52f8-4582-a6d3-bd7e43408946
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171797345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.3171797345
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.1946601413
Short name T826
Test name
Test status
Simulation time 374938331 ps
CPU time 1.48 seconds
Started Jul 21 05:39:34 PM PDT 24
Finished Jul 21 05:39:36 PM PDT 24
Peak memory 201452 kb
Host smart-663fd296-700f-4e43-ad1b-3b8002571df0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946601413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.1946601413
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.2464430297
Short name T837
Test name
Test status
Simulation time 2963467631 ps
CPU time 5.97 seconds
Started Jul 21 05:39:32 PM PDT 24
Finished Jul 21 05:39:39 PM PDT 24
Peak memory 201508 kb
Host smart-2a66d8ab-aca0-4ea9-9385-aac03fba6b25
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464430297 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_
ctrl_same_csr_outstanding.2464430297
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.2018378920
Short name T59
Test name
Test status
Simulation time 814022371 ps
CPU time 2.23 seconds
Started Jul 21 05:39:34 PM PDT 24
Finished Jul 21 05:39:37 PM PDT 24
Peak memory 201752 kb
Host smart-31266a68-4ee2-4979-b97b-1f8fb29f7eae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018378920 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.2018378920
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.2301825069
Short name T880
Test name
Test status
Simulation time 7882016799 ps
CPU time 11.08 seconds
Started Jul 21 05:39:33 PM PDT 24
Finished Jul 21 05:39:46 PM PDT 24
Peak memory 201780 kb
Host smart-abb46ce0-6aca-4d9a-ace2-b886bb725d74
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301825069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_i
ntg_err.2301825069
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.1482922013
Short name T853
Test name
Test status
Simulation time 462014833 ps
CPU time 1.34 seconds
Started Jul 21 05:39:34 PM PDT 24
Finished Jul 21 05:39:36 PM PDT 24
Peak memory 201576 kb
Host smart-d59075ad-dadb-4ff7-9adb-987fdab1ff57
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482922013 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.1482922013
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.995206321
Short name T914
Test name
Test status
Simulation time 409705499 ps
CPU time 1.3 seconds
Started Jul 21 05:39:33 PM PDT 24
Finished Jul 21 05:39:35 PM PDT 24
Peak memory 201408 kb
Host smart-6a9eba83-582e-41d1-8afd-26dfec79a371
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995206321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.995206321
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.2778915635
Short name T917
Test name
Test status
Simulation time 321957700 ps
CPU time 0.81 seconds
Started Jul 21 05:39:34 PM PDT 24
Finished Jul 21 05:39:36 PM PDT 24
Peak memory 201396 kb
Host smart-9ec87af0-fd2e-4dee-93ea-10838c8d8b96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778915635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.2778915635
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.3893218421
Short name T112
Test name
Test status
Simulation time 4452951772 ps
CPU time 4.49 seconds
Started Jul 21 05:39:30 PM PDT 24
Finished Jul 21 05:39:35 PM PDT 24
Peak memory 201868 kb
Host smart-804854e2-fdc9-424e-8c4d-22277057fd5e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893218421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_
ctrl_same_csr_outstanding.3893218421
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.3055732787
Short name T912
Test name
Test status
Simulation time 408969552 ps
CPU time 2.03 seconds
Started Jul 21 05:39:38 PM PDT 24
Finished Jul 21 05:39:42 PM PDT 24
Peak memory 201744 kb
Host smart-15ad2385-4b07-471c-93e1-4e42ba31f3fd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055732787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.3055732787
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.1347144766
Short name T860
Test name
Test status
Simulation time 8494117135 ps
CPU time 12.52 seconds
Started Jul 21 05:39:37 PM PDT 24
Finished Jul 21 05:39:52 PM PDT 24
Peak memory 201704 kb
Host smart-49277341-e919-4dc6-9c05-093d4afac7a8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347144766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_i
ntg_err.1347144766
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.3932439882
Short name T882
Test name
Test status
Simulation time 452590601 ps
CPU time 1.06 seconds
Started Jul 21 05:39:31 PM PDT 24
Finished Jul 21 05:39:33 PM PDT 24
Peak memory 201588 kb
Host smart-872ffd15-2956-4f68-bd3d-08a3537c7a1a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932439882 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.3932439882
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.1005980680
Short name T99
Test name
Test status
Simulation time 337898338 ps
CPU time 0.92 seconds
Started Jul 21 05:39:36 PM PDT 24
Finished Jul 21 05:39:38 PM PDT 24
Peak memory 201436 kb
Host smart-9cb4d467-3547-4e9f-8189-c9e07e05c1c7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005980680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.1005980680
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.4108967297
Short name T814
Test name
Test status
Simulation time 469964664 ps
CPU time 1.62 seconds
Started Jul 21 05:39:33 PM PDT 24
Finished Jul 21 05:39:36 PM PDT 24
Peak memory 201444 kb
Host smart-96e31fb9-348d-408e-81f4-e88bd10a89b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108967297 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.4108967297
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.145734251
Short name T876
Test name
Test status
Simulation time 2584027395 ps
CPU time 5.43 seconds
Started Jul 21 05:39:36 PM PDT 24
Finished Jul 21 05:39:43 PM PDT 24
Peak memory 201788 kb
Host smart-343eee37-5def-4292-8008-10614c59f1a8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145734251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_c
trl_same_csr_outstanding.145734251
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.684230486
Short name T868
Test name
Test status
Simulation time 364528644 ps
CPU time 2.4 seconds
Started Jul 21 05:39:39 PM PDT 24
Finished Jul 21 05:39:43 PM PDT 24
Peak memory 210020 kb
Host smart-5c20d950-eacc-4a91-bdb0-46da945bd388
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684230486 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.684230486
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.2273882779
Short name T56
Test name
Test status
Simulation time 4285322576 ps
CPU time 11.3 seconds
Started Jul 21 05:39:34 PM PDT 24
Finished Jul 21 05:39:46 PM PDT 24
Peak memory 201764 kb
Host smart-2b686499-3dd5-47e0-b823-4340f7d33a2f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273882779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_i
ntg_err.2273882779
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.3284651717
Short name T103
Test name
Test status
Simulation time 446894621 ps
CPU time 2.51 seconds
Started Jul 21 05:39:32 PM PDT 24
Finished Jul 21 05:39:36 PM PDT 24
Peak memory 201600 kb
Host smart-93024048-98e3-4052-8193-1cae1bf90878
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284651717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alia
sing.3284651717
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.674586862
Short name T109
Test name
Test status
Simulation time 30690089929 ps
CPU time 74.73 seconds
Started Jul 21 05:39:19 PM PDT 24
Finished Jul 21 05:40:35 PM PDT 24
Peak memory 201640 kb
Host smart-a5839eb6-0bcf-4306-93b6-e92070377e92
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674586862 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_b
ash.674586862
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.206748322
Short name T835
Test name
Test status
Simulation time 848516021 ps
CPU time 2.09 seconds
Started Jul 21 05:39:28 PM PDT 24
Finished Jul 21 05:39:31 PM PDT 24
Peak memory 201432 kb
Host smart-6b0b5ca0-4040-4699-b3dc-f2fbdaef0957
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206748322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_re
set.206748322
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.75727912
Short name T915
Test name
Test status
Simulation time 625906033 ps
CPU time 2.53 seconds
Started Jul 21 05:39:21 PM PDT 24
Finished Jul 21 05:39:24 PM PDT 24
Peak memory 201628 kb
Host smart-cd07f263-ceac-4d85-b2fb-9ed5d9825532
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75727912 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.75727912
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.3361599830
Short name T100
Test name
Test status
Simulation time 403366116 ps
CPU time 1.68 seconds
Started Jul 21 05:39:29 PM PDT 24
Finished Jul 21 05:39:31 PM PDT 24
Peak memory 201432 kb
Host smart-3578bf15-7326-4346-a009-6ba0282ee5df
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361599830 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.3361599830
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.1439910100
Short name T798
Test name
Test status
Simulation time 519490149 ps
CPU time 1.26 seconds
Started Jul 21 05:39:28 PM PDT 24
Finished Jul 21 05:39:30 PM PDT 24
Peak memory 201416 kb
Host smart-7a29c194-21ff-484d-918d-e112a10838ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439910100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.1439910100
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.3140696249
Short name T893
Test name
Test status
Simulation time 2630851547 ps
CPU time 2.33 seconds
Started Jul 21 05:39:25 PM PDT 24
Finished Jul 21 05:39:28 PM PDT 24
Peak memory 201604 kb
Host smart-f09a2a1b-bebe-42e2-83fc-ae3319fdda2b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140696249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_c
trl_same_csr_outstanding.3140696249
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.25598458
Short name T885
Test name
Test status
Simulation time 402863127 ps
CPU time 2.27 seconds
Started Jul 21 05:39:24 PM PDT 24
Finished Jul 21 05:39:27 PM PDT 24
Peak memory 201732 kb
Host smart-b7117ba1-e215-452a-96d4-080fd30adb84
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25598458 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.25598458
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.1885904466
Short name T881
Test name
Test status
Simulation time 8207590234 ps
CPU time 20.92 seconds
Started Jul 21 05:39:24 PM PDT 24
Finished Jul 21 05:39:45 PM PDT 24
Peak memory 201764 kb
Host smart-dcd5b117-a28a-4403-a520-36160f8b799c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885904466 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_in
tg_err.1885904466
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.3366942390
Short name T827
Test name
Test status
Simulation time 522905260 ps
CPU time 1.84 seconds
Started Jul 21 05:39:35 PM PDT 24
Finished Jul 21 05:39:38 PM PDT 24
Peak memory 201336 kb
Host smart-cd41f80c-52b7-417c-9c48-7adf179dc168
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366942390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.3366942390
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.327607401
Short name T820
Test name
Test status
Simulation time 359028726 ps
CPU time 1.03 seconds
Started Jul 21 05:39:30 PM PDT 24
Finished Jul 21 05:39:32 PM PDT 24
Peak memory 201412 kb
Host smart-6aa29930-65ee-4668-8e7b-4a6cefdacd1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327607401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.327607401
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.1276197011
Short name T892
Test name
Test status
Simulation time 500013281 ps
CPU time 1.79 seconds
Started Jul 21 05:39:39 PM PDT 24
Finished Jul 21 05:39:42 PM PDT 24
Peak memory 201452 kb
Host smart-36ff8977-328f-4bcb-a905-adb01206e4ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276197011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.1276197011
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.1286681728
Short name T884
Test name
Test status
Simulation time 377279192 ps
CPU time 1.62 seconds
Started Jul 21 05:39:46 PM PDT 24
Finished Jul 21 05:39:49 PM PDT 24
Peak memory 201644 kb
Host smart-cffd206a-e531-4781-808a-a27547cc784e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286681728 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.1286681728
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.584208005
Short name T802
Test name
Test status
Simulation time 461642222 ps
CPU time 0.74 seconds
Started Jul 21 05:39:36 PM PDT 24
Finished Jul 21 05:39:38 PM PDT 24
Peak memory 201372 kb
Host smart-a537f0a0-0a9e-4531-a836-59a7884c1eed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584208005 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.584208005
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.2052770229
Short name T887
Test name
Test status
Simulation time 399839827 ps
CPU time 1.29 seconds
Started Jul 21 05:39:42 PM PDT 24
Finished Jul 21 05:39:44 PM PDT 24
Peak memory 201460 kb
Host smart-b5ac3397-87ec-43a8-8753-ad684094ea9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052770229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.2052770229
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.2057435612
Short name T829
Test name
Test status
Simulation time 373279667 ps
CPU time 1.47 seconds
Started Jul 21 05:39:45 PM PDT 24
Finished Jul 21 05:39:48 PM PDT 24
Peak memory 201416 kb
Host smart-790b4c81-fb76-4d93-a140-b35e4d70f36c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057435612 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.2057435612
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.3367461824
Short name T821
Test name
Test status
Simulation time 377050751 ps
CPU time 1.05 seconds
Started Jul 21 05:39:36 PM PDT 24
Finished Jul 21 05:39:39 PM PDT 24
Peak memory 201488 kb
Host smart-b78743bd-1e8f-47a4-8723-ef2f7a12ce88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367461824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.3367461824
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.197156891
Short name T813
Test name
Test status
Simulation time 390144977 ps
CPU time 0.89 seconds
Started Jul 21 05:39:36 PM PDT 24
Finished Jul 21 05:39:38 PM PDT 24
Peak memory 201392 kb
Host smart-67a7b515-2ef7-4d9c-9268-9c12d2cc7157
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197156891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.197156891
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.2930889297
Short name T810
Test name
Test status
Simulation time 309150519 ps
CPU time 1.36 seconds
Started Jul 21 05:39:45 PM PDT 24
Finished Jul 21 05:39:48 PM PDT 24
Peak memory 201420 kb
Host smart-2d6f448a-3cac-460f-a96f-91257cbffffd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930889297 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.2930889297
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.1313788965
Short name T107
Test name
Test status
Simulation time 1000566742 ps
CPU time 4.23 seconds
Started Jul 21 05:39:31 PM PDT 24
Finished Jul 21 05:39:37 PM PDT 24
Peak memory 201608 kb
Host smart-0854f0f9-0411-4c8b-a4ad-1192d9e6291c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313788965 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alia
sing.1313788965
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.3903611532
Short name T43
Test name
Test status
Simulation time 26643151360 ps
CPU time 28.7 seconds
Started Jul 21 05:39:18 PM PDT 24
Finished Jul 21 05:39:48 PM PDT 24
Peak memory 201776 kb
Host smart-59bc464c-d453-4626-a9cc-d7cae3c981d8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903611532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_
bash.3903611532
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.3380180929
Short name T110
Test name
Test status
Simulation time 1045056798 ps
CPU time 3.24 seconds
Started Jul 21 05:39:23 PM PDT 24
Finished Jul 21 05:39:27 PM PDT 24
Peak memory 201476 kb
Host smart-727833d7-c9fc-4e4e-9b30-f70dff9fe652
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380180929 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_r
eset.3380180929
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.864704148
Short name T855
Test name
Test status
Simulation time 508159491 ps
CPU time 1.95 seconds
Started Jul 21 05:39:23 PM PDT 24
Finished Jul 21 05:39:26 PM PDT 24
Peak memory 201628 kb
Host smart-b5988da4-5131-4ef0-898f-30059145c199
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864704148 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.864704148
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.2126039547
Short name T889
Test name
Test status
Simulation time 471953834 ps
CPU time 0.92 seconds
Started Jul 21 05:39:23 PM PDT 24
Finished Jul 21 05:39:24 PM PDT 24
Peak memory 201488 kb
Host smart-ce7525bd-2170-4749-80fe-299af91b49d2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126039547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.2126039547
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.2650686223
Short name T804
Test name
Test status
Simulation time 516247757 ps
CPU time 1.23 seconds
Started Jul 21 05:39:25 PM PDT 24
Finished Jul 21 05:39:27 PM PDT 24
Peak memory 201448 kb
Host smart-77b94e0d-ebda-4a99-9a53-6b4359ba07a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650686223 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.2650686223
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.4221724789
Short name T44
Test name
Test status
Simulation time 2437274437 ps
CPU time 3.45 seconds
Started Jul 21 05:39:19 PM PDT 24
Finished Jul 21 05:39:23 PM PDT 24
Peak memory 201568 kb
Host smart-fa4c3d41-8a84-45c0-a388-b92376383597
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221724789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_c
trl_same_csr_outstanding.4221724789
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.169670602
Short name T852
Test name
Test status
Simulation time 512537286 ps
CPU time 1.85 seconds
Started Jul 21 05:39:24 PM PDT 24
Finished Jul 21 05:39:26 PM PDT 24
Peak memory 217896 kb
Host smart-51acd98e-af6a-400e-a9ff-b9468359894a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169670602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.169670602
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.3303835410
Short name T63
Test name
Test status
Simulation time 8810763519 ps
CPU time 12.13 seconds
Started Jul 21 05:39:21 PM PDT 24
Finished Jul 21 05:39:34 PM PDT 24
Peak memory 201780 kb
Host smart-e15463ad-7f7d-4e8d-8ad5-164df4c811ac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303835410 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_in
tg_err.3303835410
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.2917575114
Short name T806
Test name
Test status
Simulation time 312781982 ps
CPU time 1.28 seconds
Started Jul 21 05:39:36 PM PDT 24
Finished Jul 21 05:39:39 PM PDT 24
Peak memory 201448 kb
Host smart-125ee3b3-01be-4f54-8163-77bdad396070
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917575114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.2917575114
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.33499070
Short name T874
Test name
Test status
Simulation time 513264439 ps
CPU time 0.91 seconds
Started Jul 21 05:39:41 PM PDT 24
Finished Jul 21 05:39:42 PM PDT 24
Peak memory 201384 kb
Host smart-617d59a6-9e36-4d0f-9274-d10ae1cb20e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33499070 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.33499070
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.2615649926
Short name T805
Test name
Test status
Simulation time 530978061 ps
CPU time 1.45 seconds
Started Jul 21 05:39:35 PM PDT 24
Finished Jul 21 05:39:38 PM PDT 24
Peak memory 201456 kb
Host smart-59831731-630c-490c-9ae9-c41438a1086a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615649926 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.2615649926
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.103827379
Short name T864
Test name
Test status
Simulation time 308654947 ps
CPU time 1.27 seconds
Started Jul 21 05:39:46 PM PDT 24
Finished Jul 21 05:39:48 PM PDT 24
Peak memory 201648 kb
Host smart-aa74c188-8499-4d6b-8aca-ba3c4269d6ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103827379 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.103827379
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.3666085617
Short name T898
Test name
Test status
Simulation time 320097678 ps
CPU time 1.04 seconds
Started Jul 21 05:39:46 PM PDT 24
Finished Jul 21 05:39:48 PM PDT 24
Peak memory 201644 kb
Host smart-25b52dc6-3251-47c0-bd26-fc265b965a00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666085617 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.3666085617
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.1418202239
Short name T830
Test name
Test status
Simulation time 476326054 ps
CPU time 0.82 seconds
Started Jul 21 05:39:39 PM PDT 24
Finished Jul 21 05:39:41 PM PDT 24
Peak memory 201432 kb
Host smart-1d579d45-1558-454b-afcd-698a47854b09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418202239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.1418202239
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.1331010034
Short name T871
Test name
Test status
Simulation time 325433007 ps
CPU time 1.13 seconds
Started Jul 21 05:39:37 PM PDT 24
Finished Jul 21 05:39:41 PM PDT 24
Peak memory 201508 kb
Host smart-61adfea1-cbba-4f8d-98dd-3fad7184e4eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331010034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.1331010034
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.1545604171
Short name T825
Test name
Test status
Simulation time 504233091 ps
CPU time 0.97 seconds
Started Jul 21 05:39:45 PM PDT 24
Finished Jul 21 05:39:47 PM PDT 24
Peak memory 201420 kb
Host smart-8d27f532-7796-4ceb-8cf3-b0d321a6bed1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545604171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.1545604171
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.2020220597
Short name T848
Test name
Test status
Simulation time 465032468 ps
CPU time 1.71 seconds
Started Jul 21 05:39:36 PM PDT 24
Finished Jul 21 05:39:40 PM PDT 24
Peak memory 201448 kb
Host smart-db15e864-ab12-4620-92d4-442dd574546c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020220597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.2020220597
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.4019495348
Short name T811
Test name
Test status
Simulation time 390706262 ps
CPU time 0.84 seconds
Started Jul 21 05:39:36 PM PDT 24
Finished Jul 21 05:39:39 PM PDT 24
Peak memory 201416 kb
Host smart-4910cce4-1a17-41f8-b42d-e71069072a76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019495348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.4019495348
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.1682755396
Short name T883
Test name
Test status
Simulation time 893736422 ps
CPU time 4.26 seconds
Started Jul 21 05:39:20 PM PDT 24
Finished Jul 21 05:39:25 PM PDT 24
Peak memory 201576 kb
Host smart-92bce428-668a-4e81-ab92-99de5d5da848
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682755396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alia
sing.1682755396
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.2957592287
Short name T104
Test name
Test status
Simulation time 43384959944 ps
CPU time 41.91 seconds
Started Jul 21 05:39:27 PM PDT 24
Finished Jul 21 05:40:10 PM PDT 24
Peak memory 201748 kb
Host smart-9d13e7e5-2a11-427f-ade7-360acb31b1e2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957592287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_
bash.2957592287
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.634125211
Short name T108
Test name
Test status
Simulation time 875496085 ps
CPU time 1.75 seconds
Started Jul 21 05:39:26 PM PDT 24
Finished Jul 21 05:39:28 PM PDT 24
Peak memory 201356 kb
Host smart-a0416280-e199-4b33-b6b6-15328945b20b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634125211 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_re
set.634125211
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.2542784212
Short name T823
Test name
Test status
Simulation time 534901328 ps
CPU time 1.48 seconds
Started Jul 21 05:39:29 PM PDT 24
Finished Jul 21 05:39:31 PM PDT 24
Peak memory 201596 kb
Host smart-1e6e7332-dada-4020-8054-be96f4f272dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542784212 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.2542784212
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.1969535815
Short name T106
Test name
Test status
Simulation time 377399171 ps
CPU time 0.88 seconds
Started Jul 21 05:39:23 PM PDT 24
Finished Jul 21 05:39:25 PM PDT 24
Peak memory 201464 kb
Host smart-3ee6aee0-aa76-4d7e-a384-c819e208a0d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969535815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.1969535815
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.2445124671
Short name T897
Test name
Test status
Simulation time 394248293 ps
CPU time 0.84 seconds
Started Jul 21 05:39:23 PM PDT 24
Finished Jul 21 05:39:25 PM PDT 24
Peak memory 201364 kb
Host smart-e6d7afcc-698b-4c9d-97d5-861b2ce3925d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445124671 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.2445124671
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.1687116492
Short name T113
Test name
Test status
Simulation time 3843854808 ps
CPU time 3.1 seconds
Started Jul 21 05:39:23 PM PDT 24
Finished Jul 21 05:39:27 PM PDT 24
Peak memory 201740 kb
Host smart-3962ceee-024d-4d78-84d0-98a9462989b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687116492 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_c
trl_same_csr_outstanding.1687116492
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.1998575432
Short name T906
Test name
Test status
Simulation time 783274885 ps
CPU time 2.42 seconds
Started Jul 21 05:39:25 PM PDT 24
Finished Jul 21 05:39:28 PM PDT 24
Peak memory 201800 kb
Host smart-1b5b3832-fa25-4b0a-ab23-d23e2300a605
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998575432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.1998575432
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.1926676274
Short name T842
Test name
Test status
Simulation time 382976201 ps
CPU time 0.87 seconds
Started Jul 21 05:39:35 PM PDT 24
Finished Jul 21 05:39:37 PM PDT 24
Peak memory 201440 kb
Host smart-ddc3c02c-9efc-444e-b3d6-cc5a92929516
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926676274 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.1926676274
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.3714513553
Short name T877
Test name
Test status
Simulation time 357758420 ps
CPU time 1.44 seconds
Started Jul 21 05:39:37 PM PDT 24
Finished Jul 21 05:39:40 PM PDT 24
Peak memory 201476 kb
Host smart-3fdcc50e-84d7-4de3-a520-f90326eb866d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714513553 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.3714513553
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.1601880951
Short name T838
Test name
Test status
Simulation time 473967377 ps
CPU time 1.78 seconds
Started Jul 21 05:39:44 PM PDT 24
Finished Jul 21 05:39:46 PM PDT 24
Peak memory 201420 kb
Host smart-c92244e3-8bcb-483c-bbe2-29b1418cc2d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601880951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.1601880951
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.3019968648
Short name T833
Test name
Test status
Simulation time 503245992 ps
CPU time 0.99 seconds
Started Jul 21 05:39:37 PM PDT 24
Finished Jul 21 05:39:39 PM PDT 24
Peak memory 201504 kb
Host smart-b0bd20b2-0237-48d1-b2d0-fce3748c0f29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019968648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.3019968648
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.492575428
Short name T910
Test name
Test status
Simulation time 301588473 ps
CPU time 0.94 seconds
Started Jul 21 05:39:38 PM PDT 24
Finished Jul 21 05:39:41 PM PDT 24
Peak memory 201432 kb
Host smart-ef07e966-1c74-46b8-aa3a-a256128cfe81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492575428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.492575428
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.33714052
Short name T879
Test name
Test status
Simulation time 464585070 ps
CPU time 1.71 seconds
Started Jul 21 05:39:38 PM PDT 24
Finished Jul 21 05:39:41 PM PDT 24
Peak memory 201328 kb
Host smart-335a795b-3e74-460c-97d2-2cd79f6cdc5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33714052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.33714052
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.4280136587
Short name T834
Test name
Test status
Simulation time 524287130 ps
CPU time 1.82 seconds
Started Jul 21 05:39:42 PM PDT 24
Finished Jul 21 05:39:46 PM PDT 24
Peak memory 201420 kb
Host smart-c5be6dfc-4e22-4586-9c71-9f6c3d0a25c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280136587 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.4280136587
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.4180587636
Short name T803
Test name
Test status
Simulation time 507675315 ps
CPU time 1.2 seconds
Started Jul 21 05:39:35 PM PDT 24
Finished Jul 21 05:39:38 PM PDT 24
Peak memory 201452 kb
Host smart-40b2e896-480e-462c-a939-d8135d66035f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180587636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.4180587636
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.2812172292
Short name T890
Test name
Test status
Simulation time 401181375 ps
CPU time 1.13 seconds
Started Jul 21 05:39:39 PM PDT 24
Finished Jul 21 05:39:41 PM PDT 24
Peak memory 201352 kb
Host smart-44af0e7b-74dd-4575-95ec-ea5efa358b2c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812172292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.2812172292
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.2845904034
Short name T812
Test name
Test status
Simulation time 498830839 ps
CPU time 1.69 seconds
Started Jul 21 05:39:45 PM PDT 24
Finished Jul 21 05:39:48 PM PDT 24
Peak memory 201628 kb
Host smart-9b1a013e-0645-44c9-bf32-69fe37d018ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845904034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.2845904034
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.3105857131
Short name T891
Test name
Test status
Simulation time 553560208 ps
CPU time 1.6 seconds
Started Jul 21 05:39:27 PM PDT 24
Finished Jul 21 05:39:30 PM PDT 24
Peak memory 201608 kb
Host smart-ee68159e-114f-4bc9-97a0-352f35a2497f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105857131 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.3105857131
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.3600892471
Short name T902
Test name
Test status
Simulation time 566927936 ps
CPU time 2.15 seconds
Started Jul 21 05:39:27 PM PDT 24
Finished Jul 21 05:39:30 PM PDT 24
Peak memory 201372 kb
Host smart-fae03b11-f084-40d5-8f78-87688f1d527d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600892471 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.3600892471
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.1993695949
Short name T867
Test name
Test status
Simulation time 478732047 ps
CPU time 1.17 seconds
Started Jul 21 05:39:27 PM PDT 24
Finished Jul 21 05:39:29 PM PDT 24
Peak memory 201392 kb
Host smart-380cd286-bc61-43b6-bb84-51b4992788d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993695949 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.1993695949
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.3821906042
Short name T908
Test name
Test status
Simulation time 2225309198 ps
CPU time 5.31 seconds
Started Jul 21 05:39:31 PM PDT 24
Finished Jul 21 05:39:38 PM PDT 24
Peak memory 201592 kb
Host smart-3ab7d38d-5917-4771-a249-33243717d012
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821906042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_c
trl_same_csr_outstanding.3821906042
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.3154900608
Short name T845
Test name
Test status
Simulation time 904151824 ps
CPU time 3.27 seconds
Started Jul 21 05:39:23 PM PDT 24
Finished Jul 21 05:39:27 PM PDT 24
Peak memory 218128 kb
Host smart-0a1f79a7-77d0-473f-8385-50051be45211
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154900608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.3154900608
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.948854415
Short name T824
Test name
Test status
Simulation time 596068851 ps
CPU time 2.33 seconds
Started Jul 21 05:39:28 PM PDT 24
Finished Jul 21 05:39:31 PM PDT 24
Peak memory 201520 kb
Host smart-1facf3d8-72bd-4df9-aaad-a57a6cfd00f8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948854415 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.948854415
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.2977160474
Short name T118
Test name
Test status
Simulation time 470316386 ps
CPU time 1.03 seconds
Started Jul 21 05:39:25 PM PDT 24
Finished Jul 21 05:39:26 PM PDT 24
Peak memory 201488 kb
Host smart-4b3b9f46-c52a-410c-ae51-9022583bb3ed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977160474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.2977160474
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.3092865206
Short name T799
Test name
Test status
Simulation time 503615990 ps
CPU time 1.2 seconds
Started Jul 21 05:39:28 PM PDT 24
Finished Jul 21 05:39:30 PM PDT 24
Peak memory 201452 kb
Host smart-b045a57e-d215-46e0-be43-e4aaa82d8ce5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092865206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.3092865206
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.3803130011
Short name T815
Test name
Test status
Simulation time 4571377895 ps
CPU time 3.81 seconds
Started Jul 21 05:39:24 PM PDT 24
Finished Jul 21 05:39:28 PM PDT 24
Peak memory 201828 kb
Host smart-7114a68c-6f26-4f7d-81a9-80c19cd949b6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803130011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_c
trl_same_csr_outstanding.3803130011
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.4028500000
Short name T862
Test name
Test status
Simulation time 712382802 ps
CPU time 1.63 seconds
Started Jul 21 05:39:35 PM PDT 24
Finished Jul 21 05:39:37 PM PDT 24
Peak memory 201776 kb
Host smart-bc0c1a79-aaf7-4872-b7bc-c0a99241ebb4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028500000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.4028500000
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.741348799
Short name T863
Test name
Test status
Simulation time 8940994919 ps
CPU time 7.86 seconds
Started Jul 21 05:39:29 PM PDT 24
Finished Jul 21 05:39:38 PM PDT 24
Peak memory 201796 kb
Host smart-fa8551e1-cad1-442f-88d8-bbd16ef84736
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741348799 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_int
g_err.741348799
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.2718295221
Short name T817
Test name
Test status
Simulation time 559424407 ps
CPU time 2.19 seconds
Started Jul 21 05:39:28 PM PDT 24
Finished Jul 21 05:39:32 PM PDT 24
Peak memory 201516 kb
Host smart-9cab5b88-19e7-4a95-9d87-560f9be0d8bd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718295221 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.2718295221
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.4290589909
Short name T102
Test name
Test status
Simulation time 443700052 ps
CPU time 1.23 seconds
Started Jul 21 05:39:31 PM PDT 24
Finished Jul 21 05:39:33 PM PDT 24
Peak memory 201460 kb
Host smart-30ab37ad-d572-486c-bd0b-f7ee40ca3462
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290589909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.4290589909
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.4276428888
Short name T919
Test name
Test status
Simulation time 352972814 ps
CPU time 1.36 seconds
Started Jul 21 05:39:26 PM PDT 24
Finished Jul 21 05:39:27 PM PDT 24
Peak memory 201368 kb
Host smart-c9ca7b5d-0f3b-4757-9e85-c411e8fb8107
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276428888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.4276428888
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.1212146698
Short name T117
Test name
Test status
Simulation time 4406773245 ps
CPU time 6.06 seconds
Started Jul 21 05:39:29 PM PDT 24
Finished Jul 21 05:39:36 PM PDT 24
Peak memory 201784 kb
Host smart-fe694dba-2b6c-40e2-a1bd-73b6ed667e01
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212146698 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_c
trl_same_csr_outstanding.1212146698
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.2407921628
Short name T49
Test name
Test status
Simulation time 537133600 ps
CPU time 2.72 seconds
Started Jul 21 05:39:30 PM PDT 24
Finished Jul 21 05:39:34 PM PDT 24
Peak memory 201828 kb
Host smart-7e79b1e2-492e-4542-a15d-d4d1beba3ba2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407921628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.2407921628
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.2420383709
Short name T872
Test name
Test status
Simulation time 8391213638 ps
CPU time 19.7 seconds
Started Jul 21 05:39:29 PM PDT 24
Finished Jul 21 05:39:50 PM PDT 24
Peak memory 201836 kb
Host smart-f8186673-9586-4511-a4cb-a0ad4a0bfab1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420383709 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_in
tg_err.2420383709
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.526473725
Short name T847
Test name
Test status
Simulation time 574944860 ps
CPU time 1.27 seconds
Started Jul 21 05:39:28 PM PDT 24
Finished Jul 21 05:39:30 PM PDT 24
Peak memory 201584 kb
Host smart-97ad0bc7-f1a0-45a5-a8ea-73f8596ee4f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526473725 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.526473725
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.3233608685
Short name T918
Test name
Test status
Simulation time 347048752 ps
CPU time 1.25 seconds
Started Jul 21 05:39:30 PM PDT 24
Finished Jul 21 05:39:33 PM PDT 24
Peak memory 201400 kb
Host smart-e6a9944d-50cf-48d8-b0f1-115285dc2e07
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233608685 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.3233608685
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.2263104448
Short name T836
Test name
Test status
Simulation time 524895556 ps
CPU time 0.76 seconds
Started Jul 21 05:39:27 PM PDT 24
Finished Jul 21 05:39:28 PM PDT 24
Peak memory 201372 kb
Host smart-4105329c-62c5-49f6-a044-82b807a2f88b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263104448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.2263104448
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.1651466733
Short name T865
Test name
Test status
Simulation time 2582945834 ps
CPU time 4.94 seconds
Started Jul 21 05:39:35 PM PDT 24
Finished Jul 21 05:39:41 PM PDT 24
Peak memory 201584 kb
Host smart-a0248593-ab0d-4f10-a855-0d2a5a56a7c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651466733 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_c
trl_same_csr_outstanding.1651466733
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.1968335583
Short name T886
Test name
Test status
Simulation time 523766965 ps
CPU time 2.41 seconds
Started Jul 21 05:39:27 PM PDT 24
Finished Jul 21 05:39:30 PM PDT 24
Peak memory 201732 kb
Host smart-d8595271-356a-4faa-81e7-5d07286c78e2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968335583 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.1968335583
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.2040180591
Short name T47
Test name
Test status
Simulation time 4205817552 ps
CPU time 3.86 seconds
Started Jul 21 05:39:22 PM PDT 24
Finished Jul 21 05:39:26 PM PDT 24
Peak memory 201812 kb
Host smart-7d00db8a-1e21-44d3-8400-c918cf9983f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040180591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_in
tg_err.2040180591
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.2676009742
Short name T894
Test name
Test status
Simulation time 384638429 ps
CPU time 1.69 seconds
Started Jul 21 05:39:28 PM PDT 24
Finished Jul 21 05:39:31 PM PDT 24
Peak memory 201580 kb
Host smart-925668f4-9f81-43f3-b5e5-2e13eef54881
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676009742 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.2676009742
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.987750071
Short name T900
Test name
Test status
Simulation time 455698682 ps
CPU time 1.81 seconds
Started Jul 21 05:39:29 PM PDT 24
Finished Jul 21 05:39:31 PM PDT 24
Peak memory 201384 kb
Host smart-4bb1d18c-440f-42ab-a3dc-f4165b6b8242
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987750071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.987750071
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.374352419
Short name T800
Test name
Test status
Simulation time 358041731 ps
CPU time 1.5 seconds
Started Jul 21 05:39:31 PM PDT 24
Finished Jul 21 05:39:35 PM PDT 24
Peak memory 201396 kb
Host smart-2e8249da-ab03-4cbf-9680-58221e48a41a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374352419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.374352419
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.1531515239
Short name T875
Test name
Test status
Simulation time 4302204744 ps
CPU time 14.72 seconds
Started Jul 21 05:39:31 PM PDT 24
Finished Jul 21 05:39:47 PM PDT 24
Peak memory 201736 kb
Host smart-d5701f8c-040e-4d3c-8557-5f1fa81b7012
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531515239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_c
trl_same_csr_outstanding.1531515239
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.3017004245
Short name T903
Test name
Test status
Simulation time 429044724 ps
CPU time 2.76 seconds
Started Jul 21 05:39:28 PM PDT 24
Finished Jul 21 05:39:31 PM PDT 24
Peak memory 201696 kb
Host smart-0cc590fc-9dbd-45e5-a97b-f13766ba09e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017004245 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.3017004245
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.2739676193
Short name T866
Test name
Test status
Simulation time 7912370745 ps
CPU time 20.58 seconds
Started Jul 21 05:39:29 PM PDT 24
Finished Jul 21 05:39:50 PM PDT 24
Peak memory 201816 kb
Host smart-5b5fc41a-4872-46fc-a3e8-041bbd53bb25
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739676193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_in
tg_err.2739676193
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.2028129160
Short name T649
Test name
Test status
Simulation time 166753800414 ps
CPU time 403.69 seconds
Started Jul 21 05:40:04 PM PDT 24
Finished Jul 21 05:46:49 PM PDT 24
Peak memory 201784 kb
Host smart-75cd9093-9592-4064-80f3-bef108854218
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028129160 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gati
ng.2028129160
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.613816431
Short name T159
Test name
Test status
Simulation time 162892201567 ps
CPU time 90.97 seconds
Started Jul 21 05:40:10 PM PDT 24
Finished Jul 21 05:41:41 PM PDT 24
Peak memory 201760 kb
Host smart-a724ece0-c184-4465-967c-150be6d61800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613816431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.613816431
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.2549473423
Short name T702
Test name
Test status
Simulation time 495602983742 ps
CPU time 228.27 seconds
Started Jul 21 05:40:03 PM PDT 24
Finished Jul 21 05:43:52 PM PDT 24
Peak memory 201608 kb
Host smart-3274c3b9-c1c6-4942-a069-526164fc0f43
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549473423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrup
t_fixed.2549473423
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.3994019219
Short name T794
Test name
Test status
Simulation time 497777526232 ps
CPU time 273.28 seconds
Started Jul 21 05:40:05 PM PDT 24
Finished Jul 21 05:44:39 PM PDT 24
Peak memory 201688 kb
Host smart-ba096ef7-ded4-4c0e-ac19-7e03d8ae248d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994019219 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.3994019219
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.1179142527
Short name T484
Test name
Test status
Simulation time 166312066998 ps
CPU time 95.32 seconds
Started Jul 21 05:40:04 PM PDT 24
Finished Jul 21 05:41:40 PM PDT 24
Peak memory 201748 kb
Host smart-1e604a63-b7c4-47dc-a51b-ccc1d69a56ca
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179142527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixe
d.1179142527
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.228256638
Short name T389
Test name
Test status
Simulation time 415383296229 ps
CPU time 855.71 seconds
Started Jul 21 05:40:04 PM PDT 24
Finished Jul 21 05:54:21 PM PDT 24
Peak memory 201732 kb
Host smart-beecc03d-e3ed-4d36-83fa-e53330509ddb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228256638 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.a
dc_ctrl_filters_wakeup_fixed.228256638
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.3467012011
Short name T725
Test name
Test status
Simulation time 92766205338 ps
CPU time 348.36 seconds
Started Jul 21 05:40:08 PM PDT 24
Finished Jul 21 05:45:57 PM PDT 24
Peak memory 202124 kb
Host smart-99c5847a-ddb6-43c2-8826-3d7a41f54108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467012011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.3467012011
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.255142449
Short name T724
Test name
Test status
Simulation time 40534535338 ps
CPU time 8.16 seconds
Started Jul 21 05:40:11 PM PDT 24
Finished Jul 21 05:40:20 PM PDT 24
Peak memory 201428 kb
Host smart-2e9ff3bb-661e-46f5-ab1d-0ffa84271d5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255142449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.255142449
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.710737470
Short name T483
Test name
Test status
Simulation time 5109393059 ps
CPU time 4.19 seconds
Started Jul 21 05:40:02 PM PDT 24
Finished Jul 21 05:40:07 PM PDT 24
Peak memory 201520 kb
Host smart-c2dedf9e-f3f2-40d0-9eeb-b04cbf91ebc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710737470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.710737470
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.399378426
Short name T647
Test name
Test status
Simulation time 5740515670 ps
CPU time 10.96 seconds
Started Jul 21 05:40:11 PM PDT 24
Finished Jul 21 05:40:23 PM PDT 24
Peak memory 201596 kb
Host smart-a09b46a7-1afd-4b43-aa7c-1cf13c6e4131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399378426 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.399378426
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.2015180992
Short name T191
Test name
Test status
Simulation time 570567709078 ps
CPU time 343.97 seconds
Started Jul 21 05:40:03 PM PDT 24
Finished Jul 21 05:45:48 PM PDT 24
Peak memory 201776 kb
Host smart-2c3c7efc-97db-4202-b9d7-af89a45ecc76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015180992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.
2015180992
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.3095210628
Short name T279
Test name
Test status
Simulation time 292831657613 ps
CPU time 219.18 seconds
Started Jul 21 05:40:04 PM PDT 24
Finished Jul 21 05:43:44 PM PDT 24
Peak memory 210692 kb
Host smart-9ad9666c-d352-4984-918c-7adb109c6d80
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095210628 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.3095210628
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.3201060928
Short name T406
Test name
Test status
Simulation time 480285859 ps
CPU time 1.79 seconds
Started Jul 21 05:40:10 PM PDT 24
Finished Jul 21 05:40:13 PM PDT 24
Peak memory 201560 kb
Host smart-f57fcadd-1938-47ab-9d40-0d9375b197f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201060928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.3201060928
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.299825676
Short name T474
Test name
Test status
Simulation time 479177908992 ps
CPU time 1146.69 seconds
Started Jul 21 05:40:04 PM PDT 24
Finished Jul 21 05:59:12 PM PDT 24
Peak memory 201744 kb
Host smart-80df8be6-bb9c-4efe-bf51-f4e03aaf7e79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299825676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.299825676
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.3478754664
Short name T405
Test name
Test status
Simulation time 488739696440 ps
CPU time 1172.99 seconds
Started Jul 21 05:40:02 PM PDT 24
Finished Jul 21 05:59:36 PM PDT 24
Peak memory 201724 kb
Host smart-e98e72a9-a082-491f-ba2d-bfd8de7e9e19
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478754664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrup
t_fixed.3478754664
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.1027622847
Short name T567
Test name
Test status
Simulation time 481784500307 ps
CPU time 580.31 seconds
Started Jul 21 05:40:11 PM PDT 24
Finished Jul 21 05:49:52 PM PDT 24
Peak memory 201792 kb
Host smart-3809ca67-879b-48a9-a7b2-b442576ba64e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027622847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixe
d.1027622847
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.3263165400
Short name T630
Test name
Test status
Simulation time 199281484496 ps
CPU time 477.98 seconds
Started Jul 21 05:40:06 PM PDT 24
Finished Jul 21 05:48:05 PM PDT 24
Peak memory 201700 kb
Host smart-30b78a9f-e2e3-4849-81fc-9f1761f372ec
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263165400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
adc_ctrl_filters_wakeup_fixed.3263165400
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.642638387
Short name T457
Test name
Test status
Simulation time 112514530129 ps
CPU time 630.43 seconds
Started Jul 21 05:40:09 PM PDT 24
Finished Jul 21 05:50:40 PM PDT 24
Peak memory 202176 kb
Host smart-1ce45319-1712-468f-9fea-4f387c507f39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642638387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.642638387
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.2063009832
Short name T158
Test name
Test status
Simulation time 40700497753 ps
CPU time 48.51 seconds
Started Jul 21 05:40:10 PM PDT 24
Finished Jul 21 05:40:59 PM PDT 24
Peak memory 201580 kb
Host smart-0e19bc2b-d238-48b4-ab0a-98630953a23f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063009832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.2063009832
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.940263419
Short name T534
Test name
Test status
Simulation time 3176617791 ps
CPU time 9.01 seconds
Started Jul 21 05:40:08 PM PDT 24
Finished Jul 21 05:40:18 PM PDT 24
Peak memory 201604 kb
Host smart-3f525c56-6785-4cf8-b113-281c2513141b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940263419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.940263419
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.1240347850
Short name T66
Test name
Test status
Simulation time 4267097988 ps
CPU time 4.15 seconds
Started Jul 21 05:40:11 PM PDT 24
Finished Jul 21 05:40:16 PM PDT 24
Peak memory 217208 kb
Host smart-695ccbd0-43ec-408e-a2c6-90a172681d37
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240347850 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.1240347850
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.1483366410
Short name T472
Test name
Test status
Simulation time 5744367833 ps
CPU time 13.21 seconds
Started Jul 21 05:40:04 PM PDT 24
Finished Jul 21 05:40:18 PM PDT 24
Peak memory 201608 kb
Host smart-7fefdfd9-8ef9-468e-808b-8a4977de0e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483366410 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.1483366410
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.1421140883
Short name T709
Test name
Test status
Simulation time 262139202016 ps
CPU time 590.12 seconds
Started Jul 21 05:40:10 PM PDT 24
Finished Jul 21 05:50:01 PM PDT 24
Peak memory 202196 kb
Host smart-815dd14d-af5c-4db0-ba45-e4f58930f182
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421140883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.
1421140883
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.2069454791
Short name T645
Test name
Test status
Simulation time 434989172 ps
CPU time 1.63 seconds
Started Jul 21 05:40:22 PM PDT 24
Finished Jul 21 05:40:24 PM PDT 24
Peak memory 201472 kb
Host smart-65253645-42e3-4931-840b-2c654ef2ea0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069454791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.2069454791
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.1559581093
Short name T504
Test name
Test status
Simulation time 327691999904 ps
CPU time 819.49 seconds
Started Jul 21 05:40:29 PM PDT 24
Finished Jul 21 05:54:11 PM PDT 24
Peak memory 201592 kb
Host smart-2dd0b4bd-d62e-4b54-ac31-8b105ca39e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559581093 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.1559581093
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.977865386
Short name T234
Test name
Test status
Simulation time 165050376146 ps
CPU time 40.55 seconds
Started Jul 21 05:40:24 PM PDT 24
Finished Jul 21 05:41:05 PM PDT 24
Peak memory 201756 kb
Host smart-94e856bb-12bb-4251-a7e4-cb7351a786e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977865386 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.977865386
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.2624182181
Short name T438
Test name
Test status
Simulation time 163875081766 ps
CPU time 93.44 seconds
Started Jul 21 05:40:21 PM PDT 24
Finished Jul 21 05:41:56 PM PDT 24
Peak memory 201744 kb
Host smart-bbdf75e9-5887-4621-842b-818a45fd6307
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624182181 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fix
ed.2624182181
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.2322126569
Short name T667
Test name
Test status
Simulation time 444626967535 ps
CPU time 266.8 seconds
Started Jul 21 05:40:32 PM PDT 24
Finished Jul 21 05:45:00 PM PDT 24
Peak memory 201744 kb
Host smart-8c5eed85-5f4f-4fd4-9f2f-85804cf34901
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322126569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters
_wakeup.2322126569
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.3505104367
Short name T548
Test name
Test status
Simulation time 405715661713 ps
CPU time 925.23 seconds
Started Jul 21 05:40:24 PM PDT 24
Finished Jul 21 05:55:49 PM PDT 24
Peak memory 201704 kb
Host smart-ccfef34e-66ec-4191-85e4-31a3f4b0711a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505104367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.adc_ctrl_filters_wakeup_fixed.3505104367
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.801371890
Short name T611
Test name
Test status
Simulation time 100573429201 ps
CPU time 350.85 seconds
Started Jul 21 05:40:28 PM PDT 24
Finished Jul 21 05:46:20 PM PDT 24
Peak memory 202112 kb
Host smart-26473c41-dac6-490a-8666-a8ab5d901bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801371890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.801371890
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.1122730798
Short name T526
Test name
Test status
Simulation time 38319899480 ps
CPU time 45.34 seconds
Started Jul 21 05:40:29 PM PDT 24
Finished Jul 21 05:41:16 PM PDT 24
Peak memory 201596 kb
Host smart-d94ae112-e544-4eb7-ae13-6deff23e549c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122730798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.1122730798
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.609232176
Short name T360
Test name
Test status
Simulation time 4346609707 ps
CPU time 3.27 seconds
Started Jul 21 05:40:22 PM PDT 24
Finished Jul 21 05:40:26 PM PDT 24
Peak memory 201592 kb
Host smart-fa70728c-900f-48a3-9ad1-1902f46e698f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609232176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.609232176
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.69762086
Short name T92
Test name
Test status
Simulation time 5894554876 ps
CPU time 10.21 seconds
Started Jul 21 05:40:27 PM PDT 24
Finished Jul 21 05:40:38 PM PDT 24
Peak memory 201500 kb
Host smart-233ccf6f-d8f3-43d1-8d11-771eec55d266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69762086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.69762086
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.2860427767
Short name T140
Test name
Test status
Simulation time 366675000503 ps
CPU time 198.89 seconds
Started Jul 21 05:40:21 PM PDT 24
Finished Jul 21 05:43:41 PM PDT 24
Peak memory 201680 kb
Host smart-57ea8738-9fc6-4f70-ab9a-751be625a393
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860427767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all
.2860427767
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.3214708525
Short name T60
Test name
Test status
Simulation time 467578229 ps
CPU time 0.72 seconds
Started Jul 21 05:40:26 PM PDT 24
Finished Jul 21 05:40:28 PM PDT 24
Peak memory 201396 kb
Host smart-3ff95e53-83e3-4485-959c-4c56fb4defb5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214708525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.3214708525
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.3222371066
Short name T252
Test name
Test status
Simulation time 173329608773 ps
CPU time 181.39 seconds
Started Jul 21 05:40:26 PM PDT 24
Finished Jul 21 05:43:28 PM PDT 24
Peak memory 201788 kb
Host smart-883290d3-9805-4d99-8bac-0c284342956d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222371066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gat
ing.3222371066
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.3839279968
Short name T280
Test name
Test status
Simulation time 496448979659 ps
CPU time 333.54 seconds
Started Jul 21 05:40:28 PM PDT 24
Finished Jul 21 05:46:03 PM PDT 24
Peak memory 201736 kb
Host smart-a641d3f9-0b49-41c3-bdd8-92517523bf48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839279968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.3839279968
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.3776828066
Short name T195
Test name
Test status
Simulation time 484455418752 ps
CPU time 532.24 seconds
Started Jul 21 05:40:27 PM PDT 24
Finished Jul 21 05:49:21 PM PDT 24
Peak memory 201684 kb
Host smart-8925fb83-891f-4edc-acd0-6f042923a05f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776828066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.3776828066
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.1499614535
Short name T476
Test name
Test status
Simulation time 487817222943 ps
CPU time 105.92 seconds
Started Jul 21 05:40:26 PM PDT 24
Finished Jul 21 05:42:12 PM PDT 24
Peak memory 201696 kb
Host smart-dbfb628f-abd1-4603-b1f9-af1c7542c70f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499614535 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interru
pt_fixed.1499614535
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.634678025
Short name T473
Test name
Test status
Simulation time 165700642557 ps
CPU time 195.89 seconds
Started Jul 21 05:40:27 PM PDT 24
Finished Jul 21 05:43:43 PM PDT 24
Peak memory 201732 kb
Host smart-590810cb-719d-46dc-a962-091451cfe1ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634678025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.634678025
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.961181941
Short name T443
Test name
Test status
Simulation time 332622624912 ps
CPU time 847.02 seconds
Started Jul 21 05:40:27 PM PDT 24
Finished Jul 21 05:54:35 PM PDT 24
Peak memory 201732 kb
Host smart-fbc8033a-2259-4866-a966-be2b2b11fac0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=961181941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fixe
d.961181941
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.1616039045
Short name T145
Test name
Test status
Simulation time 570751574199 ps
CPU time 349.33 seconds
Started Jul 21 05:40:28 PM PDT 24
Finished Jul 21 05:46:18 PM PDT 24
Peak memory 201796 kb
Host smart-cae94d7a-3efc-4af9-ba26-7f276e4842b4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616039045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters
_wakeup.1616039045
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.871835627
Short name T758
Test name
Test status
Simulation time 398176004926 ps
CPU time 466.1 seconds
Started Jul 21 05:40:42 PM PDT 24
Finished Jul 21 05:48:28 PM PDT 24
Peak memory 201724 kb
Host smart-ed4cc979-7fc0-47e3-8a53-11d418ef36b4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871835627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
adc_ctrl_filters_wakeup_fixed.871835627
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.3963684215
Short name T669
Test name
Test status
Simulation time 81616140241 ps
CPU time 259.03 seconds
Started Jul 21 05:40:25 PM PDT 24
Finished Jul 21 05:44:44 PM PDT 24
Peak memory 202132 kb
Host smart-899ff210-1b88-47ef-bf90-5b6887473aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963684215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.3963684215
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.60908776
Short name T73
Test name
Test status
Simulation time 43280234479 ps
CPU time 90.45 seconds
Started Jul 21 05:40:28 PM PDT 24
Finished Jul 21 05:41:59 PM PDT 24
Peak memory 201528 kb
Host smart-b0aa2541-0e07-44e8-b7db-452c0f8bf411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60908776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.60908776
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.2102133269
Short name T598
Test name
Test status
Simulation time 5049947953 ps
CPU time 2.12 seconds
Started Jul 21 05:40:20 PM PDT 24
Finished Jul 21 05:40:24 PM PDT 24
Peak memory 201588 kb
Host smart-0f23b533-0901-46c1-8e18-8c6d52ce6b1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102133269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.2102133269
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.549338247
Short name T354
Test name
Test status
Simulation time 6152011483 ps
CPU time 14.78 seconds
Started Jul 21 05:40:26 PM PDT 24
Finished Jul 21 05:40:41 PM PDT 24
Peak memory 201580 kb
Host smart-a05b7a08-4f1a-4de4-9868-d8cfb980cc1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549338247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.549338247
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.1639724366
Short name T506
Test name
Test status
Simulation time 11745755493 ps
CPU time 26.01 seconds
Started Jul 21 05:40:23 PM PDT 24
Finished Jul 21 05:40:49 PM PDT 24
Peak memory 201740 kb
Host smart-cfe4546d-8a65-48ec-ae8a-35f91682e9cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639724366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all
.1639724366
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.2680547285
Short name T597
Test name
Test status
Simulation time 344934914 ps
CPU time 1.4 seconds
Started Jul 21 05:40:40 PM PDT 24
Finished Jul 21 05:40:42 PM PDT 24
Peak memory 201444 kb
Host smart-d0c83642-9953-426b-92a3-e0f1f1511a47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680547285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.2680547285
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.1205468981
Short name T259
Test name
Test status
Simulation time 329515536306 ps
CPU time 113.51 seconds
Started Jul 21 05:40:24 PM PDT 24
Finished Jul 21 05:42:18 PM PDT 24
Peak memory 201888 kb
Host smart-18572e5b-aea1-4891-aa63-c34f6ce68bca
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205468981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gat
ing.1205468981
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.3771483137
Short name T194
Test name
Test status
Simulation time 177426383880 ps
CPU time 376.18 seconds
Started Jul 21 05:40:21 PM PDT 24
Finished Jul 21 05:46:39 PM PDT 24
Peak memory 201756 kb
Host smart-14af68cf-6b31-48da-91d9-56722907407f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771483137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.3771483137
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.3857803863
Short name T72
Test name
Test status
Simulation time 495711507545 ps
CPU time 1147.19 seconds
Started Jul 21 05:40:22 PM PDT 24
Finished Jul 21 05:59:30 PM PDT 24
Peak memory 201840 kb
Host smart-3d93c42a-7bb4-4bcc-8992-b8fa815d0a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857803863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.3857803863
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.1746839102
Short name T533
Test name
Test status
Simulation time 481210892554 ps
CPU time 313.11 seconds
Started Jul 21 05:40:27 PM PDT 24
Finished Jul 21 05:45:41 PM PDT 24
Peak memory 201616 kb
Host smart-804f82ff-2dee-4e23-b461-5200bb7fead7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746839102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interru
pt_fixed.1746839102
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.811623102
Short name T697
Test name
Test status
Simulation time 327682165358 ps
CPU time 763.36 seconds
Started Jul 21 05:40:26 PM PDT 24
Finished Jul 21 05:53:10 PM PDT 24
Peak memory 201656 kb
Host smart-e2fefad1-4b17-4f2b-b3e3-0049ed01160e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811623102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.811623102
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.4056731607
Short name T736
Test name
Test status
Simulation time 483015279574 ps
CPU time 1143.58 seconds
Started Jul 21 05:40:29 PM PDT 24
Finished Jul 21 05:59:34 PM PDT 24
Peak memory 201628 kb
Host smart-7117c776-59da-4c4c-a420-2e2effd02b9b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056731607 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fix
ed.4056731607
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.3807680507
Short name T593
Test name
Test status
Simulation time 384008798184 ps
CPU time 838.84 seconds
Started Jul 21 05:40:45 PM PDT 24
Finished Jul 21 05:54:44 PM PDT 24
Peak memory 201736 kb
Host smart-8e58e080-13ce-4dcd-b237-1525a0661f4c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807680507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.adc_ctrl_filters_wakeup_fixed.3807680507
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.133401374
Short name T341
Test name
Test status
Simulation time 62421453682 ps
CPU time 366.06 seconds
Started Jul 21 05:40:29 PM PDT 24
Finished Jul 21 05:46:36 PM PDT 24
Peak memory 202140 kb
Host smart-383df0aa-c2ad-4020-bc76-0f8346af0fc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133401374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.133401374
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.3366152707
Short name T154
Test name
Test status
Simulation time 23142662164 ps
CPU time 29 seconds
Started Jul 21 05:40:26 PM PDT 24
Finished Jul 21 05:40:56 PM PDT 24
Peak memory 201536 kb
Host smart-ccc8426d-4a1d-4ce1-a546-f6fc873e1f9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366152707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.3366152707
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.1554344067
Short name T452
Test name
Test status
Simulation time 2777787754 ps
CPU time 2.28 seconds
Started Jul 21 05:40:45 PM PDT 24
Finished Jul 21 05:40:48 PM PDT 24
Peak memory 201588 kb
Host smart-beabc4ed-4227-4e25-81ab-025c687bc547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554344067 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.1554344067
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.3356205998
Short name T441
Test name
Test status
Simulation time 5990060477 ps
CPU time 7.21 seconds
Started Jul 21 05:40:23 PM PDT 24
Finished Jul 21 05:40:31 PM PDT 24
Peak memory 201620 kb
Host smart-f21b59fa-8bdd-4732-8cf3-8471712fdfbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356205998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.3356205998
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.2278810797
Short name T227
Test name
Test status
Simulation time 34302962131 ps
CPU time 44.07 seconds
Started Jul 21 05:40:30 PM PDT 24
Finished Jul 21 05:41:16 PM PDT 24
Peak memory 210504 kb
Host smart-3d9157be-65dd-4409-8d97-8fe8440d4e02
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278810797 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.2278810797
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.2227036283
Short name T605
Test name
Test status
Simulation time 405721938 ps
CPU time 1.05 seconds
Started Jul 21 05:40:29 PM PDT 24
Finished Jul 21 05:40:31 PM PDT 24
Peak memory 201540 kb
Host smart-12d2d170-d0b5-4332-b086-af3ac8bf45e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227036283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.2227036283
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.2654504647
Short name T295
Test name
Test status
Simulation time 166344199653 ps
CPU time 186.34 seconds
Started Jul 21 05:40:46 PM PDT 24
Finished Jul 21 05:43:53 PM PDT 24
Peak memory 201716 kb
Host smart-c0a9f033-59d5-40c9-8686-c12a706877ea
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654504647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gat
ing.2654504647
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.4213724387
Short name T225
Test name
Test status
Simulation time 160373032788 ps
CPU time 99.31 seconds
Started Jul 21 05:40:30 PM PDT 24
Finished Jul 21 05:42:11 PM PDT 24
Peak memory 201784 kb
Host smart-159eac17-7b84-4fc7-ae8f-1434cbf86fcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213724387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.4213724387
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.2543674796
Short name T2
Test name
Test status
Simulation time 163600536082 ps
CPU time 125.88 seconds
Started Jul 21 05:40:37 PM PDT 24
Finished Jul 21 05:42:43 PM PDT 24
Peak memory 201760 kb
Host smart-e149ba57-747d-4ba4-a37b-50e729b77e1e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543674796 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interru
pt_fixed.2543674796
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.1801490102
Short name T286
Test name
Test status
Simulation time 328738694859 ps
CPU time 213.13 seconds
Started Jul 21 05:40:30 PM PDT 24
Finished Jul 21 05:44:05 PM PDT 24
Peak memory 201636 kb
Host smart-869c5772-7092-4c63-96c2-3662f6a087b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801490102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.1801490102
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.1221765769
Short name T155
Test name
Test status
Simulation time 323321561350 ps
CPU time 682.5 seconds
Started Jul 21 05:40:27 PM PDT 24
Finished Jul 21 05:51:51 PM PDT 24
Peak memory 201720 kb
Host smart-a18d9036-5e1a-45be-a577-ea08bca0c035
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221765769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fix
ed.1221765769
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.128945290
Short name T292
Test name
Test status
Simulation time 356237065051 ps
CPU time 329.9 seconds
Started Jul 21 05:40:30 PM PDT 24
Finished Jul 21 05:46:01 PM PDT 24
Peak memory 201696 kb
Host smart-5abb7579-c745-4235-8347-b4f886458cae
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128945290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_
wakeup.128945290
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.1674694925
Short name T347
Test name
Test status
Simulation time 200707821986 ps
CPU time 426.48 seconds
Started Jul 21 05:40:29 PM PDT 24
Finished Jul 21 05:47:37 PM PDT 24
Peak memory 201712 kb
Host smart-f7f20321-1d8e-4724-be14-0ee2c5f776cb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674694925 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.adc_ctrl_filters_wakeup_fixed.1674694925
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.2330398326
Short name T178
Test name
Test status
Simulation time 101911891354 ps
CPU time 305.66 seconds
Started Jul 21 05:40:34 PM PDT 24
Finished Jul 21 05:45:41 PM PDT 24
Peak memory 202024 kb
Host smart-8b6eef1a-714b-4923-baa2-9652be5aea19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330398326 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.2330398326
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.111972800
Short name T708
Test name
Test status
Simulation time 40482126961 ps
CPU time 24.25 seconds
Started Jul 21 05:40:30 PM PDT 24
Finished Jul 21 05:40:56 PM PDT 24
Peak memory 201516 kb
Host smart-a7bc397c-3132-419d-a9b4-de6b15a7155c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111972800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.111972800
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.65083042
Short name T351
Test name
Test status
Simulation time 5373987576 ps
CPU time 6.29 seconds
Started Jul 21 05:40:29 PM PDT 24
Finished Jul 21 05:40:37 PM PDT 24
Peak memory 201592 kb
Host smart-450ce4eb-fa08-4db7-977e-52aacd86d60c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65083042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.65083042
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.3546923680
Short name T733
Test name
Test status
Simulation time 5823888746 ps
CPU time 4.74 seconds
Started Jul 21 05:40:38 PM PDT 24
Finished Jul 21 05:40:43 PM PDT 24
Peak memory 201660 kb
Host smart-720ae914-d8d5-4af1-9096-b43e328747a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546923680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.3546923680
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.1393367675
Short name T710
Test name
Test status
Simulation time 359489398347 ps
CPU time 848.83 seconds
Started Jul 21 05:40:29 PM PDT 24
Finished Jul 21 05:54:40 PM PDT 24
Peak memory 201736 kb
Host smart-071caad3-fabb-4475-85cf-50a6a5dc3aa5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393367675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all
.1393367675
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.3703777865
Short name T408
Test name
Test status
Simulation time 519563910 ps
CPU time 1.75 seconds
Started Jul 21 05:40:30 PM PDT 24
Finished Jul 21 05:40:33 PM PDT 24
Peak memory 201364 kb
Host smart-8368ff85-5317-46ca-b4f8-85b82cf42baf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703777865 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.3703777865
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.3444481314
Short name T192
Test name
Test status
Simulation time 449210559434 ps
CPU time 867.25 seconds
Started Jul 21 05:40:30 PM PDT 24
Finished Jul 21 05:54:59 PM PDT 24
Peak memory 201796 kb
Host smart-3a6a67c4-9971-408e-8bc7-228d7c46c06e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444481314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gat
ing.3444481314
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.2320085366
Short name T668
Test name
Test status
Simulation time 334540977374 ps
CPU time 388.52 seconds
Started Jul 21 05:40:29 PM PDT 24
Finished Jul 21 05:46:59 PM PDT 24
Peak memory 201632 kb
Host smart-610b5d92-c59e-4d1f-ada1-da4be9a75c0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320085366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.2320085366
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.799326225
Short name T564
Test name
Test status
Simulation time 166577332044 ps
CPU time 371.22 seconds
Started Jul 21 05:40:30 PM PDT 24
Finished Jul 21 05:46:43 PM PDT 24
Peak memory 201676 kb
Host smart-f4d82a0f-6bc1-4784-99f6-6cdb3289b8f5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=799326225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrup
t_fixed.799326225
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.4015622391
Short name T271
Test name
Test status
Simulation time 328231653534 ps
CPU time 195.53 seconds
Started Jul 21 05:40:36 PM PDT 24
Finished Jul 21 05:43:52 PM PDT 24
Peak memory 201724 kb
Host smart-a6b57c70-a744-4b61-b0c8-8ef8b5eb8314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015622391 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.4015622391
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.703233827
Short name T613
Test name
Test status
Simulation time 322869818404 ps
CPU time 746.6 seconds
Started Jul 21 05:40:33 PM PDT 24
Finished Jul 21 05:53:00 PM PDT 24
Peak memory 201736 kb
Host smart-13629444-dee1-45a2-a0e8-be99026e0edd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=703233827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fixe
d.703233827
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.3720317934
Short name T71
Test name
Test status
Simulation time 171729641316 ps
CPU time 119.41 seconds
Started Jul 21 05:40:28 PM PDT 24
Finished Jul 21 05:42:28 PM PDT 24
Peak memory 201736 kb
Host smart-aadb271b-f23c-4b4f-acde-45f831835daf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720317934 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters
_wakeup.3720317934
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.1022718455
Short name T770
Test name
Test status
Simulation time 606369685238 ps
CPU time 706.47 seconds
Started Jul 21 05:40:29 PM PDT 24
Finished Jul 21 05:52:16 PM PDT 24
Peak memory 201724 kb
Host smart-fad1ecd1-f9b3-48c0-94fd-ad5da7387310
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022718455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.adc_ctrl_filters_wakeup_fixed.1022718455
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.3143753242
Short name T579
Test name
Test status
Simulation time 88252791278 ps
CPU time 481.38 seconds
Started Jul 21 05:40:41 PM PDT 24
Finished Jul 21 05:48:42 PM PDT 24
Peak memory 202060 kb
Host smart-b85c4887-03b9-42d9-a953-9c64a60a4140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143753242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.3143753242
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.557156042
Short name T717
Test name
Test status
Simulation time 34647152833 ps
CPU time 15.67 seconds
Started Jul 21 05:40:29 PM PDT 24
Finished Jul 21 05:40:46 PM PDT 24
Peak memory 201608 kb
Host smart-014c291c-b689-4f0c-9a19-a8658e805b13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557156042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.557156042
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.2013424717
Short name T657
Test name
Test status
Simulation time 4204618525 ps
CPU time 10.95 seconds
Started Jul 21 05:40:27 PM PDT 24
Finished Jul 21 05:40:39 PM PDT 24
Peak memory 201572 kb
Host smart-35b0dbab-444e-411d-97a8-a2794622669d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013424717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.2013424717
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.1561611511
Short name T428
Test name
Test status
Simulation time 5889175843 ps
CPU time 1.95 seconds
Started Jul 21 05:40:29 PM PDT 24
Finished Jul 21 05:40:32 PM PDT 24
Peak memory 201568 kb
Host smart-b16a8b85-121f-4570-9a57-e67c08812c13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561611511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.1561611511
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.3442373013
Short name T338
Test name
Test status
Simulation time 119195702925 ps
CPU time 65.45 seconds
Started Jul 21 05:40:34 PM PDT 24
Finished Jul 21 05:41:40 PM PDT 24
Peak memory 210040 kb
Host smart-cd4d94d2-7b30-4ec3-8883-9345c04966e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442373013 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.3442373013
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.1531401317
Short name T487
Test name
Test status
Simulation time 365585165 ps
CPU time 0.83 seconds
Started Jul 21 05:40:33 PM PDT 24
Finished Jul 21 05:40:35 PM PDT 24
Peak memory 201552 kb
Host smart-d021d51e-dc72-4d17-97bf-4ab35031f6f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531401317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.1531401317
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.3318280057
Short name T289
Test name
Test status
Simulation time 176284691995 ps
CPU time 133.69 seconds
Started Jul 21 05:40:29 PM PDT 24
Finished Jul 21 05:42:44 PM PDT 24
Peak memory 201684 kb
Host smart-5b1ac2fd-b644-4470-9341-d7e93ac0bbb4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318280057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gat
ing.3318280057
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.978670465
Short name T631
Test name
Test status
Simulation time 166939514701 ps
CPU time 382.74 seconds
Started Jul 21 05:40:29 PM PDT 24
Finished Jul 21 05:46:54 PM PDT 24
Peak memory 201772 kb
Host smart-8a399017-20b6-4ec0-96e3-fda6407ac3c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978670465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.978670465
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.3501265333
Short name T420
Test name
Test status
Simulation time 492928993233 ps
CPU time 1099.85 seconds
Started Jul 21 05:40:28 PM PDT 24
Finished Jul 21 05:58:49 PM PDT 24
Peak memory 201724 kb
Host smart-7c0d7275-0e6c-45b9-bfa6-f2da7d846466
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501265333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interru
pt_fixed.3501265333
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.1774571917
Short name T219
Test name
Test status
Simulation time 169004532356 ps
CPU time 362.05 seconds
Started Jul 21 05:40:30 PM PDT 24
Finished Jul 21 05:46:34 PM PDT 24
Peak memory 201732 kb
Host smart-8942de0b-6888-494d-a7e0-beab3cc17b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774571917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.1774571917
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.3777687550
Short name T346
Test name
Test status
Simulation time 160548015896 ps
CPU time 173.59 seconds
Started Jul 21 05:40:36 PM PDT 24
Finished Jul 21 05:43:30 PM PDT 24
Peak memory 201728 kb
Host smart-873e5e01-0824-497d-afd7-035bfaf4100c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777687550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fix
ed.3777687550
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.3466731011
Short name T202
Test name
Test status
Simulation time 386889746658 ps
CPU time 270.06 seconds
Started Jul 21 05:40:29 PM PDT 24
Finished Jul 21 05:45:01 PM PDT 24
Peak memory 201628 kb
Host smart-9b8e775a-40d8-4cb4-a5f6-576930d2e26e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466731011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters
_wakeup.3466731011
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.2115975461
Short name T471
Test name
Test status
Simulation time 597506044724 ps
CPU time 368.88 seconds
Started Jul 21 05:40:27 PM PDT 24
Finished Jul 21 05:46:37 PM PDT 24
Peak memory 201724 kb
Host smart-324b8ba0-85e4-438f-8949-c6d80e86bf63
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115975461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.adc_ctrl_filters_wakeup_fixed.2115975461
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.2339706787
Short name T530
Test name
Test status
Simulation time 105589648353 ps
CPU time 380.52 seconds
Started Jul 21 05:40:41 PM PDT 24
Finished Jul 21 05:47:03 PM PDT 24
Peak memory 202092 kb
Host smart-b778959c-90b9-499b-9218-6d651df909ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339706787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.2339706787
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.280866481
Short name T414
Test name
Test status
Simulation time 38177585628 ps
CPU time 18.84 seconds
Started Jul 21 05:40:39 PM PDT 24
Finished Jul 21 05:40:59 PM PDT 24
Peak memory 201480 kb
Host smart-fbdd3913-99ab-4af4-ba6f-b966ca0be948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280866481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.280866481
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.3875000824
Short name T521
Test name
Test status
Simulation time 3538359068 ps
CPU time 4.97 seconds
Started Jul 21 05:40:29 PM PDT 24
Finished Jul 21 05:40:35 PM PDT 24
Peak memory 201608 kb
Host smart-07738918-921a-4114-bd15-8701d3b3e87c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875000824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.3875000824
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.1560832544
Short name T524
Test name
Test status
Simulation time 6197555097 ps
CPU time 1.62 seconds
Started Jul 21 05:40:33 PM PDT 24
Finished Jul 21 05:40:35 PM PDT 24
Peak memory 201612 kb
Host smart-e0707afb-d1c4-455e-8551-58b1265b20d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560832544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.1560832544
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.854152261
Short name T628
Test name
Test status
Simulation time 50869395767 ps
CPU time 62.61 seconds
Started Jul 21 05:40:44 PM PDT 24
Finished Jul 21 05:41:47 PM PDT 24
Peak memory 201632 kb
Host smart-01c60ff5-6c7e-4622-a9ed-cdfa12861937
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854152261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all.
854152261
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.1800846774
Short name T18
Test name
Test status
Simulation time 66660963063 ps
CPU time 35.15 seconds
Started Jul 21 05:40:35 PM PDT 24
Finished Jul 21 05:41:11 PM PDT 24
Peak memory 201884 kb
Host smart-d851bbd0-b000-453b-adfb-48cfe81f2bff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800846774 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.1800846774
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.3833420592
Short name T658
Test name
Test status
Simulation time 387615219 ps
CPU time 1.51 seconds
Started Jul 21 05:40:44 PM PDT 24
Finished Jul 21 05:40:46 PM PDT 24
Peak memory 201440 kb
Host smart-a9012fb1-a6bf-4c89-8961-551949de0fdd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833420592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.3833420592
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.1475103294
Short name T262
Test name
Test status
Simulation time 174259343890 ps
CPU time 395.55 seconds
Started Jul 21 05:40:38 PM PDT 24
Finished Jul 21 05:47:13 PM PDT 24
Peak memory 201708 kb
Host smart-3cf4c8f7-28f1-47f4-9ab0-015b9b10607c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475103294 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gat
ing.1475103294
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.228404112
Short name T776
Test name
Test status
Simulation time 323337910647 ps
CPU time 192.24 seconds
Started Jul 21 05:40:33 PM PDT 24
Finished Jul 21 05:43:46 PM PDT 24
Peak memory 201556 kb
Host smart-f1611717-4080-40e9-b0fe-ed77441a4539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228404112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.228404112
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.1383609672
Short name T67
Test name
Test status
Simulation time 165262811020 ps
CPU time 195.42 seconds
Started Jul 21 05:40:35 PM PDT 24
Finished Jul 21 05:43:51 PM PDT 24
Peak memory 201636 kb
Host smart-9c2ffcc7-a9ff-46d7-ad5f-f58ca0a9989f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383609672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interru
pt_fixed.1383609672
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.3737023910
Short name T670
Test name
Test status
Simulation time 167171241457 ps
CPU time 235.37 seconds
Started Jul 21 05:40:35 PM PDT 24
Finished Jul 21 05:44:31 PM PDT 24
Peak memory 201668 kb
Host smart-eeaa7ba9-ebac-46df-82a3-cfa90ccd7d7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737023910 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.3737023910
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.2643223819
Short name T373
Test name
Test status
Simulation time 168366549141 ps
CPU time 176.53 seconds
Started Jul 21 05:40:36 PM PDT 24
Finished Jul 21 05:43:33 PM PDT 24
Peak memory 201704 kb
Host smart-b4a96df2-eb61-4fe9-a517-fc057dd97b81
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643223819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fix
ed.2643223819
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.1497645018
Short name T762
Test name
Test status
Simulation time 195996407141 ps
CPU time 112.36 seconds
Started Jul 21 05:40:42 PM PDT 24
Finished Jul 21 05:42:35 PM PDT 24
Peak memory 201716 kb
Host smart-3012c5ae-0890-41c7-8e32-250d6e12ecc0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497645018 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters
_wakeup.1497645018
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.1003115568
Short name T580
Test name
Test status
Simulation time 192397279606 ps
CPU time 410.17 seconds
Started Jul 21 05:40:44 PM PDT 24
Finished Jul 21 05:47:34 PM PDT 24
Peak memory 201620 kb
Host smart-1df41b92-b659-4808-b6c7-6f5c403fa4e0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003115568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16
.adc_ctrl_filters_wakeup_fixed.1003115568
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.34221114
Short name T600
Test name
Test status
Simulation time 118174673836 ps
CPU time 613.23 seconds
Started Jul 21 05:40:34 PM PDT 24
Finished Jul 21 05:50:48 PM PDT 24
Peak memory 202132 kb
Host smart-6aeb8564-a297-49cd-bc83-36cdd91200da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34221114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.34221114
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.442404525
Short name T450
Test name
Test status
Simulation time 27736449059 ps
CPU time 4.47 seconds
Started Jul 21 05:40:42 PM PDT 24
Finished Jul 21 05:40:47 PM PDT 24
Peak memory 201504 kb
Host smart-2d14884a-441c-4f5c-9be7-65e94b417e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442404525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.442404525
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.15459221
Short name T551
Test name
Test status
Simulation time 3801440851 ps
CPU time 9.12 seconds
Started Jul 21 05:40:42 PM PDT 24
Finished Jul 21 05:40:52 PM PDT 24
Peak memory 201640 kb
Host smart-2c476019-ed63-4ffd-9e6c-841f06551eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15459221 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.15459221
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.1374796918
Short name T747
Test name
Test status
Simulation time 6219821721 ps
CPU time 14.09 seconds
Started Jul 21 05:40:34 PM PDT 24
Finished Jul 21 05:40:49 PM PDT 24
Peak memory 201604 kb
Host smart-a1e7f652-2262-493a-8db1-0b714eb48447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374796918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.1374796918
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.3983416250
Short name T22
Test name
Test status
Simulation time 225972723042 ps
CPU time 531.63 seconds
Started Jul 21 05:40:42 PM PDT 24
Finished Jul 21 05:49:34 PM PDT 24
Peak memory 201744 kb
Host smart-4e50cbfb-96ed-4f98-b477-b4d870854401
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983416250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all
.3983416250
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.2637655358
Short name T14
Test name
Test status
Simulation time 67366044983 ps
CPU time 44.08 seconds
Started Jul 21 05:40:36 PM PDT 24
Finished Jul 21 05:41:20 PM PDT 24
Peak memory 210124 kb
Host smart-8f146d77-c954-4a36-b22f-a02d04c8854a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637655358 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.2637655358
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.3213122020
Short name T638
Test name
Test status
Simulation time 346648893 ps
CPU time 0.85 seconds
Started Jul 21 05:40:43 PM PDT 24
Finished Jul 21 05:40:44 PM PDT 24
Peak memory 201512 kb
Host smart-aa6dd938-d231-4779-a180-7dc472469ca8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213122020 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.3213122020
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.1171663924
Short name T124
Test name
Test status
Simulation time 168250839369 ps
CPU time 401.53 seconds
Started Jul 21 05:40:39 PM PDT 24
Finished Jul 21 05:47:21 PM PDT 24
Peak memory 201640 kb
Host smart-69dc5fee-57e4-429b-9208-d2d9084656cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171663924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.1171663924
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.2880524450
Short name T237
Test name
Test status
Simulation time 327658843804 ps
CPU time 769.88 seconds
Started Jul 21 05:40:35 PM PDT 24
Finished Jul 21 05:53:26 PM PDT 24
Peak memory 201736 kb
Host smart-ddc123ef-3902-4b5d-ba14-1d4ed9f08ccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880524450 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.2880524450
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.492595854
Short name T344
Test name
Test status
Simulation time 326296708906 ps
CPU time 782.2 seconds
Started Jul 21 05:40:35 PM PDT 24
Finished Jul 21 05:53:38 PM PDT 24
Peak memory 201648 kb
Host smart-7ee18b2a-669d-4d13-b981-acf6b4ff7a15
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=492595854 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrup
t_fixed.492595854
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.1479243589
Short name T655
Test name
Test status
Simulation time 493426826074 ps
CPU time 1181.58 seconds
Started Jul 21 05:40:39 PM PDT 24
Finished Jul 21 06:00:21 PM PDT 24
Peak memory 201592 kb
Host smart-763f811a-9f50-4a0f-9fa9-10e3334c1e3e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479243589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fix
ed.1479243589
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.3467328164
Short name T267
Test name
Test status
Simulation time 202970671770 ps
CPU time 179.3 seconds
Started Jul 21 05:40:40 PM PDT 24
Finished Jul 21 05:43:40 PM PDT 24
Peak memory 201636 kb
Host smart-0670a48b-625e-4785-bfb5-4f8a2e91273c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467328164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters
_wakeup.3467328164
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.2764022299
Short name T394
Test name
Test status
Simulation time 402659002190 ps
CPU time 494.9 seconds
Started Jul 21 05:40:39 PM PDT 24
Finished Jul 21 05:48:55 PM PDT 24
Peak memory 201604 kb
Host smart-711f09c4-b68d-4814-b294-438e662a24cd
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764022299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.adc_ctrl_filters_wakeup_fixed.2764022299
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.3742130273
Short name T171
Test name
Test status
Simulation time 122961410297 ps
CPU time 660.01 seconds
Started Jul 21 05:40:41 PM PDT 24
Finished Jul 21 05:51:42 PM PDT 24
Peak memory 202148 kb
Host smart-e9cabce4-c5a3-4225-a430-18ead004481b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742130273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.3742130273
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.226751815
Short name T449
Test name
Test status
Simulation time 26466845922 ps
CPU time 57.31 seconds
Started Jul 21 05:40:38 PM PDT 24
Finished Jul 21 05:41:35 PM PDT 24
Peak memory 201504 kb
Host smart-e3bffa27-1f9c-4583-8f3d-ca40511edb88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226751815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.226751815
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.2456189454
Short name T744
Test name
Test status
Simulation time 3056425652 ps
CPU time 2.63 seconds
Started Jul 21 05:40:43 PM PDT 24
Finished Jul 21 05:40:46 PM PDT 24
Peak memory 201464 kb
Host smart-d9d8a026-238f-4aac-a37a-e879137996ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456189454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.2456189454
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.1991339418
Short name T348
Test name
Test status
Simulation time 5830626098 ps
CPU time 7.69 seconds
Started Jul 21 05:40:36 PM PDT 24
Finished Jul 21 05:40:44 PM PDT 24
Peak memory 201620 kb
Host smart-9c1b0456-1e5a-4b88-8fb0-aa6bdf3d4475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991339418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.1991339418
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.723773451
Short name T337
Test name
Test status
Simulation time 29604117948 ps
CPU time 68.05 seconds
Started Jul 21 05:40:35 PM PDT 24
Finished Jul 21 05:41:43 PM PDT 24
Peak memory 210088 kb
Host smart-6259aa9e-34a3-466e-bacc-3a1a8e6cddd9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723773451 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.723773451
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.4042163176
Short name T796
Test name
Test status
Simulation time 299392138 ps
CPU time 0.92 seconds
Started Jul 21 05:40:44 PM PDT 24
Finished Jul 21 05:40:45 PM PDT 24
Peak memory 201600 kb
Host smart-63e52d33-3803-4550-9243-21c7efe7c23d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042163176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.4042163176
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.3929878348
Short name T722
Test name
Test status
Simulation time 290547043955 ps
CPU time 386.99 seconds
Started Jul 21 05:40:41 PM PDT 24
Finished Jul 21 05:47:08 PM PDT 24
Peak memory 201696 kb
Host smart-886074a6-a6fb-4c8e-90f5-85b856275d2e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929878348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gat
ing.3929878348
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.3841225424
Short name T266
Test name
Test status
Simulation time 326237642445 ps
CPU time 371.65 seconds
Started Jul 21 05:40:46 PM PDT 24
Finished Jul 21 05:46:58 PM PDT 24
Peak memory 201740 kb
Host smart-f6d3ceec-18f6-4255-91d1-c5328fb4649e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841225424 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.3841225424
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.1431974769
Short name T465
Test name
Test status
Simulation time 499637221906 ps
CPU time 1027.96 seconds
Started Jul 21 05:40:44 PM PDT 24
Finished Jul 21 05:57:52 PM PDT 24
Peak memory 201624 kb
Host smart-1140c896-36f5-4d5a-84c9-6e5efc92155d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431974769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interru
pt_fixed.1431974769
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.3433675075
Short name T160
Test name
Test status
Simulation time 166658613090 ps
CPU time 101.18 seconds
Started Jul 21 05:40:45 PM PDT 24
Finished Jul 21 05:42:26 PM PDT 24
Peak memory 201728 kb
Host smart-ce91765a-fa74-4f9e-a160-d8bf0c2efd48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433675075 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.3433675075
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.2844953510
Short name T426
Test name
Test status
Simulation time 333656383668 ps
CPU time 768.13 seconds
Started Jul 21 05:40:55 PM PDT 24
Finished Jul 21 05:53:44 PM PDT 24
Peak memory 201652 kb
Host smart-047bda0c-bbad-4e6a-98e4-88c23361c68b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844953510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fix
ed.2844953510
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.3326662679
Short name T606
Test name
Test status
Simulation time 531732248583 ps
CPU time 1272.99 seconds
Started Jul 21 05:40:42 PM PDT 24
Finished Jul 21 06:01:56 PM PDT 24
Peak memory 201724 kb
Host smart-c92de2ed-751d-48b0-a2fb-040d4484e0c3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326662679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters
_wakeup.3326662679
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.106395181
Short name T531
Test name
Test status
Simulation time 615305645134 ps
CPU time 342.49 seconds
Started Jul 21 05:40:48 PM PDT 24
Finished Jul 21 05:46:31 PM PDT 24
Peak memory 201700 kb
Host smart-0bc8fe42-4de5-4a97-8d5e-1f2ccb608711
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106395181 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
adc_ctrl_filters_wakeup_fixed.106395181
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.2557266999
Short name T786
Test name
Test status
Simulation time 119355817591 ps
CPU time 616.79 seconds
Started Jul 21 05:40:41 PM PDT 24
Finished Jul 21 05:50:59 PM PDT 24
Peak memory 202112 kb
Host smart-90d837a0-1279-4f86-9f80-4c7530545064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557266999 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.2557266999
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.84928855
Short name T10
Test name
Test status
Simulation time 39343663168 ps
CPU time 23.41 seconds
Started Jul 21 05:40:41 PM PDT 24
Finished Jul 21 05:41:05 PM PDT 24
Peak memory 201604 kb
Host smart-3ebdeadb-6d6e-4154-b300-53e4a33c49c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84928855 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.84928855
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.1721698767
Short name T681
Test name
Test status
Simulation time 3423243593 ps
CPU time 2.69 seconds
Started Jul 21 05:40:42 PM PDT 24
Finished Jul 21 05:40:45 PM PDT 24
Peak memory 201596 kb
Host smart-de04642c-2c41-4be9-8870-f621b32407a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721698767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.1721698767
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.1925966795
Short name T468
Test name
Test status
Simulation time 5762501023 ps
CPU time 3.85 seconds
Started Jul 21 05:40:49 PM PDT 24
Finished Jul 21 05:40:53 PM PDT 24
Peak memory 201516 kb
Host smart-13b84f9f-32a5-4293-b7e4-7ec0ba9dee01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925966795 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.1925966795
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.2960569735
Short name T675
Test name
Test status
Simulation time 156400968068 ps
CPU time 836.22 seconds
Started Jul 21 05:40:43 PM PDT 24
Finished Jul 21 05:54:39 PM PDT 24
Peak memory 202076 kb
Host smart-0221109b-27b9-4cd2-88d5-01f49a46b6d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960569735 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all
.2960569735
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.2360017705
Short name T469
Test name
Test status
Simulation time 552257338 ps
CPU time 0.94 seconds
Started Jul 21 05:40:49 PM PDT 24
Finished Jul 21 05:40:50 PM PDT 24
Peak memory 201548 kb
Host smart-d432b3db-1bc1-473b-830e-5d5997fd72dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360017705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.2360017705
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.3892833726
Short name T143
Test name
Test status
Simulation time 492589875434 ps
CPU time 172 seconds
Started Jul 21 05:40:48 PM PDT 24
Finished Jul 21 05:43:41 PM PDT 24
Peak memory 201760 kb
Host smart-e99f9914-2911-4117-85e4-219ee62cc93e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892833726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.3892833726
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.107243471
Short name T327
Test name
Test status
Simulation time 329808244398 ps
CPU time 767.88 seconds
Started Jul 21 05:40:47 PM PDT 24
Finished Jul 21 05:53:36 PM PDT 24
Peak memory 201732 kb
Host smart-5406aded-0d7c-42ee-9e61-7b7bde298313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107243471 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.107243471
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.1966748333
Short name T424
Test name
Test status
Simulation time 163904961899 ps
CPU time 332.79 seconds
Started Jul 21 05:40:48 PM PDT 24
Finished Jul 21 05:46:21 PM PDT 24
Peak memory 201608 kb
Host smart-8463459d-6c2d-49a6-9563-8b1918acc070
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966748333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interru
pt_fixed.1966748333
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.3284289703
Short name T256
Test name
Test status
Simulation time 326933972090 ps
CPU time 367.9 seconds
Started Jul 21 05:40:44 PM PDT 24
Finished Jul 21 05:46:52 PM PDT 24
Peak memory 201640 kb
Host smart-c3e464f2-a3b2-4147-b0aa-20859e71a6c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284289703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.3284289703
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.4109869392
Short name T583
Test name
Test status
Simulation time 485826297878 ps
CPU time 1038.86 seconds
Started Jul 21 05:40:40 PM PDT 24
Finished Jul 21 05:58:00 PM PDT 24
Peak memory 201608 kb
Host smart-fcedf8a3-8154-4b45-b9da-ec17bc54ae8f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109869392 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fix
ed.4109869392
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.1754914617
Short name T720
Test name
Test status
Simulation time 599778610080 ps
CPU time 374.8 seconds
Started Jul 21 05:40:52 PM PDT 24
Finished Jul 21 05:47:08 PM PDT 24
Peak memory 201720 kb
Host smart-a8832526-ac6a-4046-9a91-2b6234d2a6a3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754914617 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.adc_ctrl_filters_wakeup_fixed.1754914617
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.1868320168
Short name T682
Test name
Test status
Simulation time 133977767738 ps
CPU time 672.95 seconds
Started Jul 21 05:40:55 PM PDT 24
Finished Jul 21 05:52:08 PM PDT 24
Peak memory 202056 kb
Host smart-73883659-6280-43ff-86bf-74b1ff903357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868320168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.1868320168
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.1099402766
Short name T397
Test name
Test status
Simulation time 35352495346 ps
CPU time 75.89 seconds
Started Jul 21 05:40:47 PM PDT 24
Finished Jul 21 05:42:04 PM PDT 24
Peak memory 201548 kb
Host smart-499bd392-2ccf-462e-9bb7-de65a7b2d714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099402766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.1099402766
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.3575352824
Short name T367
Test name
Test status
Simulation time 5252185762 ps
CPU time 4.81 seconds
Started Jul 21 05:40:47 PM PDT 24
Finished Jul 21 05:40:53 PM PDT 24
Peak memory 201620 kb
Host smart-dfa903e7-ba7f-4ff4-9066-ddbb5b422850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575352824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.3575352824
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.1388484138
Short name T444
Test name
Test status
Simulation time 5614503946 ps
CPU time 7.17 seconds
Started Jul 21 05:40:40 PM PDT 24
Finished Jul 21 05:40:48 PM PDT 24
Peak memory 201476 kb
Host smart-e8a29ec1-f23f-4df4-97a0-338abbbbc0f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388484138 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.1388484138
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.3951526152
Short name T342
Test name
Test status
Simulation time 442772586487 ps
CPU time 1285.08 seconds
Started Jul 21 05:40:45 PM PDT 24
Finished Jul 21 06:02:11 PM PDT 24
Peak memory 218416 kb
Host smart-8c4d990b-3a87-4fd4-b3a3-a1834288a1de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951526152 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all
.3951526152
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.253257245
Short name T242
Test name
Test status
Simulation time 233590654041 ps
CPU time 136.68 seconds
Started Jul 21 05:40:48 PM PDT 24
Finished Jul 21 05:43:05 PM PDT 24
Peak memory 213116 kb
Host smart-8a496642-467b-49c4-b114-c16de0aa2d39
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253257245 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.253257245
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.3713430872
Short name T787
Test name
Test status
Simulation time 469608073 ps
CPU time 0.7 seconds
Started Jul 21 05:40:11 PM PDT 24
Finished Jul 21 05:40:13 PM PDT 24
Peak memory 201544 kb
Host smart-1dad5168-ad84-4e11-84c1-3ef8227b486e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713430872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.3713430872
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.3778488892
Short name T500
Test name
Test status
Simulation time 519356282722 ps
CPU time 207.8 seconds
Started Jul 21 05:40:13 PM PDT 24
Finished Jul 21 05:43:42 PM PDT 24
Peak memory 201544 kb
Host smart-b2da66b5-df18-4f13-9024-14bc921944f2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778488892 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gati
ng.3778488892
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.1231052297
Short name T581
Test name
Test status
Simulation time 177271776901 ps
CPU time 71.55 seconds
Started Jul 21 05:40:07 PM PDT 24
Finished Jul 21 05:41:19 PM PDT 24
Peak memory 201704 kb
Host smart-a2b952bb-f7a9-4fe8-a67f-65d5ced9fc36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231052297 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.1231052297
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.3382869388
Short name T522
Test name
Test status
Simulation time 324832231275 ps
CPU time 212.07 seconds
Started Jul 21 05:40:11 PM PDT 24
Finished Jul 21 05:43:44 PM PDT 24
Peak memory 201728 kb
Host smart-87c4666e-2d64-4c5e-b237-3d574b4845c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382869388 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.3382869388
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.2017081760
Short name T684
Test name
Test status
Simulation time 162675337184 ps
CPU time 203.52 seconds
Started Jul 21 05:40:09 PM PDT 24
Finished Jul 21 05:43:33 PM PDT 24
Peak memory 201736 kb
Host smart-53898f33-ea2d-4162-bb6a-18411b57e5a3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017081760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrup
t_fixed.2017081760
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.3674883968
Short name T201
Test name
Test status
Simulation time 160068001528 ps
CPU time 38.27 seconds
Started Jul 21 05:40:10 PM PDT 24
Finished Jul 21 05:40:49 PM PDT 24
Peak memory 201692 kb
Host smart-179f846a-3fde-4e14-86e5-cf2065d92921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674883968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.3674883968
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.362324939
Short name T491
Test name
Test status
Simulation time 327143538170 ps
CPU time 738.69 seconds
Started Jul 21 05:40:07 PM PDT 24
Finished Jul 21 05:52:26 PM PDT 24
Peak memory 201768 kb
Host smart-7e30dc68-ee1e-4980-9a28-2dc9bfd278fd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=362324939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixed
.362324939
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.412035276
Short name T291
Test name
Test status
Simulation time 366984393238 ps
CPU time 812.46 seconds
Started Jul 21 05:40:12 PM PDT 24
Finished Jul 21 05:53:45 PM PDT 24
Peak memory 201780 kb
Host smart-d72b9aee-728c-43c6-b0f3-6aa672cfb3bd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412035276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_w
akeup.412035276
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.2178978824
Short name T541
Test name
Test status
Simulation time 381326904664 ps
CPU time 425.02 seconds
Started Jul 21 05:40:09 PM PDT 24
Finished Jul 21 05:47:14 PM PDT 24
Peak memory 201616 kb
Host smart-a6693edf-091f-4bae-952b-0f2cf883ba9a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178978824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
adc_ctrl_filters_wakeup_fixed.2178978824
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.1209795804
Short name T343
Test name
Test status
Simulation time 100221015304 ps
CPU time 345.65 seconds
Started Jul 21 05:40:11 PM PDT 24
Finished Jul 21 05:45:58 PM PDT 24
Peak memory 201996 kb
Host smart-8176f384-a4aa-4830-9ed5-282934fe269c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209795804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.1209795804
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.275970836
Short name T767
Test name
Test status
Simulation time 29732989767 ps
CPU time 17.94 seconds
Started Jul 21 05:40:08 PM PDT 24
Finished Jul 21 05:40:26 PM PDT 24
Peak memory 201496 kb
Host smart-037f995c-307d-4517-9af8-88b3d2b1de0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275970836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.275970836
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.318412580
Short name T763
Test name
Test status
Simulation time 4381337301 ps
CPU time 11 seconds
Started Jul 21 05:40:10 PM PDT 24
Finished Jul 21 05:40:21 PM PDT 24
Peak memory 201608 kb
Host smart-9f256387-c418-4faa-a583-f5d9705b0a86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318412580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.318412580
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.236493517
Short name T53
Test name
Test status
Simulation time 7884277100 ps
CPU time 5.77 seconds
Started Jul 21 05:40:10 PM PDT 24
Finished Jul 21 05:40:17 PM PDT 24
Peak memory 218320 kb
Host smart-1ec4de35-1c32-48d9-9a54-9e8a07802b12
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236493517 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.236493517
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.2906660592
Short name T421
Test name
Test status
Simulation time 5672006377 ps
CPU time 13.47 seconds
Started Jul 21 05:40:07 PM PDT 24
Finished Jul 21 05:40:21 PM PDT 24
Peak memory 201596 kb
Host smart-d7d5e2fb-f61b-4715-b1d4-017d214a15b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906660592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.2906660592
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.2564828952
Short name T674
Test name
Test status
Simulation time 75594293165 ps
CPU time 54.44 seconds
Started Jul 21 05:40:08 PM PDT 24
Finished Jul 21 05:41:03 PM PDT 24
Peak memory 201932 kb
Host smart-409987ec-acec-4f84-8556-02f7389c215e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564828952 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.2564828952
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.2663940808
Short name T382
Test name
Test status
Simulation time 570609812 ps
CPU time 0.76 seconds
Started Jul 21 05:40:51 PM PDT 24
Finished Jul 21 05:40:52 PM PDT 24
Peak memory 201544 kb
Host smart-f5e49f92-7d3b-4366-a4f6-682ab7d49421
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663940808 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.2663940808
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.1563112982
Short name T82
Test name
Test status
Simulation time 321620839787 ps
CPU time 215.32 seconds
Started Jul 21 05:40:54 PM PDT 24
Finished Jul 21 05:44:30 PM PDT 24
Peak memory 201740 kb
Host smart-bd9c0d1b-f1b7-44c9-86e3-69e2d9dea930
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563112982 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gat
ing.1563112982
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.681963421
Short name T778
Test name
Test status
Simulation time 394031350724 ps
CPU time 433.74 seconds
Started Jul 21 05:40:57 PM PDT 24
Finished Jul 21 05:48:11 PM PDT 24
Peak memory 201792 kb
Host smart-7daa620e-80a7-4254-8ec2-bd39182b8c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681963421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.681963421
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.3928417542
Short name T648
Test name
Test status
Simulation time 327634041119 ps
CPU time 194.97 seconds
Started Jul 21 05:40:53 PM PDT 24
Finished Jul 21 05:44:08 PM PDT 24
Peak memory 201692 kb
Host smart-0209f98f-cb54-46e8-8fb4-80677bb04ea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928417542 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.3928417542
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.2755029110
Short name T643
Test name
Test status
Simulation time 160323972090 ps
CPU time 370.85 seconds
Started Jul 21 05:40:54 PM PDT 24
Finished Jul 21 05:47:06 PM PDT 24
Peak memory 201592 kb
Host smart-d045d036-184d-444f-a6d5-6692524fd776
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755029110 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interru
pt_fixed.2755029110
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.3479715006
Short name T464
Test name
Test status
Simulation time 161942420922 ps
CPU time 98.48 seconds
Started Jul 21 05:40:48 PM PDT 24
Finished Jul 21 05:42:27 PM PDT 24
Peak memory 201660 kb
Host smart-989b0bfd-0b89-4d08-ac23-240cfcc1e4d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479715006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.3479715006
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.1935358030
Short name T514
Test name
Test status
Simulation time 324874043339 ps
CPU time 802.56 seconds
Started Jul 21 05:41:00 PM PDT 24
Finished Jul 21 05:54:23 PM PDT 24
Peak memory 201560 kb
Host smart-d428d64d-aee0-402d-9e22-6b2564247de8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935358030 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fix
ed.1935358030
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.2282466864
Short name T212
Test name
Test status
Simulation time 537295047282 ps
CPU time 190.68 seconds
Started Jul 21 05:41:01 PM PDT 24
Finished Jul 21 05:44:12 PM PDT 24
Peak memory 201576 kb
Host smart-d7815d15-7fbb-4f1e-b9a8-54466f7f8502
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282466864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters
_wakeup.2282466864
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.3500525847
Short name T416
Test name
Test status
Simulation time 626367529462 ps
CPU time 353.75 seconds
Started Jul 21 05:41:01 PM PDT 24
Finished Jul 21 05:46:55 PM PDT 24
Peak memory 201568 kb
Host smart-871f38cc-201f-4b31-83f2-dde0f0faaa57
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500525847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.adc_ctrl_filters_wakeup_fixed.3500525847
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.2275149233
Short name T336
Test name
Test status
Simulation time 114800720073 ps
CPU time 391.7 seconds
Started Jul 21 05:40:52 PM PDT 24
Finished Jul 21 05:47:24 PM PDT 24
Peak memory 202216 kb
Host smart-89498b10-b840-4215-a4f7-08f46b16647a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275149233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.2275149233
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.785196775
Short name T544
Test name
Test status
Simulation time 26630806924 ps
CPU time 56.89 seconds
Started Jul 21 05:41:01 PM PDT 24
Finished Jul 21 05:41:59 PM PDT 24
Peak memory 201424 kb
Host smart-86413404-24ff-4cb1-9b63-80e586106760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785196775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.785196775
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.3982709534
Short name T403
Test name
Test status
Simulation time 5194304495 ps
CPU time 4.03 seconds
Started Jul 21 05:40:54 PM PDT 24
Finished Jul 21 05:40:59 PM PDT 24
Peak memory 201744 kb
Host smart-15e8c87f-dc76-4acc-931e-fa8b6612aa81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982709534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.3982709534
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.1267564551
Short name T523
Test name
Test status
Simulation time 5679464323 ps
CPU time 13.34 seconds
Started Jul 21 05:40:51 PM PDT 24
Finished Jul 21 05:41:05 PM PDT 24
Peak memory 201660 kb
Host smart-6e52768a-cb12-44af-8484-4555d312738e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267564551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.1267564551
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.3333889569
Short name T554
Test name
Test status
Simulation time 360714489902 ps
CPU time 815.66 seconds
Started Jul 21 05:40:51 PM PDT 24
Finished Jul 21 05:54:27 PM PDT 24
Peak memory 201548 kb
Host smart-9aebe04c-f9a9-4938-8e9b-957127598bba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333889569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all
.3333889569
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.2376883755
Short name T374
Test name
Test status
Simulation time 303086635 ps
CPU time 0.78 seconds
Started Jul 21 05:40:59 PM PDT 24
Finished Jul 21 05:41:00 PM PDT 24
Peak memory 201432 kb
Host smart-26619a90-c22f-41b4-97a6-7f8fe1a18b7d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376883755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.2376883755
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.980065447
Short name T278
Test name
Test status
Simulation time 165145050636 ps
CPU time 373.35 seconds
Started Jul 21 05:40:58 PM PDT 24
Finished Jul 21 05:47:12 PM PDT 24
Peak memory 201688 kb
Host smart-f8d7d365-8ded-481a-a0be-790b3e552fea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980065447 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.980065447
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.887785901
Short name T545
Test name
Test status
Simulation time 164168981326 ps
CPU time 95 seconds
Started Jul 21 05:41:00 PM PDT 24
Finished Jul 21 05:42:35 PM PDT 24
Peak memory 201584 kb
Host smart-3012f7ad-2adb-4251-b7fd-fa87d4f806c4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=887785901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrup
t_fixed.887785901
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.1202401095
Short name T532
Test name
Test status
Simulation time 160256432027 ps
CPU time 148.75 seconds
Started Jul 21 05:41:01 PM PDT 24
Finished Jul 21 05:43:30 PM PDT 24
Peak memory 201628 kb
Host smart-ff55ac83-d216-4bad-94cf-68146a453e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202401095 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.1202401095
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.3030659037
Short name T69
Test name
Test status
Simulation time 334047121515 ps
CPU time 774.05 seconds
Started Jul 21 05:41:01 PM PDT 24
Finished Jul 21 05:53:56 PM PDT 24
Peak memory 201564 kb
Host smart-e8b994f3-51e9-4521-8b9c-50758df578f8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030659037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fix
ed.3030659037
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.1254710075
Short name T207
Test name
Test status
Simulation time 182244146284 ps
CPU time 203.99 seconds
Started Jul 21 05:41:01 PM PDT 24
Finished Jul 21 05:44:26 PM PDT 24
Peak memory 201772 kb
Host smart-777fa1ad-bdae-4a2f-bfa3-c189df623f77
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254710075 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters
_wakeup.1254710075
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.4196972999
Short name T358
Test name
Test status
Simulation time 194721240569 ps
CPU time 46.18 seconds
Started Jul 21 05:40:59 PM PDT 24
Finished Jul 21 05:41:46 PM PDT 24
Peak memory 201720 kb
Host smart-066d652b-63c7-4578-bebe-34f6d308b736
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196972999 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.adc_ctrl_filters_wakeup_fixed.4196972999
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.1339655352
Short name T695
Test name
Test status
Simulation time 125182021749 ps
CPU time 447.74 seconds
Started Jul 21 05:40:59 PM PDT 24
Finished Jul 21 05:48:27 PM PDT 24
Peak memory 202104 kb
Host smart-e84389b0-873f-4820-8abc-fa76b37a5dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339655352 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.1339655352
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.3768189183
Short name T372
Test name
Test status
Simulation time 40714871491 ps
CPU time 47.21 seconds
Started Jul 21 05:40:59 PM PDT 24
Finished Jul 21 05:41:47 PM PDT 24
Peak memory 201544 kb
Host smart-4545d0c6-76a9-4888-b117-d44c0bc6a3e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768189183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.3768189183
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.2534442448
Short name T383
Test name
Test status
Simulation time 2890994398 ps
CPU time 2.31 seconds
Started Jul 21 05:40:58 PM PDT 24
Finished Jul 21 05:41:01 PM PDT 24
Peak memory 201584 kb
Host smart-6b7160ea-ae5f-4a9e-b13e-790b5f59cc87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534442448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.2534442448
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.2177995411
Short name T568
Test name
Test status
Simulation time 5698234470 ps
CPU time 4.12 seconds
Started Jul 21 05:40:55 PM PDT 24
Finished Jul 21 05:41:00 PM PDT 24
Peak memory 201604 kb
Host smart-4554808b-8c2b-472e-b36d-c26081150000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177995411 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.2177995411
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.2105458384
Short name T269
Test name
Test status
Simulation time 194164979459 ps
CPU time 210.65 seconds
Started Jul 21 05:41:00 PM PDT 24
Finished Jul 21 05:44:31 PM PDT 24
Peak memory 201724 kb
Host smart-8510d9e2-2879-4039-b6eb-7040eb1ee4f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105458384 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all
.2105458384
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.2770094724
Short name T243
Test name
Test status
Simulation time 91006255010 ps
CPU time 44.71 seconds
Started Jul 21 05:40:58 PM PDT 24
Finished Jul 21 05:41:43 PM PDT 24
Peak memory 201908 kb
Host smart-c3b3a37a-ea1c-44d0-bb14-36be0300db13
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770094724 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.2770094724
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.3860284607
Short name T62
Test name
Test status
Simulation time 490403000 ps
CPU time 1.22 seconds
Started Jul 21 05:41:07 PM PDT 24
Finished Jul 21 05:41:08 PM PDT 24
Peak memory 201512 kb
Host smart-b04d93eb-9fc7-4451-a036-4a471760ed6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860284607 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.3860284607
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.3954581409
Short name T205
Test name
Test status
Simulation time 525025126006 ps
CPU time 1235.99 seconds
Started Jul 21 05:41:06 PM PDT 24
Finished Jul 21 06:01:43 PM PDT 24
Peak memory 201668 kb
Host smart-4c819bb4-1a90-477b-a64c-622eca45bf26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954581409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.3954581409
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.2552361656
Short name T694
Test name
Test status
Simulation time 502792088590 ps
CPU time 1216.73 seconds
Started Jul 21 05:41:00 PM PDT 24
Finished Jul 21 06:01:17 PM PDT 24
Peak memory 201736 kb
Host smart-1f3033bb-85f9-481d-889e-2c72fdb592c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552361656 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.2552361656
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.2296660349
Short name T512
Test name
Test status
Simulation time 493056565703 ps
CPU time 598.64 seconds
Started Jul 21 05:41:02 PM PDT 24
Finished Jul 21 05:51:01 PM PDT 24
Peak memory 201720 kb
Host smart-8c3f5568-dfcd-4ef5-906c-54d84c2bb946
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296660349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interru
pt_fixed.2296660349
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.3980804773
Short name T355
Test name
Test status
Simulation time 324219249416 ps
CPU time 210.64 seconds
Started Jul 21 05:40:58 PM PDT 24
Finished Jul 21 05:44:29 PM PDT 24
Peak memory 201728 kb
Host smart-4331b04b-4e9e-46c4-9548-f65d2304498e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980804773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fix
ed.3980804773
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.2623873608
Short name T765
Test name
Test status
Simulation time 98533930862 ps
CPU time 374.69 seconds
Started Jul 21 05:41:06 PM PDT 24
Finished Jul 21 05:47:20 PM PDT 24
Peak memory 202140 kb
Host smart-edc2e204-9347-4b05-a478-94410492543d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623873608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.2623873608
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.2534587409
Short name T454
Test name
Test status
Simulation time 34964635053 ps
CPU time 78.45 seconds
Started Jul 21 05:41:14 PM PDT 24
Finished Jul 21 05:42:33 PM PDT 24
Peak memory 201608 kb
Host smart-c7278598-89b4-4444-ae4f-589677989f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534587409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.2534587409
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.2324674741
Short name T402
Test name
Test status
Simulation time 2846589588 ps
CPU time 7.09 seconds
Started Jul 21 05:41:07 PM PDT 24
Finished Jul 21 05:41:14 PM PDT 24
Peak memory 201596 kb
Host smart-d1c4fac1-c43f-4093-b38a-511dac4029bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324674741 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.2324674741
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.1044291886
Short name T430
Test name
Test status
Simulation time 6020755235 ps
CPU time 3.92 seconds
Started Jul 21 05:40:58 PM PDT 24
Finished Jul 21 05:41:03 PM PDT 24
Peak memory 201612 kb
Host smart-04ebecdc-86d4-448c-8f2e-ee0fb9c49c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044291886 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.1044291886
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.834972011
Short name T676
Test name
Test status
Simulation time 340770522707 ps
CPU time 210.22 seconds
Started Jul 21 05:41:05 PM PDT 24
Finished Jul 21 05:44:36 PM PDT 24
Peak memory 201740 kb
Host smart-56ea92b6-2716-4e9f-ab22-5f580eb4a6a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834972011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all.
834972011
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.1286060937
Short name T25
Test name
Test status
Simulation time 44293842716 ps
CPU time 48.6 seconds
Started Jul 21 05:41:07 PM PDT 24
Finished Jul 21 05:41:56 PM PDT 24
Peak memory 210008 kb
Host smart-d734e164-8888-4c5c-919e-f122ff5e514f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286060937 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.1286060937
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.1995255215
Short name T83
Test name
Test status
Simulation time 497467572 ps
CPU time 1.74 seconds
Started Jul 21 05:41:09 PM PDT 24
Finished Jul 21 05:41:11 PM PDT 24
Peak memory 201532 kb
Host smart-e916bb29-98df-47e8-8bb4-045f52d0c4cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995255215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.1995255215
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.3324702428
Short name T182
Test name
Test status
Simulation time 371048199504 ps
CPU time 364.86 seconds
Started Jul 21 05:41:10 PM PDT 24
Finished Jul 21 05:47:16 PM PDT 24
Peak memory 201628 kb
Host smart-2177353a-d28c-4afb-bbfe-5a45889e9dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324702428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.3324702428
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.3815417194
Short name T200
Test name
Test status
Simulation time 322899501516 ps
CPU time 625.87 seconds
Started Jul 21 05:41:07 PM PDT 24
Finished Jul 21 05:51:33 PM PDT 24
Peak memory 201652 kb
Host smart-7ed3c58b-5a4b-42de-9d49-0b8d4e683fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815417194 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.3815417194
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.2182089044
Short name T139
Test name
Test status
Simulation time 167027678454 ps
CPU time 63.1 seconds
Started Jul 21 05:41:05 PM PDT 24
Finished Jul 21 05:42:08 PM PDT 24
Peak memory 201772 kb
Host smart-7221b953-ea20-4a48-9014-ab85a0503361
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182089044 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interru
pt_fixed.2182089044
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.3202092513
Short name T127
Test name
Test status
Simulation time 489238881149 ps
CPU time 320.01 seconds
Started Jul 21 05:41:06 PM PDT 24
Finished Jul 21 05:46:27 PM PDT 24
Peak memory 201732 kb
Host smart-98423bd8-5ae5-4b2f-90eb-41e88b70a60a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202092513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.3202092513
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.1960309391
Short name T392
Test name
Test status
Simulation time 328862725234 ps
CPU time 592.36 seconds
Started Jul 21 05:41:05 PM PDT 24
Finished Jul 21 05:50:58 PM PDT 24
Peak memory 201708 kb
Host smart-69a6996e-3656-4c65-8676-cbdbdcd8e2ff
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960309391 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fix
ed.1960309391
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.2471180759
Short name T735
Test name
Test status
Simulation time 381276008618 ps
CPU time 101.96 seconds
Started Jul 21 05:41:11 PM PDT 24
Finished Jul 21 05:42:53 PM PDT 24
Peak memory 201808 kb
Host smart-586d2910-ca90-45e4-8be7-8a9d23ded3ef
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471180759 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters
_wakeup.2471180759
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.3736563471
Short name T364
Test name
Test status
Simulation time 198918844158 ps
CPU time 115.1 seconds
Started Jul 21 05:41:14 PM PDT 24
Finished Jul 21 05:43:10 PM PDT 24
Peak memory 201724 kb
Host smart-17c3ffd1-a606-4006-ac84-f6f603510acc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736563471 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.adc_ctrl_filters_wakeup_fixed.3736563471
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.2901111891
Short name T742
Test name
Test status
Simulation time 37475911008 ps
CPU time 81.43 seconds
Started Jul 21 05:41:10 PM PDT 24
Finished Jul 21 05:42:32 PM PDT 24
Peak memory 201600 kb
Host smart-97c4ce37-1a1e-480c-83b6-a7c9cfd49b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901111891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.2901111891
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.1396091410
Short name T712
Test name
Test status
Simulation time 4857112716 ps
CPU time 12.86 seconds
Started Jul 21 05:41:11 PM PDT 24
Finished Jul 21 05:41:24 PM PDT 24
Peak memory 201608 kb
Host smart-03bfe05d-e3b8-4c5a-a978-6d5b10e9db87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396091410 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.1396091410
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.101527809
Short name T773
Test name
Test status
Simulation time 5759377021 ps
CPU time 4.34 seconds
Started Jul 21 05:41:04 PM PDT 24
Finished Jul 21 05:41:09 PM PDT 24
Peak memory 201604 kb
Host smart-8c7c147b-3887-4879-b86a-43f4eb8da4d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101527809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.101527809
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.2451568188
Short name T319
Test name
Test status
Simulation time 67924261895 ps
CPU time 35.22 seconds
Started Jul 21 05:41:13 PM PDT 24
Finished Jul 21 05:41:48 PM PDT 24
Peak memory 210072 kb
Host smart-367cf585-d286-4ff4-878b-c5ac75a0c0fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451568188 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.2451568188
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.2314224333
Short name T479
Test name
Test status
Simulation time 378854751 ps
CPU time 0.75 seconds
Started Jul 21 05:41:18 PM PDT 24
Finished Jul 21 05:41:19 PM PDT 24
Peak memory 201564 kb
Host smart-9489956f-6238-4468-b9de-4c490d9505dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314224333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.2314224333
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.1674220503
Short name T699
Test name
Test status
Simulation time 357547467176 ps
CPU time 434.94 seconds
Started Jul 21 05:41:19 PM PDT 24
Finished Jul 21 05:48:34 PM PDT 24
Peak memory 201744 kb
Host smart-7a8aaea3-5b61-4161-b23c-5db200b0b4bf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674220503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gat
ing.1674220503
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.1546202529
Short name T248
Test name
Test status
Simulation time 165926328167 ps
CPU time 182.38 seconds
Started Jul 21 05:41:16 PM PDT 24
Finished Jul 21 05:44:18 PM PDT 24
Peak memory 201644 kb
Host smart-ad3a392e-14d5-4647-9d12-e75ef94099b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546202529 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.1546202529
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.4062170012
Short name T265
Test name
Test status
Simulation time 331882045465 ps
CPU time 105.23 seconds
Started Jul 21 05:41:10 PM PDT 24
Finished Jul 21 05:42:56 PM PDT 24
Peak memory 201788 kb
Host smart-310771e2-b28d-4e96-9c61-74a6ceeb339f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062170012 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.4062170012
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.4090478946
Short name T370
Test name
Test status
Simulation time 320448913417 ps
CPU time 198.24 seconds
Started Jul 21 05:41:10 PM PDT 24
Finished Jul 21 05:44:29 PM PDT 24
Peak memory 201716 kb
Host smart-d2064cbb-6021-427b-8fcb-c9df25e91b3a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090478946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interru
pt_fixed.4090478946
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.585381318
Short name T5
Test name
Test status
Simulation time 501747131096 ps
CPU time 100.68 seconds
Started Jul 21 05:41:11 PM PDT 24
Finished Jul 21 05:42:52 PM PDT 24
Peak memory 201816 kb
Host smart-93f37509-9c6a-4022-ba6c-b2af588b7726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585381318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.585381318
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.1534579211
Short name T525
Test name
Test status
Simulation time 496315031574 ps
CPU time 561.22 seconds
Started Jul 21 05:41:11 PM PDT 24
Finished Jul 21 05:50:32 PM PDT 24
Peak memory 201792 kb
Host smart-46d31861-5925-424d-979d-aa4af2db75cd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534579211 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fix
ed.1534579211
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.3457529883
Short name T241
Test name
Test status
Simulation time 391803366485 ps
CPU time 214.13 seconds
Started Jul 21 05:41:12 PM PDT 24
Finished Jul 21 05:44:46 PM PDT 24
Peak memory 201612 kb
Host smart-c7b67397-c30b-4ce7-b2af-76f041189084
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457529883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters
_wakeup.3457529883
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.1646789363
Short name T4
Test name
Test status
Simulation time 407331522035 ps
CPU time 247.89 seconds
Started Jul 21 05:41:17 PM PDT 24
Finished Jul 21 05:45:26 PM PDT 24
Peak memory 201776 kb
Host smart-89f9e5f3-0f75-4052-b5ef-79c6d17c96cb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646789363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.adc_ctrl_filters_wakeup_fixed.1646789363
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.1578981448
Short name T460
Test name
Test status
Simulation time 23084816618 ps
CPU time 26.52 seconds
Started Jul 21 05:41:17 PM PDT 24
Finished Jul 21 05:41:44 PM PDT 24
Peak memory 201572 kb
Host smart-89aa4ec2-32a7-45d5-9f77-d22c7e5954e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578981448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.1578981448
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.716375674
Short name T565
Test name
Test status
Simulation time 5186353079 ps
CPU time 12.19 seconds
Started Jul 21 05:41:16 PM PDT 24
Finished Jul 21 05:41:29 PM PDT 24
Peak memory 201588 kb
Host smart-af9cd42a-d60a-49ea-9ef0-4f422d842202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716375674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.716375674
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.4126666981
Short name T571
Test name
Test status
Simulation time 6124440524 ps
CPU time 4.35 seconds
Started Jul 21 05:41:11 PM PDT 24
Finished Jul 21 05:41:16 PM PDT 24
Peak memory 201496 kb
Host smart-2d45a441-1d6d-403a-8d86-9b1c92dbca10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126666981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.4126666981
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.797917341
Short name T290
Test name
Test status
Simulation time 170258610915 ps
CPU time 51.64 seconds
Started Jul 21 05:41:17 PM PDT 24
Finished Jul 21 05:42:09 PM PDT 24
Peak memory 201716 kb
Host smart-18d77d17-6923-4cf4-952a-6db9f023bb28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797917341 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all.
797917341
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.629040822
Short name T19
Test name
Test status
Simulation time 275567025558 ps
CPU time 161.07 seconds
Started Jul 21 05:41:16 PM PDT 24
Finished Jul 21 05:43:57 PM PDT 24
Peak memory 210096 kb
Host smart-98c7ef18-7e8e-48dc-89c8-efbad93d6720
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629040822 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.629040822
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.2815784064
Short name T792
Test name
Test status
Simulation time 422255414 ps
CPU time 1.55 seconds
Started Jul 21 05:41:21 PM PDT 24
Finished Jul 21 05:41:23 PM PDT 24
Peak memory 201536 kb
Host smart-ca93c2a2-754c-40f2-a50e-5cb327cc9114
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815784064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.2815784064
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.1537877307
Short name T711
Test name
Test status
Simulation time 338509504483 ps
CPU time 301.46 seconds
Started Jul 21 05:41:21 PM PDT 24
Finished Jul 21 05:46:23 PM PDT 24
Peak memory 201640 kb
Host smart-7f53c214-cd0a-4961-bb1a-072245239a04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537877307 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.1537877307
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.2669878432
Short name T93
Test name
Test status
Simulation time 498871507687 ps
CPU time 266.74 seconds
Started Jul 21 05:41:20 PM PDT 24
Finished Jul 21 05:45:47 PM PDT 24
Peak memory 201800 kb
Host smart-8c16b2ee-731a-45df-90ac-6928dc34b756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669878432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.2669878432
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.3898209824
Short name T755
Test name
Test status
Simulation time 166715758560 ps
CPU time 361.48 seconds
Started Jul 21 05:41:22 PM PDT 24
Finished Jul 21 05:47:24 PM PDT 24
Peak memory 201724 kb
Host smart-9302a396-682b-418e-afb6-fe48f58e0d83
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898209824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interru
pt_fixed.3898209824
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.2466478964
Short name T316
Test name
Test status
Simulation time 487862946815 ps
CPU time 357.26 seconds
Started Jul 21 05:41:18 PM PDT 24
Finished Jul 21 05:47:16 PM PDT 24
Peak memory 201724 kb
Host smart-b0d94a24-0b96-417b-aaaa-222ed60125c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466478964 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.2466478964
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.113243350
Short name T362
Test name
Test status
Simulation time 497484930749 ps
CPU time 1062.04 seconds
Started Jul 21 05:41:20 PM PDT 24
Finished Jul 21 05:59:02 PM PDT 24
Peak memory 201636 kb
Host smart-df7236fa-0aa9-4beb-9c1b-b0e8984e5eea
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=113243350 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fixe
d.113243350
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.3092419978
Short name T183
Test name
Test status
Simulation time 345525695351 ps
CPU time 807.72 seconds
Started Jul 21 05:41:23 PM PDT 24
Finished Jul 21 05:54:51 PM PDT 24
Peak memory 201744 kb
Host smart-5ded4ae7-6a8a-4381-a279-f0dbe1a08165
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092419978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters
_wakeup.3092419978
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.1025076481
Short name T537
Test name
Test status
Simulation time 596596776418 ps
CPU time 788.8 seconds
Started Jul 21 05:41:21 PM PDT 24
Finished Jul 21 05:54:31 PM PDT 24
Peak memory 201716 kb
Host smart-a801dea0-9b24-4b29-9456-1b31a84ea3c8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025076481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25
.adc_ctrl_filters_wakeup_fixed.1025076481
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.327338920
Short name T94
Test name
Test status
Simulation time 72793843000 ps
CPU time 377.39 seconds
Started Jul 21 05:41:22 PM PDT 24
Finished Jul 21 05:47:40 PM PDT 24
Peak memory 202008 kb
Host smart-d78a5a00-27e7-4d15-a6b4-cbd896ccec47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327338920 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.327338920
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.3812209571
Short name T146
Test name
Test status
Simulation time 40654877260 ps
CPU time 16.72 seconds
Started Jul 21 05:41:23 PM PDT 24
Finished Jul 21 05:41:40 PM PDT 24
Peak memory 201520 kb
Host smart-3f18ace7-7e1d-434f-a119-34f993c72aee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812209571 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.3812209571
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.3389856528
Short name T572
Test name
Test status
Simulation time 4530861574 ps
CPU time 10.83 seconds
Started Jul 21 05:41:23 PM PDT 24
Finished Jul 21 05:41:34 PM PDT 24
Peak memory 201424 kb
Host smart-749b546c-2cc0-4910-a637-303238584ed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389856528 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.3389856528
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.2693061783
Short name T516
Test name
Test status
Simulation time 5821502556 ps
CPU time 9.99 seconds
Started Jul 21 05:41:18 PM PDT 24
Finished Jul 21 05:41:28 PM PDT 24
Peak memory 201572 kb
Host smart-a3c97247-2a25-45b8-95b3-6607c4080eae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693061783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.2693061783
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.488358271
Short name T745
Test name
Test status
Simulation time 40350277090 ps
CPU time 45.52 seconds
Started Jul 21 05:41:25 PM PDT 24
Finished Jul 21 05:42:10 PM PDT 24
Peak memory 201732 kb
Host smart-11b1bccc-1b7e-45f7-8524-558ffd126972
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488358271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all.
488358271
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.3747031854
Short name T21
Test name
Test status
Simulation time 143542174140 ps
CPU time 144.19 seconds
Started Jul 21 05:41:23 PM PDT 24
Finished Jul 21 05:43:47 PM PDT 24
Peak memory 209948 kb
Host smart-ff5c5c63-c6d9-474d-8c57-67ee82c5e78b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747031854 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.3747031854
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.108582666
Short name T61
Test name
Test status
Simulation time 436295226 ps
CPU time 1.2 seconds
Started Jul 21 05:41:36 PM PDT 24
Finished Jul 21 05:41:38 PM PDT 24
Peak memory 201556 kb
Host smart-24055e28-d1d4-4527-bd2e-83c1ffed3607
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108582666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.108582666
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.1004790605
Short name T247
Test name
Test status
Simulation time 202973496871 ps
CPU time 414.14 seconds
Started Jul 21 05:41:35 PM PDT 24
Finished Jul 21 05:48:30 PM PDT 24
Peak memory 201788 kb
Host smart-38292fd9-7096-4cdf-83e2-d731ce1d26a4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004790605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gat
ing.1004790605
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.3249795212
Short name T285
Test name
Test status
Simulation time 345029956960 ps
CPU time 199.25 seconds
Started Jul 21 05:41:37 PM PDT 24
Finished Jul 21 05:44:56 PM PDT 24
Peak memory 201728 kb
Host smart-d55c3557-e5bf-4f4d-8b02-b066a4e597bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249795212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.3249795212
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.4112034719
Short name T311
Test name
Test status
Simulation time 324682751122 ps
CPU time 168.62 seconds
Started Jul 21 05:41:32 PM PDT 24
Finished Jul 21 05:44:21 PM PDT 24
Peak memory 201784 kb
Host smart-52a118bf-5500-45f7-9867-46902924ad87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112034719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.4112034719
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.2404509187
Short name T379
Test name
Test status
Simulation time 329186643570 ps
CPU time 58.05 seconds
Started Jul 21 05:41:29 PM PDT 24
Finished Jul 21 05:42:27 PM PDT 24
Peak memory 201624 kb
Host smart-2eedc88a-1145-4945-8802-526b47b84db8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404509187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interru
pt_fixed.2404509187
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.1115946726
Short name T752
Test name
Test status
Simulation time 325100132661 ps
CPU time 206.06 seconds
Started Jul 21 05:41:30 PM PDT 24
Finished Jul 21 05:44:57 PM PDT 24
Peak memory 201796 kb
Host smart-9d5e60cd-2fec-4997-84ab-af7977f3d89f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115946726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.1115946726
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.3157830626
Short name T704
Test name
Test status
Simulation time 497278734441 ps
CPU time 586.48 seconds
Started Jul 21 05:41:29 PM PDT 24
Finished Jul 21 05:51:16 PM PDT 24
Peak memory 201632 kb
Host smart-1d27214c-7d74-419c-8135-c800d967163e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157830626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fix
ed.3157830626
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.3994029727
Short name T6
Test name
Test status
Simulation time 176161459940 ps
CPU time 197.73 seconds
Started Jul 21 05:41:31 PM PDT 24
Finished Jul 21 05:44:49 PM PDT 24
Peak memory 201676 kb
Host smart-45d5aa16-6a76-4e8d-8754-92b76bb7bf61
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994029727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters
_wakeup.3994029727
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.3367714252
Short name T163
Test name
Test status
Simulation time 203014733477 ps
CPU time 90.11 seconds
Started Jul 21 05:41:36 PM PDT 24
Finished Jul 21 05:43:07 PM PDT 24
Peak memory 201732 kb
Host smart-6df14bbe-6418-46a5-b56b-a87dc5746b72
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367714252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.adc_ctrl_filters_wakeup_fixed.3367714252
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.254857718
Short name T793
Test name
Test status
Simulation time 76093109812 ps
CPU time 259.28 seconds
Started Jul 21 05:41:37 PM PDT 24
Finished Jul 21 05:45:57 PM PDT 24
Peak memory 201856 kb
Host smart-4229ad79-35ce-4e4a-9ef9-42df102a4e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254857718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.254857718
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.2731631023
Short name T380
Test name
Test status
Simulation time 29727780589 ps
CPU time 69.57 seconds
Started Jul 21 05:41:35 PM PDT 24
Finished Jul 21 05:42:45 PM PDT 24
Peak memory 201600 kb
Host smart-2b7354d6-c93b-4c0d-bc50-910f3c088bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731631023 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.2731631023
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.370961891
Short name T386
Test name
Test status
Simulation time 4916559278 ps
CPU time 5.78 seconds
Started Jul 21 05:41:36 PM PDT 24
Finished Jul 21 05:41:42 PM PDT 24
Peak memory 201620 kb
Host smart-ac8ba151-d9f0-4377-9999-5418bcacfc9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370961891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.370961891
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.2352006690
Short name T455
Test name
Test status
Simulation time 5863100299 ps
CPU time 3.33 seconds
Started Jul 21 05:41:32 PM PDT 24
Finished Jul 21 05:41:36 PM PDT 24
Peak memory 201512 kb
Host smart-c644d89c-a40a-47c1-96d7-f0c3d16e2f66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352006690 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.2352006690
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.4122019529
Short name T743
Test name
Test status
Simulation time 168378568082 ps
CPU time 360.55 seconds
Started Jul 21 05:41:37 PM PDT 24
Finished Jul 21 05:47:37 PM PDT 24
Peak memory 201608 kb
Host smart-00a896fb-d27a-4e67-ae53-8bc92ede88ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122019529 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all
.4122019529
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.250571909
Short name T679
Test name
Test status
Simulation time 236085565476 ps
CPU time 253.94 seconds
Started Jul 21 05:41:37 PM PDT 24
Finished Jul 21 05:45:52 PM PDT 24
Peak memory 217552 kb
Host smart-72c9f0d0-d090-4c07-8c77-3e8e2cbd096f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250571909 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.250571909
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.996709773
Short name T446
Test name
Test status
Simulation time 405878247 ps
CPU time 0.68 seconds
Started Jul 21 05:41:48 PM PDT 24
Finished Jul 21 05:41:49 PM PDT 24
Peak memory 201488 kb
Host smart-5ebea06d-629e-4b74-99a0-139479500813
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996709773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.996709773
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.1565865260
Short name T511
Test name
Test status
Simulation time 498304983286 ps
CPU time 1154.12 seconds
Started Jul 21 05:41:42 PM PDT 24
Finished Jul 21 06:00:56 PM PDT 24
Peak memory 201716 kb
Host smart-cc41fb7d-b076-4ce4-9a98-ab0fa0370fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565865260 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.1565865260
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.1694582777
Short name T458
Test name
Test status
Simulation time 486718343409 ps
CPU time 1011.06 seconds
Started Jul 21 05:41:41 PM PDT 24
Finished Jul 21 05:58:33 PM PDT 24
Peak memory 201724 kb
Host smart-564d9d4a-213d-41b3-aa8a-cbe3e955972b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694582777 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interru
pt_fixed.1694582777
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.3824039237
Short name T135
Test name
Test status
Simulation time 162946388240 ps
CPU time 39.26 seconds
Started Jul 21 05:41:35 PM PDT 24
Finished Jul 21 05:42:15 PM PDT 24
Peak memory 201800 kb
Host smart-27e38db4-a748-4c61-a478-7a2977344512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824039237 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.3824039237
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.3224519838
Short name T527
Test name
Test status
Simulation time 487814049571 ps
CPU time 568.83 seconds
Started Jul 21 05:41:37 PM PDT 24
Finished Jul 21 05:51:07 PM PDT 24
Peak memory 201428 kb
Host smart-eb3d4e10-8f0e-4f2a-9c4c-c3d86ff30859
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224519838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fix
ed.3224519838
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.1088563303
Short name T592
Test name
Test status
Simulation time 177726026675 ps
CPU time 104.74 seconds
Started Jul 21 05:41:43 PM PDT 24
Finished Jul 21 05:43:28 PM PDT 24
Peak memory 201752 kb
Host smart-58bcada1-89f9-47a0-a6ee-0a742ecff8b9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088563303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters
_wakeup.1088563303
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.162750213
Short name T557
Test name
Test status
Simulation time 199502555972 ps
CPU time 146.82 seconds
Started Jul 21 05:41:42 PM PDT 24
Finished Jul 21 05:44:09 PM PDT 24
Peak memory 201744 kb
Host smart-b975b999-29ec-4f61-be37-6df548a4555e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162750213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
adc_ctrl_filters_wakeup_fixed.162750213
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.2061589701
Short name T8
Test name
Test status
Simulation time 80374324376 ps
CPU time 297.82 seconds
Started Jul 21 05:41:50 PM PDT 24
Finished Jul 21 05:46:48 PM PDT 24
Peak memory 202132 kb
Host smart-26978b89-53d0-4858-a830-d89e78e66b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061589701 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.2061589701
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.2186231492
Short name T482
Test name
Test status
Simulation time 37583203325 ps
CPU time 22.58 seconds
Started Jul 21 05:41:42 PM PDT 24
Finished Jul 21 05:42:05 PM PDT 24
Peak memory 201656 kb
Host smart-b260596b-218e-4656-87c2-d6a734ef8065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186231492 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.2186231492
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.55403108
Short name T730
Test name
Test status
Simulation time 5181718760 ps
CPU time 6.93 seconds
Started Jul 21 05:41:52 PM PDT 24
Finished Jul 21 05:41:59 PM PDT 24
Peak memory 201592 kb
Host smart-eb3f8909-095a-4e3e-b05d-af9a05f49a29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55403108 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.55403108
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.4188447579
Short name T754
Test name
Test status
Simulation time 5954909585 ps
CPU time 14.53 seconds
Started Jul 21 05:41:37 PM PDT 24
Finished Jul 21 05:41:52 PM PDT 24
Peak memory 201472 kb
Host smart-5fbaab91-fa09-4c1f-9ac1-8761a5f3e440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188447579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.4188447579
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.822251699
Short name T494
Test name
Test status
Simulation time 170871723735 ps
CPU time 110.67 seconds
Started Jul 21 05:41:47 PM PDT 24
Finished Jul 21 05:43:38 PM PDT 24
Peak memory 201688 kb
Host smart-4803748d-ac8d-4e56-9771-b79ea96546d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822251699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all.
822251699
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.2930759848
Short name T17
Test name
Test status
Simulation time 54267504785 ps
CPU time 159.12 seconds
Started Jul 21 05:41:48 PM PDT 24
Finished Jul 21 05:44:27 PM PDT 24
Peak memory 217500 kb
Host smart-1c172a48-a328-4a06-92a9-793c0473d1b9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930759848 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.2930759848
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.2525025391
Short name T401
Test name
Test status
Simulation time 571681835 ps
CPU time 0.72 seconds
Started Jul 21 05:42:11 PM PDT 24
Finished Jul 21 05:42:12 PM PDT 24
Peak memory 201680 kb
Host smart-89d685d4-2dd8-4144-9604-a8376826c3bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525025391 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.2525025391
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.2757378536
Short name T161
Test name
Test status
Simulation time 493448690327 ps
CPU time 301.52 seconds
Started Jul 21 05:41:56 PM PDT 24
Finished Jul 21 05:46:58 PM PDT 24
Peak memory 201692 kb
Host smart-dec1bdb5-0383-4e8d-aa67-cf37637dbeab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757378536 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.2757378536
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.2917150911
Short name T413
Test name
Test status
Simulation time 168627370695 ps
CPU time 103.34 seconds
Started Jul 21 05:41:55 PM PDT 24
Finished Jul 21 05:43:39 PM PDT 24
Peak memory 201716 kb
Host smart-6ea9fb58-d0e9-4481-a8dd-1f517ea87cd2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917150911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interru
pt_fixed.2917150911
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.797891033
Short name T162
Test name
Test status
Simulation time 492501809111 ps
CPU time 149.64 seconds
Started Jul 21 05:41:49 PM PDT 24
Finished Jul 21 05:44:19 PM PDT 24
Peak memory 201748 kb
Host smart-dbcbb644-24e2-47a9-8079-4de94b25b098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797891033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.797891033
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.1571412085
Short name T353
Test name
Test status
Simulation time 163823757770 ps
CPU time 395.73 seconds
Started Jul 21 05:41:48 PM PDT 24
Finished Jul 21 05:48:24 PM PDT 24
Peak memory 201732 kb
Host smart-aa1e75fc-0864-47c6-9e05-45589205fc9d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571412085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fix
ed.1571412085
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.273100950
Short name T268
Test name
Test status
Simulation time 201856998981 ps
CPU time 115.59 seconds
Started Jul 21 05:41:54 PM PDT 24
Finished Jul 21 05:43:50 PM PDT 24
Peak memory 201792 kb
Host smart-73c8e332-b269-4e68-812e-e55e635c8677
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273100950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_
wakeup.273100950
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.1370352851
Short name T795
Test name
Test status
Simulation time 417868363354 ps
CPU time 772.63 seconds
Started Jul 21 05:41:57 PM PDT 24
Finished Jul 21 05:54:50 PM PDT 24
Peak memory 201688 kb
Host smart-84d52087-9d11-48df-97b7-6d6ae7bb1cbd
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370352851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.adc_ctrl_filters_wakeup_fixed.1370352851
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.3199205250
Short name T721
Test name
Test status
Simulation time 114943325057 ps
CPU time 384.4 seconds
Started Jul 21 05:42:00 PM PDT 24
Finished Jul 21 05:48:24 PM PDT 24
Peak memory 202204 kb
Host smart-ac776572-1657-47ec-8266-700b122d616c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199205250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.3199205250
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.4168715951
Short name T529
Test name
Test status
Simulation time 35091657323 ps
CPU time 74.09 seconds
Started Jul 21 05:41:59 PM PDT 24
Finished Jul 21 05:43:14 PM PDT 24
Peak memory 201584 kb
Host smart-f44171a2-89a9-41fa-ad22-ffff2fb86a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168715951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.4168715951
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.4087583901
Short name T561
Test name
Test status
Simulation time 3004314634 ps
CPU time 3.9 seconds
Started Jul 21 05:42:01 PM PDT 24
Finished Jul 21 05:42:05 PM PDT 24
Peak memory 201572 kb
Host smart-cc4045cf-f44b-423a-b03b-af124117dbbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087583901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.4087583901
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.3493542172
Short name T578
Test name
Test status
Simulation time 6011636889 ps
CPU time 4.38 seconds
Started Jul 21 05:41:48 PM PDT 24
Finished Jul 21 05:41:53 PM PDT 24
Peak memory 201588 kb
Host smart-3e3516dc-108f-421d-abea-0e3e1a55474c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493542172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.3493542172
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.3334707579
Short name T38
Test name
Test status
Simulation time 103259323244 ps
CPU time 569.53 seconds
Started Jul 21 05:42:03 PM PDT 24
Finished Jul 21 05:51:33 PM PDT 24
Peak memory 218448 kb
Host smart-ae8d084d-42e2-47d6-b492-16e60f3e8edc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334707579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all
.3334707579
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.1269746656
Short name T493
Test name
Test status
Simulation time 492753671 ps
CPU time 1.1 seconds
Started Jul 21 05:42:21 PM PDT 24
Finished Jul 21 05:42:22 PM PDT 24
Peak memory 201544 kb
Host smart-6bcac000-b266-4988-a2b8-ced6e9d23309
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269746656 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.1269746656
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.1156825384
Short name T626
Test name
Test status
Simulation time 490790549880 ps
CPU time 1173.45 seconds
Started Jul 21 05:42:11 PM PDT 24
Finished Jul 21 06:01:45 PM PDT 24
Peak memory 201884 kb
Host smart-3b2ab5c7-781c-4b0f-b0f1-32d4abd4b192
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156825384 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interru
pt_fixed.1156825384
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.1250816529
Short name T517
Test name
Test status
Simulation time 167389233853 ps
CPU time 185.45 seconds
Started Jul 21 05:42:07 PM PDT 24
Finished Jul 21 05:45:13 PM PDT 24
Peak memory 201732 kb
Host smart-dcf6b034-528a-4bfe-88af-fcad74c23ed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250816529 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.1250816529
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.1633850609
Short name T434
Test name
Test status
Simulation time 493421440178 ps
CPU time 547.19 seconds
Started Jul 21 05:42:07 PM PDT 24
Finished Jul 21 05:51:14 PM PDT 24
Peak memory 201700 kb
Host smart-e0ae52fa-3886-4c19-a606-9319cd12d6cc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633850609 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fix
ed.1633850609
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.3701313545
Short name T253
Test name
Test status
Simulation time 573756220941 ps
CPU time 1367.85 seconds
Started Jul 21 05:42:16 PM PDT 24
Finished Jul 21 06:05:04 PM PDT 24
Peak memory 201808 kb
Host smart-1edda115-3371-4798-877b-99db9b2db157
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701313545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters
_wakeup.3701313545
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.3548422146
Short name T486
Test name
Test status
Simulation time 198208941850 ps
CPU time 139.87 seconds
Started Jul 21 05:42:15 PM PDT 24
Finished Jul 21 05:44:36 PM PDT 24
Peak memory 201724 kb
Host smart-0170971a-9c15-4292-a06e-369185477179
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548422146 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.adc_ctrl_filters_wakeup_fixed.3548422146
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.4230355811
Short name T376
Test name
Test status
Simulation time 67956372739 ps
CPU time 273.11 seconds
Started Jul 21 05:42:15 PM PDT 24
Finished Jul 21 05:46:49 PM PDT 24
Peak memory 202120 kb
Host smart-f639f6a7-56f8-43d8-8d62-94c1fa29d28b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230355811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.4230355811
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.1978043418
Short name T791
Test name
Test status
Simulation time 32971356740 ps
CPU time 16.71 seconds
Started Jul 21 05:42:19 PM PDT 24
Finished Jul 21 05:42:36 PM PDT 24
Peak memory 201544 kb
Host smart-a0321d97-593f-418b-b819-f6e88b7a44d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978043418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.1978043418
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.606056968
Short name T357
Test name
Test status
Simulation time 4827208951 ps
CPU time 1.72 seconds
Started Jul 21 05:42:16 PM PDT 24
Finished Jul 21 05:42:18 PM PDT 24
Peak memory 201524 kb
Host smart-63bbbc29-2bd4-4d84-bd4d-f1f51a9ff8a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606056968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.606056968
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.4163511262
Short name T507
Test name
Test status
Simulation time 5504700200 ps
CPU time 6.26 seconds
Started Jul 21 05:42:08 PM PDT 24
Finished Jul 21 05:42:15 PM PDT 24
Peak memory 201612 kb
Host smart-a02f192a-7e46-4ffe-bca8-cfdeb1352746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163511262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.4163511262
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.2326011019
Short name T331
Test name
Test status
Simulation time 315936477582 ps
CPU time 893.49 seconds
Started Jul 21 05:42:22 PM PDT 24
Finished Jul 21 05:57:16 PM PDT 24
Peak memory 210300 kb
Host smart-4bcce8a7-42f2-4ec3-b957-b667ca93ab25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326011019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all
.2326011019
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.3429552613
Short name T27
Test name
Test status
Simulation time 291471097793 ps
CPU time 391.49 seconds
Started Jul 21 05:42:15 PM PDT 24
Finished Jul 21 05:48:47 PM PDT 24
Peak memory 210512 kb
Host smart-fc781098-27ff-423b-bdf5-e215d0e39f89
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429552613 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.3429552613
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.1729370532
Short name T604
Test name
Test status
Simulation time 500120458 ps
CPU time 1.73 seconds
Started Jul 21 05:40:10 PM PDT 24
Finished Jul 21 05:40:12 PM PDT 24
Peak memory 201560 kb
Host smart-e8ada7b2-1810-4b6f-834b-39cb6d0a78a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729370532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.1729370532
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.4274299485
Short name T274
Test name
Test status
Simulation time 166575653196 ps
CPU time 101.18 seconds
Started Jul 21 05:40:08 PM PDT 24
Finished Jul 21 05:41:50 PM PDT 24
Peak memory 201788 kb
Host smart-36d76524-2356-43e1-b99a-230eac2dc85f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274299485 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gati
ng.4274299485
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.1670687679
Short name T501
Test name
Test status
Simulation time 164636415350 ps
CPU time 100.05 seconds
Started Jul 21 05:40:08 PM PDT 24
Finished Jul 21 05:41:49 PM PDT 24
Peak memory 201728 kb
Host smart-128f5d59-e17f-4afd-9b8c-375e19fbd4f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670687679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.1670687679
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.1788465632
Short name T281
Test name
Test status
Simulation time 166012796960 ps
CPU time 412.15 seconds
Started Jul 21 05:40:11 PM PDT 24
Finished Jul 21 05:47:04 PM PDT 24
Peak memory 201812 kb
Host smart-d08bd364-9320-48be-8430-7d84a62961ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788465632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.1788465632
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.298226605
Short name T193
Test name
Test status
Simulation time 166431211997 ps
CPU time 102.72 seconds
Started Jul 21 05:40:09 PM PDT 24
Finished Jul 21 05:41:52 PM PDT 24
Peak memory 201704 kb
Host smart-943239ef-78d4-4b08-a6a3-b2fbc0ee5506
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=298226605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt
_fixed.298226605
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.3528656525
Short name T586
Test name
Test status
Simulation time 485242471800 ps
CPU time 1087.95 seconds
Started Jul 21 05:40:12 PM PDT 24
Finished Jul 21 05:58:21 PM PDT 24
Peak memory 201716 kb
Host smart-99a7fd57-a3be-4de7-a090-e38c4d82bada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528656525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.3528656525
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.3617209636
Short name T589
Test name
Test status
Simulation time 325749863049 ps
CPU time 399.26 seconds
Started Jul 21 05:40:11 PM PDT 24
Finished Jul 21 05:46:51 PM PDT 24
Peak memory 201784 kb
Host smart-4f2b4126-9f77-41a8-95f9-d8ccf0c1b67a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617209636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixe
d.3617209636
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.4079737164
Short name T231
Test name
Test status
Simulation time 595660102086 ps
CPU time 733.83 seconds
Started Jul 21 05:40:09 PM PDT 24
Finished Jul 21 05:52:24 PM PDT 24
Peak memory 201792 kb
Host smart-64bdc3b4-f97a-4a65-b808-0fda6c283ae1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079737164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_
wakeup.4079737164
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.3369104806
Short name T439
Test name
Test status
Simulation time 201474188259 ps
CPU time 460.47 seconds
Started Jul 21 05:40:12 PM PDT 24
Finished Jul 21 05:47:53 PM PDT 24
Peak memory 201572 kb
Host smart-a4db6f39-7536-4b4e-a2c6-e838db6f2ac9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369104806 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
adc_ctrl_filters_wakeup_fixed.3369104806
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.978343316
Short name T505
Test name
Test status
Simulation time 36230166463 ps
CPU time 7.23 seconds
Started Jul 21 05:40:09 PM PDT 24
Finished Jul 21 05:40:16 PM PDT 24
Peak memory 201496 kb
Host smart-f006cd24-221c-41eb-ad14-1c6690ed30ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978343316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.978343316
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.1859531601
Short name T399
Test name
Test status
Simulation time 3544631406 ps
CPU time 2.61 seconds
Started Jul 21 05:40:13 PM PDT 24
Finished Jul 21 05:40:16 PM PDT 24
Peak memory 201428 kb
Host smart-98150df9-89b9-46ce-a178-01254600d78b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859531601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.1859531601
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.3381921355
Short name T54
Test name
Test status
Simulation time 8708127354 ps
CPU time 5.53 seconds
Started Jul 21 05:40:08 PM PDT 24
Finished Jul 21 05:40:15 PM PDT 24
Peak memory 217268 kb
Host smart-9b5a019a-70f0-4acd-988b-27af55a20df3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381921355 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.3381921355
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.3516929883
Short name T119
Test name
Test status
Simulation time 5712607039 ps
CPU time 3.4 seconds
Started Jul 21 05:40:13 PM PDT 24
Finished Jul 21 05:40:17 PM PDT 24
Peak memory 201588 kb
Host smart-7a5994c7-0942-4d21-8ecb-699055cc8d2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516929883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.3516929883
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.1477540059
Short name T650
Test name
Test status
Simulation time 202647027352 ps
CPU time 833.61 seconds
Started Jul 21 05:40:09 PM PDT 24
Finished Jul 21 05:54:03 PM PDT 24
Peak memory 211340 kb
Host smart-9d23c855-819b-449c-9c90-232ab1dee0a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477540059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.
1477540059
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.2979596225
Short name T576
Test name
Test status
Simulation time 526534461 ps
CPU time 1.78 seconds
Started Jul 21 05:42:23 PM PDT 24
Finished Jul 21 05:42:25 PM PDT 24
Peak memory 201472 kb
Host smart-5f5b5a5e-7f6b-4706-b711-c3f5b1655359
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979596225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.2979596225
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.3956110431
Short name T313
Test name
Test status
Simulation time 163584840992 ps
CPU time 380.29 seconds
Started Jul 21 05:42:23 PM PDT 24
Finished Jul 21 05:48:43 PM PDT 24
Peak memory 201732 kb
Host smart-f5dd1bb2-3845-4e83-8f3e-55ea131195f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956110431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.3956110431
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.1031109484
Short name T326
Test name
Test status
Simulation time 482342067437 ps
CPU time 274.98 seconds
Started Jul 21 05:42:22 PM PDT 24
Finished Jul 21 05:46:57 PM PDT 24
Peak memory 201748 kb
Host smart-3a2981fc-3fd4-4867-834e-2d080668c9d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031109484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.1031109484
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.1348917014
Short name T780
Test name
Test status
Simulation time 166376486790 ps
CPU time 394.44 seconds
Started Jul 21 05:42:23 PM PDT 24
Finished Jul 21 05:48:58 PM PDT 24
Peak memory 201688 kb
Host smart-ac46f215-459e-494a-8790-7fda1ee5a81c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348917014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interru
pt_fixed.1348917014
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.1103525638
Short name T395
Test name
Test status
Simulation time 163248261035 ps
CPU time 361.51 seconds
Started Jul 21 05:42:23 PM PDT 24
Finished Jul 21 05:48:24 PM PDT 24
Peak memory 201736 kb
Host smart-280b75d2-7820-41a7-822a-0abee8838c13
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103525638 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fix
ed.1103525638
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.3839339703
Short name T728
Test name
Test status
Simulation time 405436787180 ps
CPU time 443.94 seconds
Started Jul 21 05:42:22 PM PDT 24
Finished Jul 21 05:49:46 PM PDT 24
Peak memory 201748 kb
Host smart-4999b6ba-b4de-4bb1-bea6-eefa22b0ed63
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839339703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters
_wakeup.3839339703
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.2058653575
Short name T634
Test name
Test status
Simulation time 208543716623 ps
CPU time 411.22 seconds
Started Jul 21 05:42:22 PM PDT 24
Finished Jul 21 05:49:13 PM PDT 24
Peak memory 201732 kb
Host smart-338a7ded-296e-429d-9f43-f7a21d382ecc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058653575 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.adc_ctrl_filters_wakeup_fixed.2058653575
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.145414656
Short name T173
Test name
Test status
Simulation time 92080852847 ps
CPU time 289.64 seconds
Started Jul 21 05:42:23 PM PDT 24
Finished Jul 21 05:47:13 PM PDT 24
Peak memory 202192 kb
Host smart-a44c56db-2b67-4e0b-964a-6c8f72c2687d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145414656 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.145414656
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.2261858747
Short name T547
Test name
Test status
Simulation time 43836705640 ps
CPU time 101.63 seconds
Started Jul 21 05:42:21 PM PDT 24
Finished Jul 21 05:44:03 PM PDT 24
Peak memory 201496 kb
Host smart-a558aa9e-578b-41fd-8035-51ae72e9ddd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261858747 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.2261858747
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.100585397
Short name T404
Test name
Test status
Simulation time 3005172159 ps
CPU time 2.31 seconds
Started Jul 21 05:42:23 PM PDT 24
Finished Jul 21 05:42:26 PM PDT 24
Peak memory 201640 kb
Host smart-e7b82c46-3bee-41c2-9d9d-172576ee8467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100585397 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.100585397
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.1226735406
Short name T783
Test name
Test status
Simulation time 6085752199 ps
CPU time 15.11 seconds
Started Jul 21 05:42:27 PM PDT 24
Finished Jul 21 05:42:42 PM PDT 24
Peak memory 201500 kb
Host smart-4f8fb80f-faa3-4d98-bbac-248bf3f2ca51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226735406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.1226735406
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.3322628142
Short name T591
Test name
Test status
Simulation time 36499941368 ps
CPU time 12.29 seconds
Started Jul 21 05:42:23 PM PDT 24
Finished Jul 21 05:42:36 PM PDT 24
Peak memory 201624 kb
Host smart-96ba503b-e7ec-4365-b23b-81c6c417ba1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322628142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all
.3322628142
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.3365996619
Short name T726
Test name
Test status
Simulation time 403050740 ps
CPU time 0.8 seconds
Started Jul 21 05:42:33 PM PDT 24
Finished Jul 21 05:42:34 PM PDT 24
Peak memory 201436 kb
Host smart-8c41262a-4be2-4d56-b26b-3b79e8d828f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365996619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.3365996619
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.2106828566
Short name T599
Test name
Test status
Simulation time 168125611668 ps
CPU time 81.63 seconds
Started Jul 21 05:42:28 PM PDT 24
Finished Jul 21 05:43:51 PM PDT 24
Peak memory 201748 kb
Host smart-b1f516d1-5437-4df2-ab10-93bd6aa9afc7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106828566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gat
ing.2106828566
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.1382464263
Short name T296
Test name
Test status
Simulation time 180996391824 ps
CPU time 428.15 seconds
Started Jul 21 05:42:30 PM PDT 24
Finished Jul 21 05:49:38 PM PDT 24
Peak memory 201816 kb
Host smart-b594e31d-0750-4b34-bf4f-7d71c0a8975f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382464263 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.1382464263
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.1403383520
Short name T186
Test name
Test status
Simulation time 491085662967 ps
CPU time 700.93 seconds
Started Jul 21 05:42:28 PM PDT 24
Finished Jul 21 05:54:10 PM PDT 24
Peak memory 201732 kb
Host smart-bc4c3895-a850-41c5-853b-9c09114c1e52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403383520 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.1403383520
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.2822560491
Short name T618
Test name
Test status
Simulation time 487895066517 ps
CPU time 1222.66 seconds
Started Jul 21 05:42:29 PM PDT 24
Finished Jul 21 06:02:52 PM PDT 24
Peak memory 201676 kb
Host smart-dfd495e9-e5fa-44f6-8d84-71815988e9d5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822560491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interru
pt_fixed.2822560491
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.1759303017
Short name T686
Test name
Test status
Simulation time 168391103413 ps
CPU time 75.76 seconds
Started Jul 21 05:42:27 PM PDT 24
Finished Jul 21 05:43:44 PM PDT 24
Peak memory 201856 kb
Host smart-5ba64945-697e-4101-ace5-073b684e6fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759303017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.1759303017
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.525643643
Short name T368
Test name
Test status
Simulation time 337377157079 ps
CPU time 816.2 seconds
Started Jul 21 05:42:27 PM PDT 24
Finished Jul 21 05:56:04 PM PDT 24
Peak memory 201660 kb
Host smart-a60aab34-b4c5-42df-99db-61f83b7f0c2d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=525643643 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fixe
d.525643643
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.527073542
Short name T208
Test name
Test status
Simulation time 560526651051 ps
CPU time 1337.42 seconds
Started Jul 21 05:42:30 PM PDT 24
Finished Jul 21 06:04:48 PM PDT 24
Peak memory 201688 kb
Host smart-6e731812-f4cc-4bea-87a3-e852cf04b5eb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527073542 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_
wakeup.527073542
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.1689339271
Short name T375
Test name
Test status
Simulation time 198979260074 ps
CPU time 124.09 seconds
Started Jul 21 05:42:28 PM PDT 24
Finished Jul 21 05:44:33 PM PDT 24
Peak memory 201748 kb
Host smart-616bdfd6-4e0b-429e-93cb-aa76fb022db3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689339271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.adc_ctrl_filters_wakeup_fixed.1689339271
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.2472923796
Short name T37
Test name
Test status
Simulation time 141663259826 ps
CPU time 482.33 seconds
Started Jul 21 05:42:33 PM PDT 24
Finished Jul 21 05:50:36 PM PDT 24
Peak memory 202056 kb
Host smart-aa8073e8-1dab-4db7-98f7-7dec53ef698a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472923796 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.2472923796
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.3675383505
Short name T574
Test name
Test status
Simulation time 28026596945 ps
CPU time 19.92 seconds
Started Jul 21 05:42:32 PM PDT 24
Finished Jul 21 05:42:52 PM PDT 24
Peak memory 201428 kb
Host smart-ef771fa4-1745-40bf-92a2-49ff4e89bddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675383505 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.3675383505
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.3313570076
Short name T559
Test name
Test status
Simulation time 5060320384 ps
CPU time 2.57 seconds
Started Jul 21 05:42:29 PM PDT 24
Finished Jul 21 05:42:32 PM PDT 24
Peak memory 201492 kb
Host smart-751f2b75-71e3-4beb-af92-9fa9c47d5fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313570076 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.3313570076
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.609981178
Short name T732
Test name
Test status
Simulation time 5982615733 ps
CPU time 13.51 seconds
Started Jul 21 05:42:29 PM PDT 24
Finished Jul 21 05:42:43 PM PDT 24
Peak memory 201500 kb
Host smart-d71da57b-2d82-47be-90d2-dbdbbf84ab71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609981178 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.609981178
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.2755058275
Short name T24
Test name
Test status
Simulation time 499303780611 ps
CPU time 809.2 seconds
Started Jul 21 05:42:34 PM PDT 24
Finished Jul 21 05:56:03 PM PDT 24
Peak memory 210204 kb
Host smart-16829af3-7da1-41ad-b085-005011c72a94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755058275 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all
.2755058275
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.2778738717
Short name T28
Test name
Test status
Simulation time 22340586080 ps
CPU time 50.94 seconds
Started Jul 21 05:42:33 PM PDT 24
Finished Jul 21 05:43:25 PM PDT 24
Peak memory 201860 kb
Host smart-2bc55b9b-dbff-4b28-8b1d-9654c89dd41d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778738717 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.2778738717
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.4220119926
Short name T503
Test name
Test status
Simulation time 476566955 ps
CPU time 0.7 seconds
Started Jul 21 05:42:46 PM PDT 24
Finished Jul 21 05:42:48 PM PDT 24
Peak memory 201440 kb
Host smart-dc10037e-d4d7-456c-b70c-5f418da54bed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220119926 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.4220119926
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.844420381
Short name T34
Test name
Test status
Simulation time 332699940472 ps
CPU time 630.89 seconds
Started Jul 21 05:42:41 PM PDT 24
Finished Jul 21 05:53:12 PM PDT 24
Peak memory 201712 kb
Host smart-5e710a7b-8ff6-4ad7-8168-b0934a72b03e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844420381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gati
ng.844420381
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.2116011091
Short name T490
Test name
Test status
Simulation time 329670206434 ps
CPU time 740.13 seconds
Started Jul 21 05:42:40 PM PDT 24
Finished Jul 21 05:55:01 PM PDT 24
Peak memory 201732 kb
Host smart-8f73581d-0ace-467c-b662-8e8c347ff21d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116011091 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.2116011091
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.1998426301
Short name T246
Test name
Test status
Simulation time 318765037466 ps
CPU time 156.95 seconds
Started Jul 21 05:42:40 PM PDT 24
Finished Jul 21 05:45:17 PM PDT 24
Peak memory 201632 kb
Host smart-d668b250-654a-4c60-ad40-5f16244c73a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998426301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.1998426301
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.399525053
Short name T153
Test name
Test status
Simulation time 164271544331 ps
CPU time 96.67 seconds
Started Jul 21 05:42:39 PM PDT 24
Finished Jul 21 05:44:15 PM PDT 24
Peak memory 201768 kb
Host smart-f1dcc0a1-3d38-47f2-96ce-0ca5aea9822f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=399525053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrup
t_fixed.399525053
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.4235013210
Short name T495
Test name
Test status
Simulation time 492407036549 ps
CPU time 608.85 seconds
Started Jul 21 05:42:38 PM PDT 24
Finished Jul 21 05:52:47 PM PDT 24
Peak memory 201692 kb
Host smart-80af745e-ec89-4354-987b-e61f757c9a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235013210 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.4235013210
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.3046486952
Short name T528
Test name
Test status
Simulation time 328236102027 ps
CPU time 177.7 seconds
Started Jul 21 05:42:41 PM PDT 24
Finished Jul 21 05:45:39 PM PDT 24
Peak memory 201700 kb
Host smart-0f4e6a7c-06b4-41c2-a516-737aaf5d864d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046486952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fix
ed.3046486952
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.1176667850
Short name T308
Test name
Test status
Simulation time 178895179648 ps
CPU time 107.59 seconds
Started Jul 21 05:42:41 PM PDT 24
Finished Jul 21 05:44:28 PM PDT 24
Peak memory 201732 kb
Host smart-759126ea-ef19-4ca1-9431-9c11d4f405e0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176667850 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters
_wakeup.1176667850
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.3429082658
Short name T410
Test name
Test status
Simulation time 198206729233 ps
CPU time 225.83 seconds
Started Jul 21 05:42:38 PM PDT 24
Finished Jul 21 05:46:25 PM PDT 24
Peak memory 201640 kb
Host smart-c5bc1c3b-bc71-47ee-9c3d-2d8d5def9608
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429082658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.adc_ctrl_filters_wakeup_fixed.3429082658
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.489094673
Short name T692
Test name
Test status
Simulation time 114393321739 ps
CPU time 458.14 seconds
Started Jul 21 05:42:48 PM PDT 24
Finished Jul 21 05:50:26 PM PDT 24
Peak memory 202156 kb
Host smart-2394bd35-f690-4f31-90e4-653a00272ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489094673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.489094673
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.3624826737
Short name T400
Test name
Test status
Simulation time 34488852363 ps
CPU time 13.2 seconds
Started Jul 21 05:42:38 PM PDT 24
Finished Jul 21 05:42:52 PM PDT 24
Peak memory 201420 kb
Host smart-0353ad8c-593d-460a-9f6f-130331f2a4d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624826737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.3624826737
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.3603649126
Short name T629
Test name
Test status
Simulation time 3438565110 ps
CPU time 8.16 seconds
Started Jul 21 05:42:40 PM PDT 24
Finished Jul 21 05:42:48 PM PDT 24
Peak memory 201584 kb
Host smart-ef39a7cc-b176-49a0-92b0-a283bd42290e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603649126 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.3603649126
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.2592361121
Short name T508
Test name
Test status
Simulation time 5839110768 ps
CPU time 7.4 seconds
Started Jul 21 05:42:32 PM PDT 24
Finished Jul 21 05:42:40 PM PDT 24
Peak memory 201608 kb
Host smart-04c461ca-2d08-49bd-bba9-a73e64b74ecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592361121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.2592361121
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.1968715678
Short name T566
Test name
Test status
Simulation time 242236984576 ps
CPU time 784.19 seconds
Started Jul 21 05:42:46 PM PDT 24
Finished Jul 21 05:55:51 PM PDT 24
Peak memory 210288 kb
Host smart-4f0daef4-328a-4539-99f9-a2e862c285c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968715678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all
.1968715678
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.2295200776
Short name T15
Test name
Test status
Simulation time 33679839971 ps
CPU time 64.28 seconds
Started Jul 21 05:42:48 PM PDT 24
Finished Jul 21 05:43:52 PM PDT 24
Peak memory 210132 kb
Host smart-26e8f7cc-7c27-488d-863b-d13034e878a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295200776 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.2295200776
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.418061211
Short name T652
Test name
Test status
Simulation time 343684693 ps
CPU time 0.83 seconds
Started Jul 21 05:42:55 PM PDT 24
Finished Jul 21 05:42:56 PM PDT 24
Peak memory 201364 kb
Host smart-381a4f80-3999-4568-ae84-31ad2e850d31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418061211 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.418061211
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.3327673417
Short name T309
Test name
Test status
Simulation time 166968432450 ps
CPU time 307.04 seconds
Started Jul 21 05:42:47 PM PDT 24
Finished Jul 21 05:47:54 PM PDT 24
Peak memory 201788 kb
Host smart-95288a5e-c49e-4f83-9a13-6d775e852331
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327673417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gat
ing.3327673417
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.2530504283
Short name T584
Test name
Test status
Simulation time 164545460723 ps
CPU time 386.52 seconds
Started Jul 21 05:42:49 PM PDT 24
Finished Jul 21 05:49:16 PM PDT 24
Peak memory 201724 kb
Host smart-028b9092-3444-4770-95a6-658dc4b4c329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530504283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.2530504283
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.850916077
Short name T707
Test name
Test status
Simulation time 158637691455 ps
CPU time 245.62 seconds
Started Jul 21 05:42:48 PM PDT 24
Finished Jul 21 05:46:54 PM PDT 24
Peak memory 201696 kb
Host smart-c059317e-960d-4657-807c-4fb914caffee
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=850916077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrup
t_fixed.850916077
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.3707912097
Short name T437
Test name
Test status
Simulation time 169806516121 ps
CPU time 79.46 seconds
Started Jul 21 05:42:49 PM PDT 24
Finished Jul 21 05:44:09 PM PDT 24
Peak memory 201676 kb
Host smart-5156e595-6390-4cb6-96f9-9cd5a85bdb99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707912097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.3707912097
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.2912725957
Short name T789
Test name
Test status
Simulation time 484503716438 ps
CPU time 277.1 seconds
Started Jul 21 05:42:49 PM PDT 24
Finished Jul 21 05:47:26 PM PDT 24
Peak memory 201676 kb
Host smart-6ec7a835-1e5a-4ebc-8ddc-700f7d8e91c0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912725957 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fix
ed.2912725957
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.2061712093
Short name T646
Test name
Test status
Simulation time 395099014199 ps
CPU time 244.68 seconds
Started Jul 21 05:42:49 PM PDT 24
Finished Jul 21 05:46:54 PM PDT 24
Peak memory 201752 kb
Host smart-9a2f4a1d-ea1e-47de-9b68-1794b5ff0ec3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061712093 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters
_wakeup.2061712093
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.611601509
Short name T777
Test name
Test status
Simulation time 405577782434 ps
CPU time 238.06 seconds
Started Jul 21 05:42:46 PM PDT 24
Finished Jul 21 05:46:45 PM PDT 24
Peak memory 201720 kb
Host smart-61f043a0-6da4-4e6b-ae19-cba49da18db5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611601509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
adc_ctrl_filters_wakeup_fixed.611601509
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.2849805722
Short name T377
Test name
Test status
Simulation time 135957410212 ps
CPU time 576.24 seconds
Started Jul 21 05:42:52 PM PDT 24
Finished Jul 21 05:52:29 PM PDT 24
Peak memory 202156 kb
Host smart-d1e3aa46-4e47-44a6-8d2b-24f7f9afeb44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849805722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.2849805722
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.160722408
Short name T612
Test name
Test status
Simulation time 32732922340 ps
CPU time 75.55 seconds
Started Jul 21 05:42:56 PM PDT 24
Finished Jul 21 05:44:11 PM PDT 24
Peak memory 201516 kb
Host smart-6fb0ffe3-6309-450c-8efd-8058a872899b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160722408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.160722408
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.2231723948
Short name T459
Test name
Test status
Simulation time 4393911128 ps
CPU time 6.33 seconds
Started Jul 21 05:42:53 PM PDT 24
Finished Jul 21 05:43:00 PM PDT 24
Peak memory 201492 kb
Host smart-010b422a-fe41-4118-88d4-b940026ece3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231723948 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.2231723948
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.442041496
Short name T748
Test name
Test status
Simulation time 5885574667 ps
CPU time 15.47 seconds
Started Jul 21 05:42:46 PM PDT 24
Finished Jul 21 05:43:02 PM PDT 24
Peak memory 201600 kb
Host smart-9b4eabdf-0c14-463e-b64f-2c2f83bfcdeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442041496 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.442041496
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.1452785010
Short name T603
Test name
Test status
Simulation time 312806838364 ps
CPU time 251.74 seconds
Started Jul 21 05:42:53 PM PDT 24
Finished Jul 21 05:47:05 PM PDT 24
Peak memory 210468 kb
Host smart-91356b6e-3fbf-41c6-97e3-3cace412f21f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452785010 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.1452785010
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.4027109034
Short name T784
Test name
Test status
Simulation time 552952716 ps
CPU time 0.84 seconds
Started Jul 21 05:43:07 PM PDT 24
Finished Jul 21 05:43:09 PM PDT 24
Peak memory 201480 kb
Host smart-7151ea42-e745-4c6e-9f0e-9ffa683bbad2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027109034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.4027109034
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.1070753582
Short name T75
Test name
Test status
Simulation time 326935669997 ps
CPU time 816.21 seconds
Started Jul 21 05:42:59 PM PDT 24
Finished Jul 21 05:56:36 PM PDT 24
Peak memory 201736 kb
Host smart-54ee29f6-9fa3-4aeb-b98b-c689669352ba
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070753582 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gat
ing.1070753582
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.2044695416
Short name T693
Test name
Test status
Simulation time 491427719458 ps
CPU time 136.41 seconds
Started Jul 21 05:42:59 PM PDT 24
Finished Jul 21 05:45:16 PM PDT 24
Peak memory 201540 kb
Host smart-c28086c3-e6b0-4ff8-bb6f-bd03e2a9a9b0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044695416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interru
pt_fixed.2044695416
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.2938823300
Short name T190
Test name
Test status
Simulation time 165195125722 ps
CPU time 56.71 seconds
Started Jul 21 05:42:53 PM PDT 24
Finished Jul 21 05:43:50 PM PDT 24
Peak memory 201732 kb
Host smart-4aa16da6-0d91-46a8-b867-0304e98c68bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938823300 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.2938823300
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.2410201465
Short name T349
Test name
Test status
Simulation time 487559233180 ps
CPU time 1205.27 seconds
Started Jul 21 05:42:52 PM PDT 24
Finished Jul 21 06:02:57 PM PDT 24
Peak memory 201672 kb
Host smart-3c248987-3480-469f-86f4-ee5892057aba
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410201465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fix
ed.2410201465
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.3273450244
Short name T560
Test name
Test status
Simulation time 450891581064 ps
CPU time 1023.02 seconds
Started Jul 21 05:42:59 PM PDT 24
Finished Jul 21 06:00:03 PM PDT 24
Peak memory 201840 kb
Host smart-2e24b7b7-84d1-44db-a14b-f35c27931725
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273450244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters
_wakeup.3273450244
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.2043494518
Short name T365
Test name
Test status
Simulation time 198405976282 ps
CPU time 122.14 seconds
Started Jul 21 05:43:00 PM PDT 24
Finished Jul 21 05:45:03 PM PDT 24
Peak memory 201716 kb
Host smart-5a0d4ee7-69f4-47e7-8f98-7e131d5ab00d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043494518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.adc_ctrl_filters_wakeup_fixed.2043494518
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.997436531
Short name T40
Test name
Test status
Simulation time 108083920534 ps
CPU time 307.83 seconds
Started Jul 21 05:43:00 PM PDT 24
Finished Jul 21 05:48:08 PM PDT 24
Peak memory 202096 kb
Host smart-ddd79ffe-9b66-4fb4-bddf-b762f6d9f789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997436531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.997436531
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.3854876689
Short name T570
Test name
Test status
Simulation time 47514103298 ps
CPU time 111.01 seconds
Started Jul 21 05:42:59 PM PDT 24
Finished Jul 21 05:44:50 PM PDT 24
Peak memory 201532 kb
Host smart-bd12f26d-99c6-4d36-ac15-f3f5f0d68e13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854876689 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.3854876689
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.3611349659
Short name T369
Test name
Test status
Simulation time 3967661935 ps
CPU time 1.61 seconds
Started Jul 21 05:43:03 PM PDT 24
Finished Jul 21 05:43:05 PM PDT 24
Peak memory 201576 kb
Host smart-0dd651b9-226f-4a4a-bf87-29568f756510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611349659 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.3611349659
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.2167834009
Short name T384
Test name
Test status
Simulation time 5755791313 ps
CPU time 4.13 seconds
Started Jul 21 05:42:53 PM PDT 24
Finished Jul 21 05:42:57 PM PDT 24
Peak memory 201616 kb
Host smart-c11d68ac-6650-4b87-8401-91d712196c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167834009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.2167834009
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.2215348986
Short name T764
Test name
Test status
Simulation time 133767734820 ps
CPU time 435.62 seconds
Started Jul 21 05:43:06 PM PDT 24
Finished Jul 21 05:50:22 PM PDT 24
Peak memory 202108 kb
Host smart-ac099c7d-a0ba-418d-9674-434615c2b0a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215348986 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all
.2215348986
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.2863961190
Short name T350
Test name
Test status
Simulation time 501055733 ps
CPU time 0.84 seconds
Started Jul 21 05:43:13 PM PDT 24
Finished Jul 21 05:43:14 PM PDT 24
Peak memory 201532 kb
Host smart-d974cf5f-97a8-4cb7-ad86-166b6a00d770
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863961190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.2863961190
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.2200277008
Short name T305
Test name
Test status
Simulation time 164551551645 ps
CPU time 383.35 seconds
Started Jul 21 05:43:06 PM PDT 24
Finished Jul 21 05:49:30 PM PDT 24
Peak memory 201732 kb
Host smart-70620a33-9159-4e21-9286-d81817e01371
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200277008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gat
ing.2200277008
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.813940410
Short name T224
Test name
Test status
Simulation time 339772463419 ps
CPU time 371.56 seconds
Started Jul 21 05:43:07 PM PDT 24
Finished Jul 21 05:49:19 PM PDT 24
Peak memory 201744 kb
Host smart-1a0618f4-63ac-483d-a803-ab9b3cd10d89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813940410 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.813940410
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.1644806185
Short name T238
Test name
Test status
Simulation time 505697362339 ps
CPU time 1104.97 seconds
Started Jul 21 05:43:08 PM PDT 24
Finished Jul 21 06:01:33 PM PDT 24
Peak memory 201780 kb
Host smart-c0c9cd18-5cd3-4561-8ac3-ecaa219d9a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644806185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.1644806185
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.3874244615
Short name T481
Test name
Test status
Simulation time 324736166967 ps
CPU time 721.19 seconds
Started Jul 21 05:43:08 PM PDT 24
Finished Jul 21 05:55:10 PM PDT 24
Peak memory 201712 kb
Host smart-cdc0c2ee-7bda-4366-8bf8-abb28a7160e1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874244615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interru
pt_fixed.3874244615
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.1680411450
Short name T614
Test name
Test status
Simulation time 323706666305 ps
CPU time 773.91 seconds
Started Jul 21 05:43:07 PM PDT 24
Finished Jul 21 05:56:01 PM PDT 24
Peak memory 201636 kb
Host smart-172db373-164c-4ffe-98e7-1753d6cef920
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680411450 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fix
ed.1680411450
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.2602497802
Short name T302
Test name
Test status
Simulation time 365263180960 ps
CPU time 898.22 seconds
Started Jul 21 05:43:08 PM PDT 24
Finished Jul 21 05:58:06 PM PDT 24
Peak memory 201792 kb
Host smart-2f3043cb-44f7-48e1-bce5-0b656b6389fd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602497802 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters
_wakeup.2602497802
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.3390515223
Short name T352
Test name
Test status
Simulation time 215934692220 ps
CPU time 231.56 seconds
Started Jul 21 05:43:06 PM PDT 24
Finished Jul 21 05:46:57 PM PDT 24
Peak memory 201652 kb
Host smart-d6ad677b-2d03-446a-93ce-447be65f0a81
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390515223 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.adc_ctrl_filters_wakeup_fixed.3390515223
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.2106018616
Short name T761
Test name
Test status
Simulation time 92041937937 ps
CPU time 391.92 seconds
Started Jul 21 05:43:13 PM PDT 24
Finished Jul 21 05:49:45 PM PDT 24
Peak memory 202096 kb
Host smart-5951e0dc-84b3-41a7-83d9-56dda66108e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106018616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.2106018616
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.1375261865
Short name T84
Test name
Test status
Simulation time 24759419698 ps
CPU time 14.38 seconds
Started Jul 21 05:43:14 PM PDT 24
Finished Jul 21 05:43:29 PM PDT 24
Peak memory 201572 kb
Host smart-2c8be67b-f4d6-4af0-8271-cd56bd4ccf0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375261865 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.1375261865
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.2089007044
Short name T74
Test name
Test status
Simulation time 3849486277 ps
CPU time 2.4 seconds
Started Jul 21 05:43:09 PM PDT 24
Finished Jul 21 05:43:12 PM PDT 24
Peak memory 201600 kb
Host smart-71898272-bdd3-40aa-95ba-2f73a464d493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089007044 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.2089007044
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.4102453806
Short name T539
Test name
Test status
Simulation time 5865405562 ps
CPU time 14.22 seconds
Started Jul 21 05:43:06 PM PDT 24
Finished Jul 21 05:43:21 PM PDT 24
Peak memory 201620 kb
Host smart-98e87a29-2012-40bb-b476-c587bc5cddb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102453806 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.4102453806
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.4058982831
Short name T181
Test name
Test status
Simulation time 601615112619 ps
CPU time 1789.88 seconds
Started Jul 21 05:43:12 PM PDT 24
Finished Jul 21 06:13:02 PM PDT 24
Peak memory 212724 kb
Host smart-e7d68378-8232-4367-939e-d69dadbad6d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058982831 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all
.4058982831
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.2520119626
Short name T520
Test name
Test status
Simulation time 233594857464 ps
CPU time 154.22 seconds
Started Jul 21 05:43:11 PM PDT 24
Finished Jul 21 05:45:46 PM PDT 24
Peak memory 209980 kb
Host smart-eabf57d0-2850-47db-a127-bdb6143cf065
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520119626 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.2520119626
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.4006664449
Short name T535
Test name
Test status
Simulation time 368083375 ps
CPU time 0.97 seconds
Started Jul 21 05:43:19 PM PDT 24
Finished Jul 21 05:43:20 PM PDT 24
Peak memory 201436 kb
Host smart-69976c42-c946-4a6f-a19f-45feedf8cb2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006664449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.4006664449
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.1297341319
Short name T204
Test name
Test status
Simulation time 528041229255 ps
CPU time 255.41 seconds
Started Jul 21 05:43:19 PM PDT 24
Finished Jul 21 05:47:35 PM PDT 24
Peak memory 201676 kb
Host smart-157306c0-9565-496f-8c5b-8760182e4c03
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297341319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gat
ing.1297341319
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.633554777
Short name T644
Test name
Test status
Simulation time 359281466002 ps
CPU time 227.86 seconds
Started Jul 21 05:43:22 PM PDT 24
Finished Jul 21 05:47:10 PM PDT 24
Peak memory 201816 kb
Host smart-ca9040aa-2527-444f-8eb2-af2fe2972394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633554777 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.633554777
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.3522386442
Short name T656
Test name
Test status
Simulation time 332702913325 ps
CPU time 717.04 seconds
Started Jul 21 05:43:13 PM PDT 24
Finished Jul 21 05:55:10 PM PDT 24
Peak memory 201732 kb
Host smart-e35f0811-cd2c-4581-be0b-a49ef492f33d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522386442 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.3522386442
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.836813307
Short name T771
Test name
Test status
Simulation time 328971009977 ps
CPU time 49.89 seconds
Started Jul 21 05:43:20 PM PDT 24
Finished Jul 21 05:44:10 PM PDT 24
Peak memory 201592 kb
Host smart-e6c058d5-1785-44ad-a324-2cfcc37d3e86
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=836813307 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrup
t_fixed.836813307
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.716504739
Short name T409
Test name
Test status
Simulation time 485437129978 ps
CPU time 1064.78 seconds
Started Jul 21 05:43:12 PM PDT 24
Finished Jul 21 06:00:57 PM PDT 24
Peak memory 201752 kb
Host smart-e931b2c3-5bfa-4f8a-aa51-684ef9a3442e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716504739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.716504739
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.4092691476
Short name T654
Test name
Test status
Simulation time 494377657122 ps
CPU time 574.63 seconds
Started Jul 21 05:43:12 PM PDT 24
Finished Jul 21 05:52:47 PM PDT 24
Peak memory 201672 kb
Host smart-5cba0c8d-c68d-45b4-8c05-a0e3486fb720
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092691476 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fix
ed.4092691476
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.3925402062
Short name T466
Test name
Test status
Simulation time 274596552521 ps
CPU time 152.73 seconds
Started Jul 21 05:43:18 PM PDT 24
Finished Jul 21 05:45:51 PM PDT 24
Peak memory 201744 kb
Host smart-690c88ce-a671-4333-a55b-189ff94ef52d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925402062 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters
_wakeup.3925402062
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.2380425754
Short name T715
Test name
Test status
Simulation time 604065543342 ps
CPU time 1409.94 seconds
Started Jul 21 05:43:19 PM PDT 24
Finished Jul 21 06:06:50 PM PDT 24
Peak memory 201728 kb
Host smart-8be8ffca-14d2-464a-8b79-8a24e916020a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380425754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.adc_ctrl_filters_wakeup_fixed.2380425754
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.2378201341
Short name T172
Test name
Test status
Simulation time 65759903197 ps
CPU time 280.4 seconds
Started Jul 21 05:43:22 PM PDT 24
Finished Jul 21 05:48:02 PM PDT 24
Peak memory 202116 kb
Host smart-ab75707a-f96f-4ca8-b63d-c383c1cbfe80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378201341 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.2378201341
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.2190914414
Short name T498
Test name
Test status
Simulation time 44777590812 ps
CPU time 52.35 seconds
Started Jul 21 05:43:19 PM PDT 24
Finished Jul 21 05:44:11 PM PDT 24
Peak memory 201596 kb
Host smart-44ef819f-69e0-4dd4-b818-7dea0947e5d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190914414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.2190914414
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.1078727702
Short name T797
Test name
Test status
Simulation time 2760964272 ps
CPU time 6.47 seconds
Started Jul 21 05:43:20 PM PDT 24
Finished Jul 21 05:43:27 PM PDT 24
Peak memory 201540 kb
Host smart-aab11968-e64e-4499-8379-6bde973e292e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078727702 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.1078727702
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.4063659214
Short name T419
Test name
Test status
Simulation time 5764067037 ps
CPU time 4.42 seconds
Started Jul 21 05:43:11 PM PDT 24
Finished Jul 21 05:43:16 PM PDT 24
Peak memory 201488 kb
Host smart-3b677b49-100d-4f8b-af2a-156482e00db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063659214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.4063659214
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.2052764769
Short name T390
Test name
Test status
Simulation time 165846531512 ps
CPU time 169.79 seconds
Started Jul 21 05:43:18 PM PDT 24
Finished Jul 21 05:46:08 PM PDT 24
Peak memory 201716 kb
Host smart-c0adac22-c397-4b7d-91c3-3327f72b4efc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052764769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all
.2052764769
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.3662858729
Short name T616
Test name
Test status
Simulation time 85630927130 ps
CPU time 149.32 seconds
Started Jul 21 05:43:20 PM PDT 24
Finished Jul 21 05:45:50 PM PDT 24
Peak memory 210008 kb
Host smart-06cf8a51-0a93-4eed-a5c9-637aa79d5f70
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662858729 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.3662858729
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.2163105804
Short name T536
Test name
Test status
Simulation time 479344639 ps
CPU time 0.69 seconds
Started Jul 21 05:43:36 PM PDT 24
Finished Jul 21 05:43:37 PM PDT 24
Peak memory 201552 kb
Host smart-ba82341f-a9af-4717-bd72-c4545872d64c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163105804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.2163105804
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.2509162538
Short name T677
Test name
Test status
Simulation time 604627211640 ps
CPU time 1232.25 seconds
Started Jul 21 05:43:33 PM PDT 24
Finished Jul 21 06:04:06 PM PDT 24
Peak memory 201620 kb
Host smart-2ea95224-0596-4d5e-aa42-6377280706fe
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509162538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gat
ing.2509162538
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.572185659
Short name T244
Test name
Test status
Simulation time 164160302203 ps
CPU time 373.45 seconds
Started Jul 21 05:43:32 PM PDT 24
Finished Jul 21 05:49:46 PM PDT 24
Peak memory 201568 kb
Host smart-b3b2dc12-e840-4fbf-ac8b-6de6ca2642be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572185659 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.572185659
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.176166544
Short name T596
Test name
Test status
Simulation time 163911737036 ps
CPU time 388.25 seconds
Started Jul 21 05:43:24 PM PDT 24
Finished Jul 21 05:49:52 PM PDT 24
Peak memory 201624 kb
Host smart-7d3a1d37-6175-4e08-bc6d-fc75e22d1c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176166544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.176166544
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.279356311
Short name T499
Test name
Test status
Simulation time 493419136639 ps
CPU time 897.82 seconds
Started Jul 21 05:43:25 PM PDT 24
Finished Jul 21 05:58:23 PM PDT 24
Peak memory 201604 kb
Host smart-d82473ce-2513-4da1-81ec-b134012466cc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=279356311 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrup
t_fixed.279356311
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.4004321377
Short name T199
Test name
Test status
Simulation time 331731864949 ps
CPU time 394.09 seconds
Started Jul 21 05:43:24 PM PDT 24
Finished Jul 21 05:49:58 PM PDT 24
Peak memory 201744 kb
Host smart-e811c9f5-19d4-42c5-b19c-08f2c0be3fce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004321377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.4004321377
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.3290192189
Short name T387
Test name
Test status
Simulation time 334151394341 ps
CPU time 684.82 seconds
Started Jul 21 05:43:24 PM PDT 24
Finished Jul 21 05:54:49 PM PDT 24
Peak memory 201624 kb
Host smart-1ab2fdd2-1e4b-48f5-beae-3bb3ef67127b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290192189 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fix
ed.3290192189
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.1119617516
Short name T275
Test name
Test status
Simulation time 374382322895 ps
CPU time 451.89 seconds
Started Jul 21 05:43:25 PM PDT 24
Finished Jul 21 05:50:57 PM PDT 24
Peak memory 201772 kb
Host smart-b070f6a8-cba3-4f74-841a-ddb42d3143c4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119617516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters
_wakeup.1119617516
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.3642645245
Short name T463
Test name
Test status
Simulation time 402838731546 ps
CPU time 244.34 seconds
Started Jul 21 05:43:32 PM PDT 24
Finished Jul 21 05:47:36 PM PDT 24
Peak memory 201748 kb
Host smart-1192e61c-b30a-4016-97b6-09b2d48e4acb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642645245 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.adc_ctrl_filters_wakeup_fixed.3642645245
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.4089378581
Short name T678
Test name
Test status
Simulation time 114689976342 ps
CPU time 627.29 seconds
Started Jul 21 05:43:38 PM PDT 24
Finished Jul 21 05:54:05 PM PDT 24
Peak memory 201992 kb
Host smart-d77ae9c6-9cdb-486e-b6d9-f7a3accc2ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089378581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.4089378581
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.2262616506
Short name T698
Test name
Test status
Simulation time 36031867187 ps
CPU time 40.39 seconds
Started Jul 21 05:43:36 PM PDT 24
Finished Jul 21 05:44:17 PM PDT 24
Peak memory 201596 kb
Host smart-b4b9a1fc-fa21-4077-97b5-c64694b98655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262616506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.2262616506
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.1620456354
Short name T120
Test name
Test status
Simulation time 4742026950 ps
CPU time 3.63 seconds
Started Jul 21 05:43:33 PM PDT 24
Finished Jul 21 05:43:37 PM PDT 24
Peak memory 201604 kb
Host smart-a9aeedf9-0295-4ba9-8546-c7c3d3a435ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620456354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.1620456354
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.3567218434
Short name T757
Test name
Test status
Simulation time 5731480587 ps
CPU time 13.46 seconds
Started Jul 21 05:43:21 PM PDT 24
Finished Jul 21 05:43:35 PM PDT 24
Peak memory 201648 kb
Host smart-8f4044c9-75b9-47ac-aed3-93982094efc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567218434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.3567218434
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.1093750889
Short name T300
Test name
Test status
Simulation time 500479392056 ps
CPU time 1155.33 seconds
Started Jul 21 05:43:38 PM PDT 24
Finished Jul 21 06:02:53 PM PDT 24
Peak memory 201620 kb
Host smart-ca8e46b9-839c-4e56-9017-07ed28cd3881
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093750889 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all
.1093750889
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.2424103387
Short name T258
Test name
Test status
Simulation time 150973352911 ps
CPU time 431.28 seconds
Started Jul 21 05:43:41 PM PDT 24
Finished Jul 21 05:50:52 PM PDT 24
Peak memory 218512 kb
Host smart-1361e542-32af-4193-b2f9-5445e33e1f33
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424103387 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.2424103387
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.266648790
Short name T87
Test name
Test status
Simulation time 286893677 ps
CPU time 1.23 seconds
Started Jul 21 05:44:03 PM PDT 24
Finished Jul 21 05:44:04 PM PDT 24
Peak memory 201448 kb
Host smart-ee2125bf-ffe1-417d-888c-30690cc2f0a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266648790 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.266648790
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.1417042416
Short name T215
Test name
Test status
Simulation time 334738009180 ps
CPU time 459.42 seconds
Started Jul 21 05:43:51 PM PDT 24
Finished Jul 21 05:51:30 PM PDT 24
Peak memory 201740 kb
Host smart-5c7941ed-bb3f-45b5-b28c-543117eafc67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417042416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.1417042416
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.493541864
Short name T588
Test name
Test status
Simulation time 490751438454 ps
CPU time 545.33 seconds
Started Jul 21 05:43:45 PM PDT 24
Finished Jul 21 05:52:51 PM PDT 24
Peak memory 201728 kb
Host smart-604b066e-7ea8-4b02-9c63-83061a797ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493541864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.493541864
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.1098934119
Short name T785
Test name
Test status
Simulation time 159729372797 ps
CPU time 387.71 seconds
Started Jul 21 05:43:49 PM PDT 24
Finished Jul 21 05:50:17 PM PDT 24
Peak memory 201716 kb
Host smart-c4871e74-0011-4b94-899c-781974414e52
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098934119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interru
pt_fixed.1098934119
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.4097834724
Short name T301
Test name
Test status
Simulation time 488622605859 ps
CPU time 284.5 seconds
Started Jul 21 05:43:43 PM PDT 24
Finished Jul 21 05:48:27 PM PDT 24
Peak memory 201720 kb
Host smart-7c5320bb-52d9-4dff-b76a-aaa0fe71c8b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097834724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.4097834724
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.1323981597
Short name T436
Test name
Test status
Simulation time 494318708612 ps
CPU time 1165.05 seconds
Started Jul 21 05:43:44 PM PDT 24
Finished Jul 21 06:03:10 PM PDT 24
Peak memory 201724 kb
Host smart-06d2e460-c6cd-4cbc-ba99-b1ca7c6445ff
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323981597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fix
ed.1323981597
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.978362572
Short name T276
Test name
Test status
Simulation time 459571263844 ps
CPU time 997.98 seconds
Started Jul 21 05:43:48 PM PDT 24
Finished Jul 21 06:00:27 PM PDT 24
Peak memory 201684 kb
Host smart-23b44e61-954a-46f0-9e30-f29352085495
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978362572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_
wakeup.978362572
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.2016525792
Short name T513
Test name
Test status
Simulation time 623847798018 ps
CPU time 355.1 seconds
Started Jul 21 05:43:49 PM PDT 24
Finished Jul 21 05:49:44 PM PDT 24
Peak memory 201716 kb
Host smart-9bb48dc3-f119-42f5-bc83-385142c9a507
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016525792 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.adc_ctrl_filters_wakeup_fixed.2016525792
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.1134664413
Short name T433
Test name
Test status
Simulation time 114091674905 ps
CPU time 494.15 seconds
Started Jul 21 05:43:58 PM PDT 24
Finished Jul 21 05:52:12 PM PDT 24
Peak memory 202080 kb
Host smart-630e0c73-c33f-4341-86ab-4637cc3734e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134664413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.1134664413
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.680455481
Short name T396
Test name
Test status
Simulation time 23106719395 ps
CPU time 35.61 seconds
Started Jul 21 05:43:56 PM PDT 24
Finished Jul 21 05:44:32 PM PDT 24
Peak memory 201588 kb
Host smart-7eab79b6-25e6-4a7d-af3a-83af7f294576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680455481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.680455481
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.514343881
Short name T461
Test name
Test status
Simulation time 2987644362 ps
CPU time 7.71 seconds
Started Jul 21 05:43:56 PM PDT 24
Finished Jul 21 05:44:04 PM PDT 24
Peak memory 201620 kb
Host smart-57f78760-e225-4292-a461-24c68f1d4e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514343881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.514343881
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.1558962906
Short name T573
Test name
Test status
Simulation time 5493258141 ps
CPU time 8.07 seconds
Started Jul 21 05:43:43 PM PDT 24
Finished Jul 21 05:43:51 PM PDT 24
Peak memory 201508 kb
Host smart-98e748e0-0992-46d7-8418-41eb6e77b464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558962906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.1558962906
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.4265545319
Short name T315
Test name
Test status
Simulation time 526774125856 ps
CPU time 455.55 seconds
Started Jul 21 05:43:55 PM PDT 24
Finished Jul 21 05:51:31 PM PDT 24
Peak memory 201788 kb
Host smart-d684c550-2340-468f-b69c-c478d99c9fb1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265545319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all
.4265545319
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.3432681590
Short name T582
Test name
Test status
Simulation time 408113861 ps
CPU time 1.02 seconds
Started Jul 21 05:44:16 PM PDT 24
Finished Jul 21 05:44:17 PM PDT 24
Peak memory 201364 kb
Host smart-e82b55a8-4fbf-42fb-96d3-8bbb9c030e58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432681590 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.3432681590
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.695770233
Short name T610
Test name
Test status
Simulation time 169279558393 ps
CPU time 54.18 seconds
Started Jul 21 05:44:09 PM PDT 24
Finished Jul 21 05:45:04 PM PDT 24
Peak memory 201596 kb
Host smart-c2a01a06-c5a0-4219-89dd-564560b94ee8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695770233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gati
ng.695770233
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.1852361636
Short name T185
Test name
Test status
Simulation time 171526169406 ps
CPU time 148.43 seconds
Started Jul 21 05:44:06 PM PDT 24
Finished Jul 21 05:46:35 PM PDT 24
Peak memory 201560 kb
Host smart-9e25c511-b57b-470e-899b-b1c360a9b980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852361636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.1852361636
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.756653480
Short name T689
Test name
Test status
Simulation time 164347691734 ps
CPU time 375.54 seconds
Started Jul 21 05:44:02 PM PDT 24
Finished Jul 21 05:50:18 PM PDT 24
Peak memory 201572 kb
Host smart-758d5b7f-fd81-45b6-a961-3a897f479f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756653480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.756653480
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.937731683
Short name T633
Test name
Test status
Simulation time 493571909185 ps
CPU time 300.72 seconds
Started Jul 21 05:44:01 PM PDT 24
Finished Jul 21 05:49:02 PM PDT 24
Peak memory 201620 kb
Host smart-95fc5b41-25e6-4adb-880c-dc4e2fd7e056
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=937731683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrup
t_fixed.937731683
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.2212983839
Short name T729
Test name
Test status
Simulation time 164847529510 ps
CPU time 38.03 seconds
Started Jul 21 05:44:03 PM PDT 24
Finished Jul 21 05:44:41 PM PDT 24
Peak memory 201800 kb
Host smart-a394f8f2-c180-4367-9b32-aae3428e9fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212983839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.2212983839
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.1185352569
Short name T445
Test name
Test status
Simulation time 492154910872 ps
CPU time 490.56 seconds
Started Jul 21 05:44:01 PM PDT 24
Finished Jul 21 05:52:12 PM PDT 24
Peak memory 201720 kb
Host smart-8d3a4dab-f6e9-4ff2-97c2-fa07ec2b786d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185352569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fix
ed.1185352569
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.3591976333
Short name T632
Test name
Test status
Simulation time 536132530154 ps
CPU time 841.86 seconds
Started Jul 21 05:44:02 PM PDT 24
Finished Jul 21 05:58:04 PM PDT 24
Peak memory 201808 kb
Host smart-340b3d8e-37ac-44fa-b9ad-a5fd67426a09
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591976333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters
_wakeup.3591976333
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.3505433514
Short name T489
Test name
Test status
Simulation time 390423941332 ps
CPU time 216.89 seconds
Started Jul 21 05:44:02 PM PDT 24
Finished Jul 21 05:47:39 PM PDT 24
Peak memory 201628 kb
Host smart-3d27df04-111b-42fd-a7f5-11f302c45a88
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505433514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.adc_ctrl_filters_wakeup_fixed.3505433514
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.4293507478
Short name T177
Test name
Test status
Simulation time 96948313924 ps
CPU time 403.72 seconds
Started Jul 21 05:44:08 PM PDT 24
Finished Jul 21 05:50:52 PM PDT 24
Peak memory 202140 kb
Host smart-be138c70-cccf-46e4-b34f-125b5e68d9d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293507478 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.4293507478
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.3829711529
Short name T422
Test name
Test status
Simulation time 22096961879 ps
CPU time 13.83 seconds
Started Jul 21 05:44:10 PM PDT 24
Finished Jul 21 05:44:24 PM PDT 24
Peak memory 201464 kb
Host smart-9e700130-98ed-4b1e-a862-027e250bcb0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829711529 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.3829711529
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.754912193
Short name T477
Test name
Test status
Simulation time 3770775875 ps
CPU time 4.09 seconds
Started Jul 21 05:44:08 PM PDT 24
Finished Jul 21 05:44:12 PM PDT 24
Peak memory 201592 kb
Host smart-54275466-f1cc-496b-a0cc-c7c1855acc77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754912193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.754912193
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.1463574651
Short name T672
Test name
Test status
Simulation time 5927135450 ps
CPU time 4.74 seconds
Started Jul 21 05:44:02 PM PDT 24
Finished Jul 21 05:44:07 PM PDT 24
Peak memory 201500 kb
Host smart-ffb981f6-74c7-4ca9-9045-05480d1b50d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463574651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.1463574651
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.2333276229
Short name T251
Test name
Test status
Simulation time 515291168864 ps
CPU time 100.59 seconds
Started Jul 21 05:44:15 PM PDT 24
Finished Jul 21 05:45:56 PM PDT 24
Peak memory 201792 kb
Host smart-01be452e-d603-451e-a113-35730570067c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333276229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all
.2333276229
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.42295465
Short name T538
Test name
Test status
Simulation time 368997323 ps
CPU time 1.47 seconds
Started Jul 21 05:40:14 PM PDT 24
Finished Jul 21 05:40:16 PM PDT 24
Peak memory 201556 kb
Host smart-36b96472-1992-4d69-be25-461bc67f01e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42295465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.42295465
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.1622881042
Short name T228
Test name
Test status
Simulation time 324233362003 ps
CPU time 352.27 seconds
Started Jul 21 05:40:10 PM PDT 24
Finished Jul 21 05:46:03 PM PDT 24
Peak memory 201792 kb
Host smart-849cc691-b034-4739-8761-76f18d98f0ac
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622881042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gati
ng.1622881042
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.3703939052
Short name T550
Test name
Test status
Simulation time 331331979671 ps
CPU time 743.25 seconds
Started Jul 21 05:40:07 PM PDT 24
Finished Jul 21 05:52:31 PM PDT 24
Peak memory 201664 kb
Host smart-ce20debc-471e-444c-8ae8-aedf2625c812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703939052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.3703939052
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.1310060122
Short name T562
Test name
Test status
Simulation time 495340588844 ps
CPU time 1193.7 seconds
Started Jul 21 05:40:10 PM PDT 24
Finished Jul 21 06:00:05 PM PDT 24
Peak memory 201672 kb
Host smart-a7cd2670-50a6-4b7c-8182-9e3b7755742a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310060122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrup
t_fixed.1310060122
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.934095331
Short name T664
Test name
Test status
Simulation time 160094999830 ps
CPU time 103.74 seconds
Started Jul 21 05:40:08 PM PDT 24
Finished Jul 21 05:41:52 PM PDT 24
Peak memory 201752 kb
Host smart-3d80b35d-021d-45c3-935c-0412c5a97633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934095331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.934095331
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.3866954213
Short name T660
Test name
Test status
Simulation time 329652511538 ps
CPU time 774.99 seconds
Started Jul 21 05:40:09 PM PDT 24
Finished Jul 21 05:53:04 PM PDT 24
Peak memory 201736 kb
Host smart-b5f70a3d-f2f6-4b60-bbfd-e06dc62871ef
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866954213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixe
d.3866954213
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.1106403921
Short name T320
Test name
Test status
Simulation time 534607836804 ps
CPU time 190.77 seconds
Started Jul 21 05:40:13 PM PDT 24
Finished Jul 21 05:43:25 PM PDT 24
Peak memory 201636 kb
Host smart-023fe306-3600-4ed6-a9dd-50b1a4554e09
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106403921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_
wakeup.1106403921
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.1590505288
Short name T623
Test name
Test status
Simulation time 594744047491 ps
CPU time 1255.87 seconds
Started Jul 21 05:40:12 PM PDT 24
Finished Jul 21 06:01:08 PM PDT 24
Peak memory 201508 kb
Host smart-a965995b-5ab7-4d41-8d0a-eb45e2cc6f7d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590505288 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
adc_ctrl_filters_wakeup_fixed.1590505288
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.3589875730
Short name T170
Test name
Test status
Simulation time 59817773312 ps
CPU time 223.53 seconds
Started Jul 21 05:40:19 PM PDT 24
Finished Jul 21 05:44:04 PM PDT 24
Peak memory 202048 kb
Host smart-10af7119-e3ee-4de6-b527-b14859d288ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589875730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.3589875730
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.1468720845
Short name T639
Test name
Test status
Simulation time 42547595851 ps
CPU time 28.1 seconds
Started Jul 21 05:40:16 PM PDT 24
Finished Jul 21 05:40:44 PM PDT 24
Peak memory 201604 kb
Host smart-3077088d-518d-4a58-8b2c-e2b62b29b946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468720845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.1468720845
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.1433936558
Short name T488
Test name
Test status
Simulation time 2711886108 ps
CPU time 2.47 seconds
Started Jul 21 05:40:16 PM PDT 24
Finished Jul 21 05:40:19 PM PDT 24
Peak memory 201540 kb
Host smart-a3f0077a-103e-472e-91db-8fa628564af8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433936558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.1433936558
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.894251134
Short name T52
Test name
Test status
Simulation time 4273660900 ps
CPU time 11 seconds
Started Jul 21 05:40:15 PM PDT 24
Finished Jul 21 05:40:26 PM PDT 24
Peak memory 217216 kb
Host smart-56803396-bbcc-4757-a6c4-4da0e3c97d57
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894251134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.894251134
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.2569537821
Short name T398
Test name
Test status
Simulation time 5743433728 ps
CPU time 9.44 seconds
Started Jul 21 05:40:13 PM PDT 24
Finished Jul 21 05:40:23 PM PDT 24
Peak memory 201588 kb
Host smart-d7fb4f76-56b7-4d79-b797-c96d24e54534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569537821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.2569537821
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.1551815001
Short name T23
Test name
Test status
Simulation time 9034565931 ps
CPU time 21.59 seconds
Started Jul 21 05:40:15 PM PDT 24
Finished Jul 21 05:40:38 PM PDT 24
Peak memory 201584 kb
Host smart-351922a0-a884-4084-b833-92318645d9dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551815001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.
1551815001
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.2429792322
Short name T696
Test name
Test status
Simulation time 26849623315 ps
CPU time 51.57 seconds
Started Jul 21 05:40:15 PM PDT 24
Finished Jul 21 05:41:07 PM PDT 24
Peak memory 210072 kb
Host smart-ee9db0d1-a22c-47f2-9c98-552a4165e9cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429792322 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.2429792322
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.5563196
Short name T478
Test name
Test status
Simulation time 340709591 ps
CPU time 1.19 seconds
Started Jul 21 05:44:22 PM PDT 24
Finished Jul 21 05:44:23 PM PDT 24
Peak memory 201476 kb
Host smart-fe314c58-8cb4-44ab-8843-2c7cde9e02d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5563196 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.5563196
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.3686337694
Short name T750
Test name
Test status
Simulation time 161818215583 ps
CPU time 88.95 seconds
Started Jul 21 05:44:14 PM PDT 24
Finished Jul 21 05:45:43 PM PDT 24
Peak memory 201732 kb
Host smart-9770f693-cdc3-4923-b6ec-bafc2567a461
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686337694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gat
ing.3686337694
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.2507724440
Short name T233
Test name
Test status
Simulation time 361442929076 ps
CPU time 455.87 seconds
Started Jul 21 05:44:16 PM PDT 24
Finished Jul 21 05:51:52 PM PDT 24
Peak memory 201736 kb
Host smart-f2e1e4ea-d8cc-4802-bcc5-a2b78888dc9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507724440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.2507724440
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.3132832816
Short name T272
Test name
Test status
Simulation time 163163340227 ps
CPU time 393.59 seconds
Started Jul 21 05:44:15 PM PDT 24
Finished Jul 21 05:50:49 PM PDT 24
Peak memory 201748 kb
Host smart-26b7975e-7583-453e-ac90-0dfbbd839cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132832816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.3132832816
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.1744601881
Short name T727
Test name
Test status
Simulation time 329086930381 ps
CPU time 148.94 seconds
Started Jul 21 05:44:16 PM PDT 24
Finished Jul 21 05:46:45 PM PDT 24
Peak memory 201720 kb
Host smart-456580d5-d2e6-4ea0-b78d-eea6e072e6fc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744601881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interru
pt_fixed.1744601881
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.3722320146
Short name T768
Test name
Test status
Simulation time 495059143313 ps
CPU time 317.15 seconds
Started Jul 21 05:44:15 PM PDT 24
Finished Jul 21 05:49:33 PM PDT 24
Peak memory 201784 kb
Host smart-f9165d5d-cf99-4e3a-8c5f-6ab6bd60eaf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722320146 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.3722320146
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.2282673926
Short name T575
Test name
Test status
Simulation time 504521058259 ps
CPU time 1152.78 seconds
Started Jul 21 05:44:15 PM PDT 24
Finished Jul 21 06:03:28 PM PDT 24
Peak memory 201624 kb
Host smart-f2df0441-248e-4081-ae7c-fe33a95a449e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282673926 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fix
ed.2282673926
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.719528262
Short name T749
Test name
Test status
Simulation time 188844586131 ps
CPU time 71.64 seconds
Started Jul 21 05:44:15 PM PDT 24
Finished Jul 21 05:45:27 PM PDT 24
Peak memory 201796 kb
Host smart-86554a0a-fc66-4913-af36-d5c40a03309b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719528262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_
wakeup.719528262
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.2452893732
Short name T147
Test name
Test status
Simulation time 193480374324 ps
CPU time 101.54 seconds
Started Jul 21 05:44:16 PM PDT 24
Finished Jul 21 05:45:58 PM PDT 24
Peak memory 201724 kb
Host smart-d48645e2-1339-4a2d-a451-1986b1882b26
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452893732 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.adc_ctrl_filters_wakeup_fixed.2452893732
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.4149564614
Short name T753
Test name
Test status
Simulation time 112062608923 ps
CPU time 584.22 seconds
Started Jul 21 05:44:23 PM PDT 24
Finished Jul 21 05:54:08 PM PDT 24
Peak memory 202136 kb
Host smart-a38d2930-22a4-4f9b-a0e8-ea0f47c35db1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149564614 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.4149564614
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.3509175473
Short name T635
Test name
Test status
Simulation time 33726849436 ps
CPU time 20.04 seconds
Started Jul 21 05:44:22 PM PDT 24
Finished Jul 21 05:44:43 PM PDT 24
Peak memory 201604 kb
Host smart-3277c86b-14b6-4eae-80ce-bd710980f2fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509175473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.3509175473
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.3460448515
Short name T739
Test name
Test status
Simulation time 3810753565 ps
CPU time 9.62 seconds
Started Jul 21 05:44:22 PM PDT 24
Finished Jul 21 05:44:32 PM PDT 24
Peak memory 201656 kb
Host smart-f4fdfaf6-e0e2-4433-8f30-5d9f822e3f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460448515 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.3460448515
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.3333593287
Short name T442
Test name
Test status
Simulation time 6178266281 ps
CPU time 14.9 seconds
Started Jul 21 05:44:17 PM PDT 24
Finished Jul 21 05:44:32 PM PDT 24
Peak memory 201476 kb
Host smart-9e4ee9e5-2bb4-4bf6-877f-e226409b0a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333593287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.3333593287
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.3314309217
Short name T1
Test name
Test status
Simulation time 90718625748 ps
CPU time 284.69 seconds
Started Jul 21 05:44:23 PM PDT 24
Finished Jul 21 05:49:08 PM PDT 24
Peak memory 202080 kb
Host smart-30d84a10-9f62-429c-b825-64b3223eb495
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314309217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all
.3314309217
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.4232573896
Short name T775
Test name
Test status
Simulation time 30878938508 ps
CPU time 18.48 seconds
Started Jul 21 05:44:23 PM PDT 24
Finished Jul 21 05:44:42 PM PDT 24
Peak memory 210136 kb
Host smart-7209515b-3d35-4ab1-bd20-4bc11cb87295
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232573896 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.4232573896
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.2739905390
Short name T558
Test name
Test status
Simulation time 284727937 ps
CPU time 1.25 seconds
Started Jul 21 05:44:30 PM PDT 24
Finished Jul 21 05:44:32 PM PDT 24
Peak memory 201544 kb
Host smart-ea7de94d-f974-4377-aa91-419ace9a9918
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739905390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.2739905390
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.4000355396
Short name T556
Test name
Test status
Simulation time 178831282580 ps
CPU time 422.81 seconds
Started Jul 21 05:44:29 PM PDT 24
Finished Jul 21 05:51:33 PM PDT 24
Peak memory 201644 kb
Host smart-c8ce803b-b144-4472-8b6e-ec1b06641311
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000355396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gat
ing.4000355396
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.3625791572
Short name T563
Test name
Test status
Simulation time 346438077563 ps
CPU time 203.47 seconds
Started Jul 21 05:44:29 PM PDT 24
Finished Jul 21 05:47:53 PM PDT 24
Peak memory 201756 kb
Host smart-01fcb701-0501-463d-bda1-7c011952fe0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625791572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.3625791572
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.4287935408
Short name T138
Test name
Test status
Simulation time 324723016933 ps
CPU time 823.26 seconds
Started Jul 21 05:44:22 PM PDT 24
Finished Jul 21 05:58:06 PM PDT 24
Peak memory 201744 kb
Host smart-db2d1fa9-6238-4eec-82de-52d91e01e119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287935408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.4287935408
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.1671764955
Short name T417
Test name
Test status
Simulation time 489343268341 ps
CPU time 1128.7 seconds
Started Jul 21 05:44:23 PM PDT 24
Finished Jul 21 06:03:12 PM PDT 24
Peak memory 201660 kb
Host smart-37dd3d58-2011-4656-bb9c-9242b8651cd4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671764955 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interru
pt_fixed.1671764955
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.2814562871
Short name T76
Test name
Test status
Simulation time 329165730508 ps
CPU time 689.97 seconds
Started Jul 21 05:44:22 PM PDT 24
Finished Jul 21 05:55:52 PM PDT 24
Peak memory 201700 kb
Host smart-691fe8ae-376f-4708-b578-3c15f719ec03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814562871 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.2814562871
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.303612397
Short name T706
Test name
Test status
Simulation time 162719329474 ps
CPU time 103.61 seconds
Started Jul 21 05:44:23 PM PDT 24
Finished Jul 21 05:46:06 PM PDT 24
Peak memory 201764 kb
Host smart-7b741d86-cc27-4406-acc2-f7f7d58d2f39
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=303612397 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fixe
d.303612397
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.2892138431
Short name T475
Test name
Test status
Simulation time 404590183177 ps
CPU time 842.8 seconds
Started Jul 21 05:44:29 PM PDT 24
Finished Jul 21 05:58:33 PM PDT 24
Peak memory 201660 kb
Host smart-5d51b976-fdd2-4b8b-840a-bc7496717d16
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892138431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.adc_ctrl_filters_wakeup_fixed.2892138431
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.1489184999
Short name T492
Test name
Test status
Simulation time 126302652012 ps
CPU time 704.39 seconds
Started Jul 21 05:44:29 PM PDT 24
Finished Jul 21 05:56:14 PM PDT 24
Peak memory 202164 kb
Host smart-dd93c72d-5bc0-463c-b56d-14a3fe0959ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489184999 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.1489184999
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.1599310092
Short name T703
Test name
Test status
Simulation time 46846478533 ps
CPU time 110.46 seconds
Started Jul 21 05:44:28 PM PDT 24
Finished Jul 21 05:46:19 PM PDT 24
Peak memory 201508 kb
Host smart-b67113e7-5bb4-40de-b7f0-ecfb2b30ce2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599310092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.1599310092
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.1462353086
Short name T625
Test name
Test status
Simulation time 3124896915 ps
CPU time 2.56 seconds
Started Jul 21 05:44:29 PM PDT 24
Finished Jul 21 05:44:32 PM PDT 24
Peak memory 201536 kb
Host smart-14a08e9a-21a9-44a7-bd3d-86a37ca0f0ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462353086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.1462353086
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.3858823255
Short name T415
Test name
Test status
Simulation time 5869512264 ps
CPU time 4.2 seconds
Started Jul 21 05:44:22 PM PDT 24
Finished Jul 21 05:44:27 PM PDT 24
Peak memory 201496 kb
Host smart-27e83f84-f93f-4399-8242-1fb706eb0717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858823255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.3858823255
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.1402610270
Short name T196
Test name
Test status
Simulation time 482516483333 ps
CPU time 542.58 seconds
Started Jul 21 05:44:28 PM PDT 24
Finished Jul 21 05:53:31 PM PDT 24
Peak memory 201712 kb
Host smart-4aa7ce5d-6eb9-49d9-8447-7c6c849347f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402610270 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all
.1402610270
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.3334652592
Short name T782
Test name
Test status
Simulation time 174868871714 ps
CPU time 111.44 seconds
Started Jul 21 05:44:29 PM PDT 24
Finished Jul 21 05:46:21 PM PDT 24
Peak memory 201876 kb
Host smart-c1b56ab7-d91a-44fb-a4ee-eda99a5e6a95
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334652592 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.3334652592
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.4148016118
Short name T363
Test name
Test status
Simulation time 415345121 ps
CPU time 1.08 seconds
Started Jul 21 05:44:42 PM PDT 24
Finished Jul 21 05:44:43 PM PDT 24
Peak memory 201436 kb
Host smart-b317c58e-1a78-40cb-b8fe-8227c867741a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148016118 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.4148016118
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.2863995586
Short name T553
Test name
Test status
Simulation time 163427242708 ps
CPU time 77.93 seconds
Started Jul 21 05:44:42 PM PDT 24
Finished Jul 21 05:46:00 PM PDT 24
Peak memory 201812 kb
Host smart-1cb82955-6171-42c6-ac8f-bbe065195384
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863995586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gat
ing.2863995586
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.71029405
Short name T651
Test name
Test status
Simulation time 328266489355 ps
CPU time 758.93 seconds
Started Jul 21 05:44:35 PM PDT 24
Finished Jul 21 05:57:15 PM PDT 24
Peak memory 201752 kb
Host smart-c87186df-e180-4342-a63a-514f07dc01e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71029405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.71029405
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.1612270867
Short name T788
Test name
Test status
Simulation time 164290633194 ps
CPU time 29.83 seconds
Started Jul 21 05:44:35 PM PDT 24
Finished Jul 21 05:45:05 PM PDT 24
Peak memory 201608 kb
Host smart-7ca5108a-818b-4dcb-bc24-24f5c84eda43
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612270867 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interru
pt_fixed.1612270867
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.3153105044
Short name T737
Test name
Test status
Simulation time 485296670390 ps
CPU time 289.27 seconds
Started Jul 21 05:44:35 PM PDT 24
Finished Jul 21 05:49:25 PM PDT 24
Peak memory 201728 kb
Host smart-dbbc9dde-a54c-44e2-a2e9-cc7051b690ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153105044 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.3153105044
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.1069630727
Short name T518
Test name
Test status
Simulation time 163587604235 ps
CPU time 324.71 seconds
Started Jul 21 05:44:35 PM PDT 24
Finished Jul 21 05:50:00 PM PDT 24
Peak memory 201660 kb
Host smart-b8b667a4-66a0-489d-96a1-bc649093d355
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069630727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fix
ed.1069630727
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.786630581
Short name T232
Test name
Test status
Simulation time 194480695123 ps
CPU time 99.93 seconds
Started Jul 21 05:44:34 PM PDT 24
Finished Jul 21 05:46:15 PM PDT 24
Peak memory 201700 kb
Host smart-f032d47c-6c81-4fa2-aad1-95c804cd932d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786630581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_
wakeup.786630581
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.3808335904
Short name T549
Test name
Test status
Simulation time 197671204793 ps
CPU time 455.73 seconds
Started Jul 21 05:44:41 PM PDT 24
Finished Jul 21 05:52:17 PM PDT 24
Peak memory 201744 kb
Host smart-b05e9047-5eb5-41b5-804b-d4be13a9b8d1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808335904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.adc_ctrl_filters_wakeup_fixed.3808335904
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.2855311400
Short name T412
Test name
Test status
Simulation time 126368726079 ps
CPU time 461 seconds
Started Jul 21 05:44:42 PM PDT 24
Finished Jul 21 05:52:24 PM PDT 24
Peak memory 202176 kb
Host smart-04675745-86c2-488f-9737-06ddbd25ea39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855311400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.2855311400
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.134824457
Short name T595
Test name
Test status
Simulation time 40263489837 ps
CPU time 23.75 seconds
Started Jul 21 05:44:43 PM PDT 24
Finished Jul 21 05:45:07 PM PDT 24
Peak memory 201420 kb
Host smart-7050367e-94f9-4899-9633-2201936b434a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134824457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.134824457
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.1590032503
Short name T519
Test name
Test status
Simulation time 4947866647 ps
CPU time 2.51 seconds
Started Jul 21 05:44:42 PM PDT 24
Finished Jul 21 05:44:45 PM PDT 24
Peak memory 201540 kb
Host smart-69de5295-b493-4997-93d0-8900770e07e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590032503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.1590032503
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.2261112540
Short name T121
Test name
Test status
Simulation time 5652685159 ps
CPU time 6.99 seconds
Started Jul 21 05:44:29 PM PDT 24
Finished Jul 21 05:44:36 PM PDT 24
Peak memory 201576 kb
Host smart-8d8de3b5-77a1-4fbb-8200-7834dec9e453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261112540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.2261112540
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.3105240628
Short name T766
Test name
Test status
Simulation time 264363622190 ps
CPU time 897.76 seconds
Started Jul 21 05:44:41 PM PDT 24
Finished Jul 21 05:59:39 PM PDT 24
Peak memory 202096 kb
Host smart-1fcd17cb-85bd-4d83-912d-63567b121b42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105240628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all
.3105240628
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.3451686069
Short name T485
Test name
Test status
Simulation time 47606572190 ps
CPU time 27.11 seconds
Started Jul 21 05:44:44 PM PDT 24
Finished Jul 21 05:45:11 PM PDT 24
Peak memory 210456 kb
Host smart-ec5cd765-f40a-4656-9288-629ca7d827c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451686069 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.3451686069
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.2844557997
Short name T731
Test name
Test status
Simulation time 433179035 ps
CPU time 0.77 seconds
Started Jul 21 05:44:54 PM PDT 24
Finished Jul 21 05:44:55 PM PDT 24
Peak memory 201364 kb
Host smart-d60d7e09-1cf8-4444-b370-c74ba66446b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844557997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.2844557997
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.2581551099
Short name T293
Test name
Test status
Simulation time 635652621511 ps
CPU time 406.94 seconds
Started Jul 21 05:44:47 PM PDT 24
Finished Jul 21 05:51:34 PM PDT 24
Peak memory 201804 kb
Host smart-9da097c2-a0c9-4241-a6ae-48aa15d8c045
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581551099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gat
ing.2581551099
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.3197657023
Short name T133
Test name
Test status
Simulation time 163646661186 ps
CPU time 68.21 seconds
Started Jul 21 05:44:48 PM PDT 24
Finished Jul 21 05:45:57 PM PDT 24
Peak memory 201816 kb
Host smart-deda6732-08d7-44b7-b1c5-1fa501d86ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197657023 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.3197657023
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.2103904821
Short name T150
Test name
Test status
Simulation time 490444159732 ps
CPU time 273.24 seconds
Started Jul 21 05:44:47 PM PDT 24
Finished Jul 21 05:49:20 PM PDT 24
Peak memory 201656 kb
Host smart-b420996f-5cd2-42e0-84df-a0a4a348a8ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103904821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.2103904821
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.848534747
Short name T70
Test name
Test status
Simulation time 326293258164 ps
CPU time 746.04 seconds
Started Jul 21 05:44:48 PM PDT 24
Finished Jul 21 05:57:15 PM PDT 24
Peak memory 201752 kb
Host smart-6b3533d9-869a-476f-97fd-32cc61ce23c0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=848534747 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrup
t_fixed.848534747
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.3294621722
Short name T496
Test name
Test status
Simulation time 327507385502 ps
CPU time 195.34 seconds
Started Jul 21 05:44:53 PM PDT 24
Finished Jul 21 05:48:09 PM PDT 24
Peak memory 201912 kb
Host smart-6e8db590-c6d4-4151-b9a0-e8ad96b55ea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294621722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.3294621722
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.1061922390
Short name T431
Test name
Test status
Simulation time 161490838850 ps
CPU time 77.81 seconds
Started Jul 21 05:44:47 PM PDT 24
Finished Jul 21 05:46:05 PM PDT 24
Peak memory 201600 kb
Host smart-61def13c-39d2-47e0-ba1d-4a07529e25f5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061922390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fix
ed.1061922390
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.3489078419
Short name T329
Test name
Test status
Simulation time 562000512540 ps
CPU time 707.04 seconds
Started Jul 21 05:44:47 PM PDT 24
Finished Jul 21 05:56:34 PM PDT 24
Peak memory 201804 kb
Host smart-3164b528-46ed-486c-896c-f4a4b8f01633
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489078419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters
_wakeup.3489078419
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.2481513460
Short name T453
Test name
Test status
Simulation time 201896681291 ps
CPU time 126.32 seconds
Started Jul 21 05:44:49 PM PDT 24
Finished Jul 21 05:46:56 PM PDT 24
Peak memory 201692 kb
Host smart-68a9c118-de51-45b4-8ccf-65843646bc1b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481513460 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.adc_ctrl_filters_wakeup_fixed.2481513460
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.3208840451
Short name T680
Test name
Test status
Simulation time 128867381130 ps
CPU time 493.12 seconds
Started Jul 21 05:44:54 PM PDT 24
Finished Jul 21 05:53:07 PM PDT 24
Peak memory 202204 kb
Host smart-4b76718d-0736-4fb8-99a5-79206a23430f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208840451 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.3208840451
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.2874143553
Short name T388
Test name
Test status
Simulation time 46844101622 ps
CPU time 85.51 seconds
Started Jul 21 05:44:53 PM PDT 24
Finished Jul 21 05:46:19 PM PDT 24
Peak memory 201492 kb
Host smart-7c5044fa-70b1-42ac-815e-17b758c06537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874143553 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.2874143553
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.2942888213
Short name T371
Test name
Test status
Simulation time 4388246024 ps
CPU time 6.56 seconds
Started Jul 21 05:44:54 PM PDT 24
Finished Jul 21 05:45:01 PM PDT 24
Peak memory 201576 kb
Host smart-d9937fec-5bed-44f5-9e24-e184553ac8c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942888213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.2942888213
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.1011594338
Short name T451
Test name
Test status
Simulation time 5796337070 ps
CPU time 3.87 seconds
Started Jul 21 05:44:41 PM PDT 24
Finished Jul 21 05:44:45 PM PDT 24
Peak memory 201484 kb
Host smart-1d518147-f6e7-42a3-b445-6b1e8fb34173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011594338 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.1011594338
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.2042378169
Short name T229
Test name
Test status
Simulation time 336004242919 ps
CPU time 384.59 seconds
Started Jul 21 05:44:54 PM PDT 24
Finished Jul 21 05:51:18 PM PDT 24
Peak memory 201728 kb
Host smart-dad0ddf9-a852-4e49-873c-7dae43d3e84f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042378169 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all
.2042378169
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.3356378361
Short name T32
Test name
Test status
Simulation time 224039580411 ps
CPU time 112.7 seconds
Started Jul 21 05:44:53 PM PDT 24
Finished Jul 21 05:46:46 PM PDT 24
Peak memory 209884 kb
Host smart-4ec5e934-63ec-473a-b98a-d70427f0cd87
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356378361 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.3356378361
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.3834873726
Short name T587
Test name
Test status
Simulation time 314158083 ps
CPU time 0.84 seconds
Started Jul 21 05:45:07 PM PDT 24
Finished Jul 21 05:45:08 PM PDT 24
Peak memory 201552 kb
Host smart-dee8ac9b-bc99-482a-a970-c6d44c64b308
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834873726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.3834873726
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.1543615823
Short name T128
Test name
Test status
Simulation time 160662467748 ps
CPU time 330.27 seconds
Started Jul 21 05:45:09 PM PDT 24
Finished Jul 21 05:50:40 PM PDT 24
Peak memory 201888 kb
Host smart-99ba85c2-50d4-49dc-98be-34a1f089972f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543615823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gat
ing.1543615823
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.1817592748
Short name T318
Test name
Test status
Simulation time 411869755581 ps
CPU time 237.86 seconds
Started Jul 21 05:45:00 PM PDT 24
Finished Jul 21 05:48:58 PM PDT 24
Peak memory 201688 kb
Host smart-ed1963be-2ba5-4b63-984b-ce4385066baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817592748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.1817592748
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.3338343302
Short name T467
Test name
Test status
Simulation time 324146103848 ps
CPU time 136.91 seconds
Started Jul 21 05:45:09 PM PDT 24
Finished Jul 21 05:47:26 PM PDT 24
Peak memory 201876 kb
Host smart-1d56dbcc-555a-477e-b787-d7ebbadeb33f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338343302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interru
pt_fixed.3338343302
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.918076705
Short name T769
Test name
Test status
Simulation time 164767191056 ps
CPU time 54.9 seconds
Started Jul 21 05:44:59 PM PDT 24
Finished Jul 21 05:45:55 PM PDT 24
Peak memory 201776 kb
Host smart-9cf728e3-1cbd-416f-a677-ffa9ea66bbe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918076705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.918076705
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.289557762
Short name T418
Test name
Test status
Simulation time 324208974719 ps
CPU time 376.35 seconds
Started Jul 21 05:45:00 PM PDT 24
Finished Jul 21 05:51:17 PM PDT 24
Peak memory 201732 kb
Host smart-f860c861-fda2-449a-8408-9bf295918a8f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=289557762 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fixe
d.289557762
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.4260999461
Short name T659
Test name
Test status
Simulation time 563440350230 ps
CPU time 325.86 seconds
Started Jul 21 05:45:02 PM PDT 24
Finished Jul 21 05:50:28 PM PDT 24
Peak memory 201640 kb
Host smart-a0240b92-4a89-45f4-85dd-a50a66e92600
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260999461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters
_wakeup.4260999461
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.3657267105
Short name T130
Test name
Test status
Simulation time 421844398104 ps
CPU time 142.4 seconds
Started Jul 21 05:45:00 PM PDT 24
Finished Jul 21 05:47:23 PM PDT 24
Peak memory 201632 kb
Host smart-e4e08662-5ef1-4c52-8792-b2aa9d640442
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657267105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.adc_ctrl_filters_wakeup_fixed.3657267105
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.512297019
Short name T85
Test name
Test status
Simulation time 131638224533 ps
CPU time 607.51 seconds
Started Jul 21 05:45:01 PM PDT 24
Finished Jul 21 05:55:09 PM PDT 24
Peak memory 202160 kb
Host smart-e62a515d-de24-4053-9a2e-34d25c5e881d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512297019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.512297019
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.171214755
Short name T666
Test name
Test status
Simulation time 38290135128 ps
CPU time 87.7 seconds
Started Jul 21 05:45:00 PM PDT 24
Finished Jul 21 05:46:28 PM PDT 24
Peak memory 201484 kb
Host smart-918e28d9-052c-470c-9243-504259d7b0f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171214755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.171214755
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.1012854376
Short name T552
Test name
Test status
Simulation time 4064840905 ps
CPU time 5.49 seconds
Started Jul 21 05:45:00 PM PDT 24
Finished Jul 21 05:45:06 PM PDT 24
Peak memory 201492 kb
Host smart-de9e8d42-8d54-4a4f-943f-3585861eb879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012854376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.1012854376
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.1924108098
Short name T653
Test name
Test status
Simulation time 5750780474 ps
CPU time 12.99 seconds
Started Jul 21 05:45:00 PM PDT 24
Finished Jul 21 05:45:13 PM PDT 24
Peak memory 201624 kb
Host smart-570c5b1b-b32c-493e-942f-56ff983912fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924108098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.1924108098
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.715018701
Short name T662
Test name
Test status
Simulation time 41078777623 ps
CPU time 93.22 seconds
Started Jul 21 05:45:08 PM PDT 24
Finished Jul 21 05:46:42 PM PDT 24
Peak memory 201808 kb
Host smart-053a3680-3685-4dbb-82f6-c0de4fa7e82a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715018701 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all.
715018701
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.975695863
Short name T86
Test name
Test status
Simulation time 377431289 ps
CPU time 1.45 seconds
Started Jul 21 05:45:15 PM PDT 24
Finished Jul 21 05:45:16 PM PDT 24
Peak memory 201552 kb
Host smart-19d76b56-1d20-4aec-a771-82810dc84f8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975695863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.975695863
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.1135479250
Short name T152
Test name
Test status
Simulation time 535796962355 ps
CPU time 235.81 seconds
Started Jul 21 05:45:12 PM PDT 24
Finished Jul 21 05:49:08 PM PDT 24
Peak memory 201668 kb
Host smart-5f446298-8cf4-4da5-b527-67ff805480d2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135479250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gat
ing.1135479250
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.1741778600
Short name T213
Test name
Test status
Simulation time 555873957805 ps
CPU time 265.45 seconds
Started Jul 21 05:45:08 PM PDT 24
Finished Jul 21 05:49:34 PM PDT 24
Peak memory 201776 kb
Host smart-6b9d6a4c-80dc-41f1-8cb3-e4516bfe790c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741778600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.1741778600
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.3953810132
Short name T287
Test name
Test status
Simulation time 484468177872 ps
CPU time 1092.22 seconds
Started Jul 21 05:45:08 PM PDT 24
Finished Jul 21 06:03:21 PM PDT 24
Peak memory 201800 kb
Host smart-1aca8ccc-053d-473f-be9a-786e730ada58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953810132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.3953810132
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.3000448832
Short name T774
Test name
Test status
Simulation time 325048168227 ps
CPU time 203.39 seconds
Started Jul 21 05:45:11 PM PDT 24
Finished Jul 21 05:48:35 PM PDT 24
Peak memory 201680 kb
Host smart-d78af0b8-3388-400a-9623-74b7718e009f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000448832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interru
pt_fixed.3000448832
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.3127339647
Short name T640
Test name
Test status
Simulation time 333922916920 ps
CPU time 822.01 seconds
Started Jul 21 05:45:08 PM PDT 24
Finished Jul 21 05:58:51 PM PDT 24
Peak memory 201676 kb
Host smart-04286951-b3a5-4022-b924-1c7dd3244143
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127339647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fix
ed.3127339647
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.79932462
Short name T624
Test name
Test status
Simulation time 206403853679 ps
CPU time 452.23 seconds
Started Jul 21 05:45:08 PM PDT 24
Finished Jul 21 05:52:40 PM PDT 24
Peak memory 201736 kb
Host smart-07c69090-826a-4e05-b178-1a2aed693d65
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79932462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_w
akeup.79932462
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.4096057680
Short name T427
Test name
Test status
Simulation time 622971740599 ps
CPU time 240.95 seconds
Started Jul 21 05:45:08 PM PDT 24
Finished Jul 21 05:49:09 PM PDT 24
Peak memory 201672 kb
Host smart-a5d64cd9-c7e8-4380-ac11-dc92145d6351
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096057680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.adc_ctrl_filters_wakeup_fixed.4096057680
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.2216492184
Short name T333
Test name
Test status
Simulation time 122395815217 ps
CPU time 416.99 seconds
Started Jul 21 05:45:14 PM PDT 24
Finished Jul 21 05:52:11 PM PDT 24
Peak memory 202160 kb
Host smart-6550e1a8-63db-4c28-a50e-f7f2e9257512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216492184 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.2216492184
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.2963177742
Short name T621
Test name
Test status
Simulation time 31131214580 ps
CPU time 61.65 seconds
Started Jul 21 05:45:15 PM PDT 24
Finished Jul 21 05:46:17 PM PDT 24
Peak memory 201600 kb
Host smart-f7515ef1-ffb6-41be-a332-7c0db61010b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963177742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.2963177742
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.2707912446
Short name T620
Test name
Test status
Simulation time 5312597318 ps
CPU time 12.01 seconds
Started Jul 21 05:45:08 PM PDT 24
Finished Jul 21 05:45:21 PM PDT 24
Peak memory 201524 kb
Host smart-645fab44-e647-4b71-bff5-28cd46e27d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707912446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.2707912446
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.4254222353
Short name T601
Test name
Test status
Simulation time 5916911247 ps
CPU time 4.84 seconds
Started Jul 21 05:45:08 PM PDT 24
Finished Jul 21 05:45:13 PM PDT 24
Peak memory 201604 kb
Host smart-98080be8-e7f7-4e90-9797-8fb869462171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254222353 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.4254222353
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.2524973912
Short name T235
Test name
Test status
Simulation time 126283998088 ps
CPU time 112.89 seconds
Started Jul 21 05:45:16 PM PDT 24
Finished Jul 21 05:47:09 PM PDT 24
Peak memory 210496 kb
Host smart-195bfd50-9613-4158-8fd7-3e456643f76b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524973912 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.2524973912
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.1073014997
Short name T423
Test name
Test status
Simulation time 502562666 ps
CPU time 1.12 seconds
Started Jul 21 05:45:25 PM PDT 24
Finished Jul 21 05:45:27 PM PDT 24
Peak memory 201600 kb
Host smart-76a06f13-723d-479b-a79d-79529b7dc358
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073014997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.1073014997
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.2854782372
Short name T240
Test name
Test status
Simulation time 568558519338 ps
CPU time 604.27 seconds
Started Jul 21 05:45:19 PM PDT 24
Finished Jul 21 05:55:24 PM PDT 24
Peak memory 201676 kb
Host smart-9ae5aa89-da2f-455b-b036-a5e674dc94dc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854782372 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gat
ing.2854782372
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.365017593
Short name T165
Test name
Test status
Simulation time 499020090224 ps
CPU time 283.5 seconds
Started Jul 21 05:45:18 PM PDT 24
Finished Jul 21 05:50:02 PM PDT 24
Peak memory 201628 kb
Host smart-f8225e7a-6fcd-4e90-bfdb-7725e2def779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365017593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.365017593
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.3156133474
Short name T510
Test name
Test status
Simulation time 162648188237 ps
CPU time 207.65 seconds
Started Jul 21 05:45:19 PM PDT 24
Finished Jul 21 05:48:47 PM PDT 24
Peak memory 201736 kb
Host smart-953a8e01-b0b4-4e3f-8bcc-10b516a0f15f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156133474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interru
pt_fixed.3156133474
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.585279481
Short name T221
Test name
Test status
Simulation time 489539859171 ps
CPU time 550.11 seconds
Started Jul 21 05:45:20 PM PDT 24
Finished Jul 21 05:54:31 PM PDT 24
Peak memory 201888 kb
Host smart-1f47e0eb-7464-4ad1-9b2d-15c0ece3a79d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585279481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.585279481
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.165466804
Short name T617
Test name
Test status
Simulation time 486709962430 ps
CPU time 590.14 seconds
Started Jul 21 05:45:18 PM PDT 24
Finished Jul 21 05:55:08 PM PDT 24
Peak memory 201600 kb
Host smart-b7483728-82fb-4312-abaa-3d78e021966f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=165466804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fixe
d.165466804
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.2887247832
Short name T123
Test name
Test status
Simulation time 521381013334 ps
CPU time 292.19 seconds
Started Jul 21 05:45:19 PM PDT 24
Finished Jul 21 05:50:12 PM PDT 24
Peak memory 201688 kb
Host smart-ed79e1da-2849-428f-84a6-51a9d4adcac8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887247832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters
_wakeup.2887247832
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.3510896346
Short name T619
Test name
Test status
Simulation time 401234102689 ps
CPU time 926.44 seconds
Started Jul 21 05:45:20 PM PDT 24
Finished Jul 21 06:00:47 PM PDT 24
Peak memory 201616 kb
Host smart-c215b9da-1066-46f5-95ad-2c7be1c6bd4d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510896346 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.adc_ctrl_filters_wakeup_fixed.3510896346
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.1855985171
Short name T688
Test name
Test status
Simulation time 88439303270 ps
CPU time 479.32 seconds
Started Jul 21 05:45:24 PM PDT 24
Finished Jul 21 05:53:23 PM PDT 24
Peak memory 202324 kb
Host smart-d42f0795-b7f8-4cdc-bb0a-711c57c6729d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855985171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.1855985171
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.2371121237
Short name T393
Test name
Test status
Simulation time 30209137058 ps
CPU time 16.51 seconds
Started Jul 21 05:45:20 PM PDT 24
Finished Jul 21 05:45:37 PM PDT 24
Peak memory 201488 kb
Host smart-888f7b9a-a305-48ca-9d38-d95c65382054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371121237 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.2371121237
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.4005598159
Short name T609
Test name
Test status
Simulation time 3121788851 ps
CPU time 8.3 seconds
Started Jul 21 05:45:19 PM PDT 24
Finished Jul 21 05:45:28 PM PDT 24
Peak memory 201604 kb
Host smart-cc733e6e-6075-4565-811a-dc66beee4786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005598159 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.4005598159
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.355485238
Short name T480
Test name
Test status
Simulation time 5863657174 ps
CPU time 1.85 seconds
Started Jul 21 05:45:15 PM PDT 24
Finished Jul 21 05:45:17 PM PDT 24
Peak memory 201496 kb
Host smart-4309daba-cafa-464e-9e63-543cd2be2dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355485238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.355485238
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.3049662154
Short name T33
Test name
Test status
Simulation time 196253516579 ps
CPU time 324.17 seconds
Started Jul 21 05:45:20 PM PDT 24
Finished Jul 21 05:50:45 PM PDT 24
Peak memory 218184 kb
Host smart-34908bbe-b15f-48a8-989f-d2fc17d0ad15
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049662154 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.3049662154
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.2869466683
Short name T636
Test name
Test status
Simulation time 670015899 ps
CPU time 0.7 seconds
Started Jul 21 05:45:40 PM PDT 24
Finished Jul 21 05:45:41 PM PDT 24
Peak memory 201580 kb
Host smart-9ff61b8d-193e-4dd5-86a8-cb868a06edcc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869466683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.2869466683
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.3781573267
Short name T9
Test name
Test status
Simulation time 197099931432 ps
CPU time 125.5 seconds
Started Jul 21 05:45:38 PM PDT 24
Finished Jul 21 05:47:44 PM PDT 24
Peak memory 201744 kb
Host smart-f36897db-218d-44c2-8874-3f08ce023b6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781573267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.3781573267
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.3677450787
Short name T448
Test name
Test status
Simulation time 167301332762 ps
CPU time 97.15 seconds
Started Jul 21 05:45:31 PM PDT 24
Finished Jul 21 05:47:08 PM PDT 24
Peak memory 201740 kb
Host smart-5829031b-1443-4102-9079-26aa94ed638e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677450787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.3677450787
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.2433590869
Short name T673
Test name
Test status
Simulation time 159428239771 ps
CPU time 112.7 seconds
Started Jul 21 05:45:32 PM PDT 24
Finished Jul 21 05:47:25 PM PDT 24
Peak memory 201708 kb
Host smart-b789b20e-839e-40e4-a3be-102a450ee1d9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433590869 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interru
pt_fixed.2433590869
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.1477603426
Short name T425
Test name
Test status
Simulation time 165054158221 ps
CPU time 231.06 seconds
Started Jul 21 05:45:29 PM PDT 24
Finished Jul 21 05:49:20 PM PDT 24
Peak memory 201896 kb
Host smart-5379827c-2d10-4b73-8346-e96cf59e6f8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477603426 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.1477603426
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.1252143923
Short name T602
Test name
Test status
Simulation time 332253657157 ps
CPU time 814.1 seconds
Started Jul 21 05:45:31 PM PDT 24
Finished Jul 21 05:59:05 PM PDT 24
Peak memory 201560 kb
Host smart-d93f5b75-cd25-422d-8296-c2438dfe1d3b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252143923 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fix
ed.1252143923
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.179630865
Short name T131
Test name
Test status
Simulation time 180508241734 ps
CPU time 442.65 seconds
Started Jul 21 05:45:34 PM PDT 24
Finished Jul 21 05:52:57 PM PDT 24
Peak memory 201728 kb
Host smart-40ffa43c-7449-465c-b7d6-105f735baf01
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179630865 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_
wakeup.179630865
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.649062764
Short name T718
Test name
Test status
Simulation time 614798034570 ps
CPU time 1370.84 seconds
Started Jul 21 05:45:31 PM PDT 24
Finished Jul 21 06:08:22 PM PDT 24
Peak memory 201696 kb
Host smart-b253c68a-14cd-48ca-9bcb-d2c23be71384
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649062764 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
adc_ctrl_filters_wakeup_fixed.649062764
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.1810793305
Short name T39
Test name
Test status
Simulation time 78931582332 ps
CPU time 436.72 seconds
Started Jul 21 05:45:39 PM PDT 24
Finished Jul 21 05:52:56 PM PDT 24
Peak memory 202064 kb
Host smart-45047618-edd8-41f6-b8aa-3fc1245a50fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810793305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.1810793305
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.215303568
Short name T615
Test name
Test status
Simulation time 37321672868 ps
CPU time 15.4 seconds
Started Jul 21 05:45:38 PM PDT 24
Finished Jul 21 05:45:54 PM PDT 24
Peak memory 201504 kb
Host smart-789574f1-c39a-4c98-89ae-21af46840753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215303568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.215303568
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.2591158527
Short name T96
Test name
Test status
Simulation time 3603592453 ps
CPU time 9.79 seconds
Started Jul 21 05:45:38 PM PDT 24
Finished Jul 21 05:45:48 PM PDT 24
Peak memory 201580 kb
Host smart-2be57920-bb3d-4d57-bd23-f72cf9f99bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591158527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.2591158527
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.3562946981
Short name T540
Test name
Test status
Simulation time 5781407027 ps
CPU time 4.15 seconds
Started Jul 21 05:45:26 PM PDT 24
Finished Jul 21 05:45:30 PM PDT 24
Peak memory 201508 kb
Host smart-4759dc2c-cd00-4760-90f4-bb78fb480fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562946981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.3562946981
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.833533085
Short name T282
Test name
Test status
Simulation time 328368112684 ps
CPU time 184.56 seconds
Started Jul 21 05:45:39 PM PDT 24
Finished Jul 21 05:48:44 PM PDT 24
Peak memory 201764 kb
Host smart-70b0bfd0-a928-474b-8bc1-76b156c1cf3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833533085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all.
833533085
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.3880627629
Short name T391
Test name
Test status
Simulation time 440386164 ps
CPU time 1.46 seconds
Started Jul 21 05:45:51 PM PDT 24
Finished Jul 21 05:45:52 PM PDT 24
Peak memory 201476 kb
Host smart-ee93173f-1c12-44d6-979d-1d98c82fdf2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880627629 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.3880627629
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.1224983891
Short name T719
Test name
Test status
Simulation time 160970846507 ps
CPU time 104.6 seconds
Started Jul 21 05:45:48 PM PDT 24
Finished Jul 21 05:47:33 PM PDT 24
Peak memory 201760 kb
Host smart-ee687b6e-fecd-4677-8b89-c6cbf8833d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224983891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.1224983891
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.2896046270
Short name T734
Test name
Test status
Simulation time 499340314392 ps
CPU time 869.64 seconds
Started Jul 21 05:45:38 PM PDT 24
Finished Jul 21 06:00:08 PM PDT 24
Peak memory 201672 kb
Host smart-b1a68851-8b57-4019-a16b-0d154cf70689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896046270 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.2896046270
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.327377514
Short name T546
Test name
Test status
Simulation time 490783794160 ps
CPU time 1143.72 seconds
Started Jul 21 05:45:39 PM PDT 24
Finished Jul 21 06:04:43 PM PDT 24
Peak memory 201584 kb
Host smart-32fc5202-ba4c-4b6c-9c3d-5705ffb284d4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=327377514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrup
t_fixed.327377514
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.476997764
Short name T189
Test name
Test status
Simulation time 493964524433 ps
CPU time 582.57 seconds
Started Jul 21 05:45:39 PM PDT 24
Finished Jul 21 05:55:22 PM PDT 24
Peak memory 201792 kb
Host smart-603d8582-ddc2-4179-a69b-5669ec602790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476997764 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.476997764
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.2646702884
Short name T760
Test name
Test status
Simulation time 493452676514 ps
CPU time 1092.48 seconds
Started Jul 21 05:45:39 PM PDT 24
Finished Jul 21 06:03:52 PM PDT 24
Peak memory 201536 kb
Host smart-b9f94dd0-ec27-435d-88cc-6929d88c2e6f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646702884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fix
ed.2646702884
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.2767762963
Short name T270
Test name
Test status
Simulation time 344598405528 ps
CPU time 415.93 seconds
Started Jul 21 05:45:39 PM PDT 24
Finished Jul 21 05:52:35 PM PDT 24
Peak memory 201700 kb
Host smart-b46ff78c-f7aa-4dde-b8ea-3c1bf8ee8265
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767762963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters
_wakeup.2767762963
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.3719169059
Short name T432
Test name
Test status
Simulation time 414786784161 ps
CPU time 130.11 seconds
Started Jul 21 05:45:45 PM PDT 24
Finished Jul 21 05:47:55 PM PDT 24
Peak memory 201732 kb
Host smart-1312e53f-5115-4793-bcd5-cb805f8af385
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719169059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.adc_ctrl_filters_wakeup_fixed.3719169059
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.2080864914
Short name T700
Test name
Test status
Simulation time 128223200791 ps
CPU time 620.65 seconds
Started Jul 21 05:45:46 PM PDT 24
Finished Jul 21 05:56:07 PM PDT 24
Peak memory 202168 kb
Host smart-11c0c5bd-5923-4c6c-b540-2935bab73b25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080864914 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.2080864914
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.3090967647
Short name T691
Test name
Test status
Simulation time 36273189688 ps
CPU time 19.74 seconds
Started Jul 21 05:45:46 PM PDT 24
Finished Jul 21 05:46:06 PM PDT 24
Peak memory 201616 kb
Host smart-10f33837-c375-4777-97e3-a6f4ccf46476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090967647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.3090967647
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.1253125973
Short name T772
Test name
Test status
Simulation time 5199610925 ps
CPU time 6.22 seconds
Started Jul 21 05:45:45 PM PDT 24
Finished Jul 21 05:45:51 PM PDT 24
Peak memory 201576 kb
Host smart-c42f7bb4-1430-4c32-bd5a-b81a8353eb71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253125973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.1253125973
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.2964825465
Short name T690
Test name
Test status
Simulation time 5565830615 ps
CPU time 6.99 seconds
Started Jul 21 05:45:38 PM PDT 24
Finished Jul 21 05:45:46 PM PDT 24
Peak memory 201584 kb
Host smart-6fd1cefd-4c8f-4c66-b233-164f6e2e1544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964825465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.2964825465
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.3113013018
Short name T577
Test name
Test status
Simulation time 421769162374 ps
CPU time 130.57 seconds
Started Jul 21 05:45:50 PM PDT 24
Finished Jul 21 05:48:01 PM PDT 24
Peak memory 201616 kb
Host smart-6d860a41-059e-484b-a725-577018fcc79d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113013018 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all
.3113013018
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.88724947
Short name T16
Test name
Test status
Simulation time 48839228900 ps
CPU time 115.46 seconds
Started Jul 21 05:45:50 PM PDT 24
Finished Jul 21 05:47:46 PM PDT 24
Peak memory 212312 kb
Host smart-e1ff54ae-fe8f-4398-a6df-a7659ff20076
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88724947 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.88724947
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.2312012488
Short name T685
Test name
Test status
Simulation time 512045811 ps
CPU time 1.25 seconds
Started Jul 21 05:46:05 PM PDT 24
Finished Jul 21 05:46:06 PM PDT 24
Peak memory 201536 kb
Host smart-c6f18de4-0375-44bd-816b-a89f63e0f538
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312012488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.2312012488
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.3335258042
Short name T239
Test name
Test status
Simulation time 524811269561 ps
CPU time 98.55 seconds
Started Jul 21 05:46:05 PM PDT 24
Finished Jul 21 05:47:44 PM PDT 24
Peak memory 201804 kb
Host smart-cc2b4582-c0bf-4d24-a3fb-bfeab69472fd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335258042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gat
ing.3335258042
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.5761226
Short name T277
Test name
Test status
Simulation time 509673352329 ps
CPU time 1092.27 seconds
Started Jul 21 05:46:05 PM PDT 24
Finished Jul 21 06:04:18 PM PDT 24
Peak memory 201720 kb
Host smart-4d93443d-044a-40fd-942e-d2127aadca55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5761226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.5761226
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.3496603016
Short name T366
Test name
Test status
Simulation time 329841206827 ps
CPU time 220.61 seconds
Started Jul 21 05:45:57 PM PDT 24
Finished Jul 21 05:49:38 PM PDT 24
Peak memory 201660 kb
Host smart-b1d2ccfa-ac4e-4d1f-b58d-841edd5ae076
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496603016 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interru
pt_fixed.3496603016
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.551659384
Short name T440
Test name
Test status
Simulation time 161830694617 ps
CPU time 345.99 seconds
Started Jul 21 05:45:52 PM PDT 24
Finished Jul 21 05:51:38 PM PDT 24
Peak memory 201812 kb
Host smart-0464a85c-3e31-4606-b94c-2f0d4b1abecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551659384 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.551659384
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.1688684582
Short name T781
Test name
Test status
Simulation time 159529271424 ps
CPU time 377.61 seconds
Started Jul 21 05:45:52 PM PDT 24
Finished Jul 21 05:52:09 PM PDT 24
Peak memory 201796 kb
Host smart-24d0bc81-bc1c-4851-8b42-21a99f6c3fd7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688684582 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fix
ed.1688684582
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.2374317593
Short name T126
Test name
Test status
Simulation time 442873440602 ps
CPU time 1105.1 seconds
Started Jul 21 05:45:58 PM PDT 24
Finished Jul 21 06:04:24 PM PDT 24
Peak memory 201756 kb
Host smart-cc53dad3-ab10-43ef-bc52-ba9dc1c08e7f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374317593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters
_wakeup.2374317593
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.2393114727
Short name T502
Test name
Test status
Simulation time 605557926060 ps
CPU time 1426.73 seconds
Started Jul 21 05:46:10 PM PDT 24
Finished Jul 21 06:09:57 PM PDT 24
Peak memory 201632 kb
Host smart-deb51ef5-6f39-4d8a-91dc-69a0bfc54801
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393114727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.adc_ctrl_filters_wakeup_fixed.2393114727
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.3843175527
Short name T91
Test name
Test status
Simulation time 28691290110 ps
CPU time 16.76 seconds
Started Jul 21 05:46:04 PM PDT 24
Finished Jul 21 05:46:21 PM PDT 24
Peak memory 201584 kb
Host smart-92142343-72aa-477b-9d99-96d25b4beaf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843175527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.3843175527
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.2796402188
Short name T385
Test name
Test status
Simulation time 3535369686 ps
CPU time 8.65 seconds
Started Jul 21 05:46:04 PM PDT 24
Finished Jul 21 05:46:13 PM PDT 24
Peak memory 201664 kb
Host smart-625b25b3-4670-472c-bb88-679b153b2355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796402188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.2796402188
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.2949707025
Short name T435
Test name
Test status
Simulation time 6246442622 ps
CPU time 9.39 seconds
Started Jul 21 05:45:52 PM PDT 24
Finished Jul 21 05:46:02 PM PDT 24
Peak memory 201604 kb
Host smart-85f15a4a-d711-42a7-965d-5a6ec93a7173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949707025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.2949707025
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.1552649721
Short name T325
Test name
Test status
Simulation time 647025374529 ps
CPU time 254.59 seconds
Started Jul 21 05:46:10 PM PDT 24
Finished Jul 21 05:50:25 PM PDT 24
Peak memory 201668 kb
Host smart-1785d239-0522-4a87-9034-b1d5bf9b0b4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552649721 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all
.1552649721
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.3002919751
Short name T756
Test name
Test status
Simulation time 88531839736 ps
CPU time 218.22 seconds
Started Jul 21 05:46:04 PM PDT 24
Finished Jul 21 05:49:42 PM PDT 24
Peak memory 211452 kb
Host smart-56034f31-2017-4438-a8af-7caa84db11cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002919751 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.3002919751
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.2760833303
Short name T723
Test name
Test status
Simulation time 361950754 ps
CPU time 1.03 seconds
Started Jul 21 05:40:19 PM PDT 24
Finished Jul 21 05:40:21 PM PDT 24
Peak memory 201436 kb
Host smart-f3cc011f-44ab-48ed-aea3-aa21c6c53fa3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760833303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.2760833303
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.4160911989
Short name T203
Test name
Test status
Simulation time 163056004158 ps
CPU time 351.25 seconds
Started Jul 21 05:40:18 PM PDT 24
Finished Jul 21 05:46:10 PM PDT 24
Peak memory 201776 kb
Host smart-d2f66445-2ed7-42a6-ae75-c74bf2970f8c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160911989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gati
ng.4160911989
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.1797347207
Short name T716
Test name
Test status
Simulation time 510268568226 ps
CPU time 633.84 seconds
Started Jul 21 05:40:18 PM PDT 24
Finished Jul 21 05:50:52 PM PDT 24
Peak memory 201764 kb
Host smart-943436c5-ad45-46d3-9065-c3f6167f384a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797347207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.1797347207
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.3502689186
Short name T759
Test name
Test status
Simulation time 333059309355 ps
CPU time 689.88 seconds
Started Jul 21 05:40:19 PM PDT 24
Finished Jul 21 05:51:55 PM PDT 24
Peak memory 201744 kb
Host smart-494f113c-87d3-41a6-915d-e1e6feffce89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502689186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.3502689186
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.522054592
Short name T407
Test name
Test status
Simulation time 498090469158 ps
CPU time 617.09 seconds
Started Jul 21 05:40:21 PM PDT 24
Finished Jul 21 05:50:39 PM PDT 24
Peak memory 201620 kb
Host smart-670942a6-f8c2-48ea-973b-c4424c75b9f2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=522054592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt
_fixed.522054592
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.2432586035
Short name T220
Test name
Test status
Simulation time 328857805568 ps
CPU time 339.06 seconds
Started Jul 21 05:40:20 PM PDT 24
Finished Jul 21 05:46:00 PM PDT 24
Peak memory 201624 kb
Host smart-98f5b43e-557b-4be4-925b-0c8cb5150986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432586035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.2432586035
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.330820788
Short name T705
Test name
Test status
Simulation time 486096589057 ps
CPU time 1045.57 seconds
Started Jul 21 05:40:16 PM PDT 24
Finished Jul 21 05:57:43 PM PDT 24
Peak memory 201752 kb
Host smart-89d6e285-26a9-4d1c-9572-566d02c0dee1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=330820788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixed
.330820788
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.4281863844
Short name T284
Test name
Test status
Simulation time 630324516615 ps
CPU time 321.26 seconds
Started Jul 21 05:40:15 PM PDT 24
Finished Jul 21 05:45:37 PM PDT 24
Peak memory 201744 kb
Host smart-affcfde0-631b-441c-ad97-1c0f67f00ed0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281863844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_
wakeup.4281863844
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.2975766798
Short name T740
Test name
Test status
Simulation time 616322379680 ps
CPU time 340.26 seconds
Started Jul 21 05:40:16 PM PDT 24
Finished Jul 21 05:45:57 PM PDT 24
Peak memory 201748 kb
Host smart-e4c53929-c93c-473b-bd1e-38d114f61c8b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975766798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
adc_ctrl_filters_wakeup_fixed.2975766798
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.3346595555
Short name T334
Test name
Test status
Simulation time 85337646182 ps
CPU time 343.23 seconds
Started Jul 21 05:40:16 PM PDT 24
Finished Jul 21 05:46:00 PM PDT 24
Peak memory 202080 kb
Host smart-840e4845-5a2d-4180-9939-a8751a96f539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346595555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.3346595555
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.3798712777
Short name T779
Test name
Test status
Simulation time 38311801409 ps
CPU time 91.48 seconds
Started Jul 21 05:40:19 PM PDT 24
Finished Jul 21 05:41:51 PM PDT 24
Peak memory 201608 kb
Host smart-c39614e7-7245-4b42-9a50-5d4c3b0e6a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798712777 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.3798712777
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.2798052800
Short name T590
Test name
Test status
Simulation time 5514742962 ps
CPU time 11.35 seconds
Started Jul 21 05:40:19 PM PDT 24
Finished Jul 21 05:40:31 PM PDT 24
Peak memory 201604 kb
Host smart-743d9a99-288d-4811-9392-57f12d28b7a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798052800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.2798052800
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.3869938743
Short name T429
Test name
Test status
Simulation time 5857903290 ps
CPU time 7.53 seconds
Started Jul 21 05:40:21 PM PDT 24
Finished Jul 21 05:40:30 PM PDT 24
Peak memory 201424 kb
Host smart-e0630774-d273-4fe8-96f6-cc255e35fb53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869938743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.3869938743
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.1647121319
Short name T317
Test name
Test status
Simulation time 499229135790 ps
CPU time 1192.84 seconds
Started Jul 21 05:40:18 PM PDT 24
Finished Jul 21 06:00:12 PM PDT 24
Peak memory 201744 kb
Host smart-0ec01cf3-43cd-4438-a78d-757fe05cc0b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647121319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.
1647121319
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.2100531979
Short name T168
Test name
Test status
Simulation time 43804440682 ps
CPU time 16.06 seconds
Started Jul 21 05:40:17 PM PDT 24
Finished Jul 21 05:40:34 PM PDT 24
Peak memory 201932 kb
Host smart-7caf815d-d7b2-4397-972d-384f112cc5a2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100531979 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.2100531979
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.3362969810
Short name T683
Test name
Test status
Simulation time 531019638 ps
CPU time 1.9 seconds
Started Jul 21 05:40:18 PM PDT 24
Finished Jul 21 05:40:20 PM PDT 24
Peak memory 201488 kb
Host smart-073db837-0104-465a-b0cd-7bce37fe3ead
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362969810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.3362969810
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.2695455702
Short name T288
Test name
Test status
Simulation time 509531240298 ps
CPU time 201.85 seconds
Started Jul 21 05:40:15 PM PDT 24
Finished Jul 21 05:43:38 PM PDT 24
Peak memory 201672 kb
Host smart-e912420a-9846-48d6-8e91-611fc44d0b24
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695455702 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gati
ng.2695455702
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.494712827
Short name T255
Test name
Test status
Simulation time 498041732267 ps
CPU time 1062.26 seconds
Started Jul 21 05:40:15 PM PDT 24
Finished Jul 21 05:57:58 PM PDT 24
Peak memory 201728 kb
Host smart-24e1fbdc-29a3-4e38-aacf-b84362ebf2b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494712827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.494712827
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.2488900131
Short name T230
Test name
Test status
Simulation time 484408793072 ps
CPU time 275.93 seconds
Started Jul 21 05:40:16 PM PDT 24
Finished Jul 21 05:44:53 PM PDT 24
Peak memory 201744 kb
Host smart-57769790-d75a-446b-8cb1-1c6de911bde4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488900131 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.2488900131
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.3988031176
Short name T447
Test name
Test status
Simulation time 163873170290 ps
CPU time 170 seconds
Started Jul 21 05:40:26 PM PDT 24
Finished Jul 21 05:43:17 PM PDT 24
Peak memory 201612 kb
Host smart-352eac59-0a3a-46a4-bede-50f895944b0f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988031176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrup
t_fixed.3988031176
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.4236375087
Short name T641
Test name
Test status
Simulation time 491757824285 ps
CPU time 115.72 seconds
Started Jul 21 05:40:24 PM PDT 24
Finished Jul 21 05:42:20 PM PDT 24
Peak memory 201748 kb
Host smart-051b6957-d6f8-4cd3-99be-9dcbcb93561d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236375087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.4236375087
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.4211077930
Short name T156
Test name
Test status
Simulation time 488530713874 ps
CPU time 1088.1 seconds
Started Jul 21 05:40:21 PM PDT 24
Finished Jul 21 05:58:30 PM PDT 24
Peak memory 201624 kb
Host smart-52a4ef32-d482-4f34-a2f2-7296e3dc2123
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211077930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixe
d.4211077930
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.3999753714
Short name T701
Test name
Test status
Simulation time 189559288723 ps
CPU time 148.42 seconds
Started Jul 21 05:40:17 PM PDT 24
Finished Jul 21 05:42:46 PM PDT 24
Peak memory 201748 kb
Host smart-8fe51c78-9068-4e01-9641-30db8e823c3e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999753714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_
wakeup.3999753714
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.2238176330
Short name T359
Test name
Test status
Simulation time 590976884099 ps
CPU time 1366.42 seconds
Started Jul 21 05:40:14 PM PDT 24
Finished Jul 21 06:03:01 PM PDT 24
Peak memory 201616 kb
Host smart-eb1bde1c-90b2-4c3a-94c1-65b610875b53
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238176330 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
adc_ctrl_filters_wakeup_fixed.2238176330
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.3708411627
Short name T169
Test name
Test status
Simulation time 122236410766 ps
CPU time 653.67 seconds
Started Jul 21 05:40:15 PM PDT 24
Finished Jul 21 05:51:10 PM PDT 24
Peak memory 202104 kb
Host smart-f6b5c94e-8019-4168-9115-f25f0ac25b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708411627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.3708411627
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.2780398227
Short name T585
Test name
Test status
Simulation time 31884908197 ps
CPU time 70.85 seconds
Started Jul 21 05:40:17 PM PDT 24
Finished Jul 21 05:41:28 PM PDT 24
Peak memory 201664 kb
Host smart-f03d9671-0c08-4de1-9b6b-18615d133489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780398227 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.2780398227
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.462943387
Short name T356
Test name
Test status
Simulation time 5066930282 ps
CPU time 2.8 seconds
Started Jul 21 05:40:19 PM PDT 24
Finished Jul 21 05:40:23 PM PDT 24
Peak memory 201608 kb
Host smart-2df60b94-b4e0-4a6b-8332-118b585501e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462943387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.462943387
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.3220758505
Short name T361
Test name
Test status
Simulation time 6079243514 ps
CPU time 16.31 seconds
Started Jul 21 05:40:17 PM PDT 24
Finished Jul 21 05:40:34 PM PDT 24
Peak memory 201608 kb
Host smart-d701807f-412f-48fa-a8f0-edaa0029b034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220758505 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.3220758505
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.1855921489
Short name T332
Test name
Test status
Simulation time 174317056939 ps
CPU time 71.28 seconds
Started Jul 21 05:40:19 PM PDT 24
Finished Jul 21 05:41:31 PM PDT 24
Peak memory 201720 kb
Host smart-72e7f144-548a-425f-9da0-353c2bbbd835
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855921489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.
1855921489
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.854689541
Short name T738
Test name
Test status
Simulation time 72246680531 ps
CPU time 130.47 seconds
Started Jul 21 05:40:16 PM PDT 24
Finished Jul 21 05:42:27 PM PDT 24
Peak memory 210376 kb
Host smart-407748ad-ae0c-4c5a-abef-82f7f9279391
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854689541 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.854689541
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.3609118699
Short name T509
Test name
Test status
Simulation time 394465148 ps
CPU time 0.69 seconds
Started Jul 21 05:40:20 PM PDT 24
Finished Jul 21 05:40:22 PM PDT 24
Peak memory 201536 kb
Host smart-4d56c9d0-c408-4858-80e3-9e49eb136551
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609118699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.3609118699
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.1313345298
Short name T164
Test name
Test status
Simulation time 366094918209 ps
CPU time 96.11 seconds
Started Jul 21 05:40:21 PM PDT 24
Finished Jul 21 05:41:58 PM PDT 24
Peak memory 201476 kb
Host smart-3e2abdde-83dd-420a-bdf2-407e30bd5f8c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313345298 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gati
ng.1313345298
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.3186041912
Short name T663
Test name
Test status
Simulation time 501525649332 ps
CPU time 1061.61 seconds
Started Jul 21 05:40:20 PM PDT 24
Finished Jul 21 05:58:03 PM PDT 24
Peak memory 201604 kb
Host smart-f2afdd3e-0728-4d09-b0a6-07b88232d490
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186041912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrup
t_fixed.3186041912
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.717403255
Short name T497
Test name
Test status
Simulation time 328752189250 ps
CPU time 402.27 seconds
Started Jul 21 05:40:19 PM PDT 24
Finished Jul 21 05:47:02 PM PDT 24
Peak memory 201668 kb
Host smart-bff1f4b0-26a3-43ad-bc59-beae96e467cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717403255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.717403255
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.3618489051
Short name T741
Test name
Test status
Simulation time 331187048386 ps
CPU time 358.38 seconds
Started Jul 21 05:40:15 PM PDT 24
Finished Jul 21 05:46:14 PM PDT 24
Peak memory 201624 kb
Host smart-4cc5eccb-d52b-4559-9596-e2aa2e4adbb1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618489051 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixe
d.3618489051
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.3586938719
Short name T210
Test name
Test status
Simulation time 596820760441 ps
CPU time 729.83 seconds
Started Jul 21 05:40:19 PM PDT 24
Finished Jul 21 05:52:30 PM PDT 24
Peak memory 201812 kb
Host smart-cac208e7-66c3-48aa-9a09-c10b726085ec
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586938719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_
wakeup.3586938719
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.4020027570
Short name T569
Test name
Test status
Simulation time 611258619664 ps
CPU time 356.82 seconds
Started Jul 21 05:40:17 PM PDT 24
Finished Jul 21 05:46:14 PM PDT 24
Peak memory 201740 kb
Host smart-8acb1897-a8f4-43b9-bc4f-91c9830f4176
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020027570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
adc_ctrl_filters_wakeup_fixed.4020027570
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.3841444632
Short name T607
Test name
Test status
Simulation time 67632111232 ps
CPU time 279.19 seconds
Started Jul 21 05:40:17 PM PDT 24
Finished Jul 21 05:44:57 PM PDT 24
Peak memory 202036 kb
Host smart-f3db86bd-c669-4be9-a40f-ceaf342ef843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841444632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.3841444632
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.2260769275
Short name T746
Test name
Test status
Simulation time 23558201193 ps
CPU time 13.12 seconds
Started Jul 21 05:40:19 PM PDT 24
Finished Jul 21 05:40:33 PM PDT 24
Peak memory 201588 kb
Host smart-cdbbe5b4-55d0-4573-aa56-a353128284a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260769275 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.2260769275
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.627155872
Short name T543
Test name
Test status
Simulation time 3928605622 ps
CPU time 4.64 seconds
Started Jul 21 05:40:19 PM PDT 24
Finished Jul 21 05:40:25 PM PDT 24
Peak memory 201476 kb
Host smart-4f55f685-1ed0-40a4-b165-03f844ba365e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627155872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.627155872
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.3265824009
Short name T456
Test name
Test status
Simulation time 5717737074 ps
CPU time 13.83 seconds
Started Jul 21 05:40:14 PM PDT 24
Finished Jul 21 05:40:28 PM PDT 24
Peak memory 201588 kb
Host smart-8031d51a-9337-40ef-a809-784441a5f24f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265824009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.3265824009
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.1548532209
Short name T310
Test name
Test status
Simulation time 200302894281 ps
CPU time 461.03 seconds
Started Jul 21 05:40:18 PM PDT 24
Finished Jul 21 05:47:59 PM PDT 24
Peak memory 201784 kb
Host smart-572ef0d2-9ad2-406b-b134-f72ac1a95c28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548532209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.
1548532209
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.492680934
Short name T671
Test name
Test status
Simulation time 235410568062 ps
CPU time 129.08 seconds
Started Jul 21 05:40:27 PM PDT 24
Finished Jul 21 05:42:36 PM PDT 24
Peak memory 212104 kb
Host smart-4e73ac3e-f1d6-4b8a-a808-5f56f91efc27
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492680934 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.492680934
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.2940242429
Short name T665
Test name
Test status
Simulation time 479463103 ps
CPU time 0.87 seconds
Started Jul 21 05:40:26 PM PDT 24
Finished Jul 21 05:40:28 PM PDT 24
Peak memory 201528 kb
Host smart-b0816ca9-36d8-40d8-a19d-91c4c8cc21aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940242429 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.2940242429
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.1872248883
Short name T661
Test name
Test status
Simulation time 382177058406 ps
CPU time 876.25 seconds
Started Jul 21 05:40:24 PM PDT 24
Finished Jul 21 05:55:01 PM PDT 24
Peak memory 201756 kb
Host smart-9c1d0eca-95e9-4371-9ee6-5d00705de4e0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872248883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gati
ng.1872248883
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.770738492
Short name T260
Test name
Test status
Simulation time 160396717575 ps
CPU time 101.84 seconds
Started Jul 21 05:40:18 PM PDT 24
Finished Jul 21 05:42:01 PM PDT 24
Peak memory 201724 kb
Host smart-bb393930-c57a-4141-9cff-8e9b33529aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770738492 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.770738492
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.1445068125
Short name T411
Test name
Test status
Simulation time 325909379579 ps
CPU time 695.82 seconds
Started Jul 21 05:40:21 PM PDT 24
Finished Jul 21 05:51:58 PM PDT 24
Peak memory 201356 kb
Host smart-97af60de-f67b-4c83-b052-eb4753662ea1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445068125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrup
t_fixed.1445068125
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.3728843230
Short name T166
Test name
Test status
Simulation time 324433908745 ps
CPU time 214.08 seconds
Started Jul 21 05:40:20 PM PDT 24
Finished Jul 21 05:43:55 PM PDT 24
Peak memory 201688 kb
Host smart-c3b8af81-2304-43a0-b5b8-9edcf555d20f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728843230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.3728843230
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.1247624253
Short name T470
Test name
Test status
Simulation time 491859386733 ps
CPU time 520.51 seconds
Started Jul 21 05:40:19 PM PDT 24
Finished Jul 21 05:49:00 PM PDT 24
Peak memory 201732 kb
Host smart-3f8094e9-3a87-470d-8b17-e593b6a0504a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247624253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixe
d.1247624253
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.932901188
Short name T622
Test name
Test status
Simulation time 404600766656 ps
CPU time 903.74 seconds
Started Jul 21 05:40:19 PM PDT 24
Finished Jul 21 05:55:24 PM PDT 24
Peak memory 201672 kb
Host smart-53ac999f-883a-4248-b846-31719af35491
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932901188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.a
dc_ctrl_filters_wakeup_fixed.932901188
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.2799094390
Short name T751
Test name
Test status
Simulation time 121951164448 ps
CPU time 356.07 seconds
Started Jul 21 05:40:16 PM PDT 24
Finished Jul 21 05:46:13 PM PDT 24
Peak memory 202148 kb
Host smart-c24ab33b-f715-4eb0-98c7-6728b0d5ad2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799094390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.2799094390
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.1905395769
Short name T627
Test name
Test status
Simulation time 40103927486 ps
CPU time 17.9 seconds
Started Jul 21 05:40:19 PM PDT 24
Finished Jul 21 05:40:37 PM PDT 24
Peak memory 201604 kb
Host smart-77c493e3-580a-4ae9-b7f4-be8aa9debb7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905395769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.1905395769
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.4260555658
Short name T687
Test name
Test status
Simulation time 5662152630 ps
CPU time 8.4 seconds
Started Jul 21 05:40:20 PM PDT 24
Finished Jul 21 05:40:30 PM PDT 24
Peak memory 201492 kb
Host smart-a2d2544f-ec54-46d8-8138-486c09f333cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260555658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.4260555658
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.2962614223
Short name T713
Test name
Test status
Simulation time 6002284732 ps
CPU time 15.09 seconds
Started Jul 21 05:40:18 PM PDT 24
Finished Jul 21 05:40:33 PM PDT 24
Peak memory 201476 kb
Host smart-2f5a6eba-31a9-415b-b888-4a1b265756b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962614223 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.2962614223
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.3879828733
Short name T714
Test name
Test status
Simulation time 158862106107 ps
CPU time 346.27 seconds
Started Jul 21 05:40:28 PM PDT 24
Finished Jul 21 05:46:15 PM PDT 24
Peak memory 210492 kb
Host smart-6eadf217-6f96-4764-afa2-0aad11729579
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879828733 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.3879828733
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.1988781681
Short name T515
Test name
Test status
Simulation time 323658394 ps
CPU time 0.82 seconds
Started Jul 21 05:40:25 PM PDT 24
Finished Jul 21 05:40:26 PM PDT 24
Peak memory 201552 kb
Host smart-027e8d0b-3062-4c84-ba4b-5cd50b9f448b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988781681 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.1988781681
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.3845745363
Short name T264
Test name
Test status
Simulation time 528238646982 ps
CPU time 299.2 seconds
Started Jul 21 05:40:41 PM PDT 24
Finished Jul 21 05:45:41 PM PDT 24
Peak memory 201724 kb
Host smart-ad0b5a1e-6aae-4267-87df-d8b937a4df00
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845745363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gati
ng.3845745363
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.1044195561
Short name T132
Test name
Test status
Simulation time 168674198262 ps
CPU time 386.76 seconds
Started Jul 21 05:40:24 PM PDT 24
Finished Jul 21 05:46:52 PM PDT 24
Peak memory 201560 kb
Host smart-db1ce3cf-ef52-4fa6-b7eb-d6a3867a75ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044195561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.1044195561
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.3083378241
Short name T637
Test name
Test status
Simulation time 161925053189 ps
CPU time 107.5 seconds
Started Jul 21 05:40:24 PM PDT 24
Finished Jul 21 05:42:12 PM PDT 24
Peak memory 201696 kb
Host smart-8ec5bd90-5bc1-41b0-b413-fc3bd9a1cd26
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083378241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrup
t_fixed.3083378241
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.954071190
Short name T294
Test name
Test status
Simulation time 330893089963 ps
CPU time 801.82 seconds
Started Jul 21 05:40:45 PM PDT 24
Finished Jul 21 05:54:07 PM PDT 24
Peak memory 201740 kb
Host smart-d6de1ce8-076d-4ac2-afb4-c58f89242ba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954071190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.954071190
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.2863967313
Short name T381
Test name
Test status
Simulation time 326872010633 ps
CPU time 794.85 seconds
Started Jul 21 05:40:26 PM PDT 24
Finished Jul 21 05:53:42 PM PDT 24
Peak memory 201668 kb
Host smart-8ef75fb0-c75e-4bb6-9af4-82932db75b1b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863967313 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixe
d.2863967313
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.2036577855
Short name T642
Test name
Test status
Simulation time 196087663749 ps
CPU time 115.41 seconds
Started Jul 21 05:40:41 PM PDT 24
Finished Jul 21 05:42:37 PM PDT 24
Peak memory 201792 kb
Host smart-acf95ed6-5bb0-4a21-9956-00b806d12594
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036577855 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_
wakeup.2036577855
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.1630243533
Short name T594
Test name
Test status
Simulation time 597607663516 ps
CPU time 729.49 seconds
Started Jul 21 05:40:26 PM PDT 24
Finished Jul 21 05:52:36 PM PDT 24
Peak memory 201548 kb
Host smart-1da51ba9-e631-4310-8b05-34d366ea60d5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630243533 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
adc_ctrl_filters_wakeup_fixed.1630243533
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.3032427731
Short name T555
Test name
Test status
Simulation time 82552440604 ps
CPU time 238.15 seconds
Started Jul 21 05:40:26 PM PDT 24
Finished Jul 21 05:44:25 PM PDT 24
Peak memory 202000 kb
Host smart-7016e176-6f08-4725-874e-be086bfe30df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032427731 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.3032427731
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.2268349058
Short name T345
Test name
Test status
Simulation time 33334558481 ps
CPU time 76.79 seconds
Started Jul 21 05:40:27 PM PDT 24
Finished Jul 21 05:41:45 PM PDT 24
Peak memory 201604 kb
Host smart-100eb04b-6099-4879-8554-4ebf3b3346d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268349058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.2268349058
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.3147435988
Short name T542
Test name
Test status
Simulation time 2922172262 ps
CPU time 1.03 seconds
Started Jul 21 05:40:29 PM PDT 24
Finished Jul 21 05:40:32 PM PDT 24
Peak memory 201420 kb
Host smart-4fd1b84a-fb3f-4f4a-85ab-355eb682cada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147435988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.3147435988
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.2255157628
Short name T608
Test name
Test status
Simulation time 5974421712 ps
CPU time 8.1 seconds
Started Jul 21 05:40:22 PM PDT 24
Finished Jul 21 05:40:31 PM PDT 24
Peak memory 201608 kb
Host smart-f8289240-d60f-4b59-8e79-6fa40205e167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255157628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.2255157628
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.832082988
Short name T330
Test name
Test status
Simulation time 187080269739 ps
CPU time 109.36 seconds
Started Jul 21 05:40:21 PM PDT 24
Finished Jul 21 05:42:12 PM PDT 24
Peak memory 201636 kb
Host smart-735f84fb-ec8d-41fc-b3d9-ab065efdd180
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832082988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.832082988
Directory /workspace/9.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.4200450620
Short name T20
Test name
Test status
Simulation time 17411932256 ps
CPU time 37.88 seconds
Started Jul 21 05:40:22 PM PDT 24
Finished Jul 21 05:41:00 PM PDT 24
Peak memory 210432 kb
Host smart-fc7ba40c-261e-4b03-80a2-dcb4dca0052b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200450620 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.4200450620
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%