Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	7175	1			T1	35		T8	12		T9	57
testmodes[AdcCtrlTestmodeNormal]	5325	1			T1	19		T2	3		T3	2
testmodes[AdcCtrlTestmodeLowpower]	5552	1			T1	4		T8	16		T9	16
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	4079	1			T1	27		T8	10		T9	43
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1670	1			T1	8		T8	2		T9	12
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1313	1			T9	2		T39	19		T40	19
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1707	1			T1	7		T8	2		T9	10
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	1983	1			T1	8		T2	2		T3	1
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1300	1			T1	3		T8	1		T9	3
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1262	1			T1	1		T9	4		T39	22
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1325	1			T1	3		T9	1		T39	13
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2714	1			T8	15		T9	10		T10	18