Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26488

1

T1

71

T2

27

T3

13

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22508

1

T1

62

T2

27

T5

3

auto[ADC_CTRL_FILTER_COND_OUT]

3980

1

T1

9

T3

13

T4

24

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20457

1

T1

67

T3

12

T8

44

auto[1]

6031

1

T1

4

T2

27

T3

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22243

1

T1

61

T2

3

T3

2

auto[1]

4245

1

T1

10

T2

24

T3

11

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	28	1			T160	12		T222	16		-	-
values[0]	96	1			T155	15		T223	13		T224	9
values[1]	809	1			T81	11		T27	18		T36	3
values[2]	677	1			T127	1		T165	20		T137	1
values[3]	604	1			T7	1		T37	9		T129	14
values[4]	690	1			T1	9		T7	1		T8	13
values[5]	3183	1			T1	4		T2	27		T4	24
values[6]	760	1			T3	12		T29	12		T37	5
values[7]	665	1			T6	1		T7	1		T8	1
values[8]	677	1			T9	18		T12	5		T168	1
values[9]	1166	1			T3	1		T30	3		T125	24
minimum	17133	1			T1	58		T8	31		T9	95

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	867	1			T81	11		T27	18		T36	3
values[1]	766	1			T165	20		T137	1		T24	24
values[2]	756	1			T1	9		T8	13		T81	1
values[3]	2945	1			T2	27		T5	3		T7	2
values[4]	906	1			T1	4		T4	24		T81	7
values[5]	635	1			T6	1		T7	1		T8	1
values[6]	697	1			T3	12		T9	18		T29	12
values[7]	640	1			T12	5		T125	17		T225	9
values[8]	943	1			T3	1		T30	3		T125	13
values[9]	178	1			T125	11		T138	11		T142	10
minimum	17155	1			T1	58		T8	31		T9	95

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22297

1

T1

68

T2

27

T3

13

auto[1]

4191

1

T1

3

T9

5

T29

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T36	3		T128	24		T129	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T81	1		T27	8		T127	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T226	12		T227	1		T14	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T165	10		T137	1		T24	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T8	1		T12	1		T37	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T1	4		T81	1		T143	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1607	1			T2	3		T5	3		T11	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T7	2		T27	2		T168	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T1	4		T38	11		T154	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T4	2		T81	1		T165	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T7	1		T8	1		T31	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T6	1		T37	5		T228	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T9	9		T29	12		T35	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T3	1		T9	3		T12	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T12	3		T125	17		T225	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T23	1		T165	5		T25	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T130	3		T146	14		T132	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T3	1		T30	2		T125	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T125	11		T138	1		T142	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T132	1		T229	1		T230	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17004	1			T1	53		T8	31		T9	94
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T129	15		T25	1		T139	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T81	10		T27	10		T33	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T14	2		T17	3		T100	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T165	10		T24	12		T145	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T8	12		T129	9		T231	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T1	5		T13	1		T232	26
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	921	1			T2	24		T11	31		T233	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T27	1		T154	10		T131	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T38	19		T154	12		T142	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T4	22		T81	6		T165	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T31	1		T144	8		T131	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T228	14		T146	9		T174	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T9	3		T35	17		T234	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T3	11		T9	3		T12	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T12	2		T139	4		T171	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T165	4		T231	2		T175	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T146	22		T132	3		T26	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T30	1		T141	18		T24	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T138	10		T142	5		T235	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T132	18		T222	2		T188	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T1	5		T9	1		T27	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T160	1		T222	14		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T155	1		T223	1		T236	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T224	1		T237	14		T238	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T36	3		T128	24		T129	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T81	1		T27	8		T130	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T25	1		T226	12		T139	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T127	1		T165	10		T137	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T37	9		T129	5		T239	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T7	1		T143	1		T34	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T8	1		T12	1		T30	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T1	4		T7	1		T81	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1720	1			T1	4		T2	3		T5	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T4	2		T81	1		T168	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T29	12		T38	11		T142	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T3	1		T37	5		T228	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T7	1		T8	1		T35	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T6	1		T12	7		T141	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T9	9		T12	3		T125	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T9	3		T168	1		T23	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	362	1			T125	11		T225	9		T138	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T3	1		T30	2		T125	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16992	1			T1	53		T8	31		T9	94
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T160	11		T222	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T155	14		T223	12		T240	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T224	8		T237	16		T238	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T129	15		T175	13		T241	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T81	10		T27	10		T33	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T25	1		T139	4		T14	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T165	10		T24	12		T145	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T129	9		T239	11		T242	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T232	26		T14	2		T176	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T8	12		T154	12		T144	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T1	5		T27	1		T154	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1034	1			T2	24		T11	31		T233	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T4	22		T81	6		T165	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T38	19		T142	8		T31	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T3	11		T228	14		T146	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T35	17		T234	6		T144	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T12	8		T141	12		T243	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T9	3		T12	2		T139	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T9	3		T142	9		T231	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T138	10		T142	5		T146	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T30	1		T165	4		T141	18
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T1	5		T9	1		T27	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T36	1		T128	1		T129	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T81	11		T27	11		T127	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T226	1		T227	1		T14	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T165	11		T137	1		T24	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T8	13		T12	1		T37	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	327	1			T1	8		T81	1		T143	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1266	1			T2	27		T5	3		T11	34
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T7	2		T27	2		T168	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T1	2		T38	20		T154	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T4	24		T81	7		T165	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T7	1		T8	1		T31	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T6	1		T37	1		T228	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T9	9		T29	1		T35	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T3	12		T9	4		T12	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T12	4		T125	1		T225	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T23	1		T165	5		T25	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T130	1		T146	24		T132	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T3	1		T30	2		T125	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T125	1		T138	11		T142	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T132	19		T229	1		T230	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17146	1			T1	58		T8	31		T9	95
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T36	2		T128	23		T129	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T27	7		T130	13		T33	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T226	11		T14	2		T241	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T165	9		T24	11		T244	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T37	8		T129	4		T231	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T1	1		T13	1		T34	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1262	1			T126	25		T129	10		T152	23
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T27	1		T154	11		T131	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T1	2		T38	10		T154	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T165	6		T175	12		T32	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T31	1		T131	3		T132	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T37	4		T228	11		T245	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T9	3		T29	11		T35	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T9	2		T12	2		T141	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T12	1		T125	16		T225	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T165	4		T231	10		T184	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T130	2		T146	12		T132	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T30	1		T125	12		T141	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T125	10		T142	4		T246	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T230	8		T73	14		T195	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T241	6		T240	3		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T160	12		T222	3		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T155	15		T223	13		T236	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T224	9		T237	17		T238	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T36	1		T128	1		T129	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T81	11		T27	11		T130	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T25	2		T226	1		T139	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T127	1		T165	11		T137	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T37	1		T129	10		T239	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T7	1		T143	1		T34	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T8	13		T12	1		T30	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T1	8		T7	1		T81	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1388	1			T1	2		T2	27		T5	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T4	24		T81	7		T168	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T29	1		T38	20		T142	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T3	12		T37	1		T228	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T7	1		T8	1		T35	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T6	1		T12	13		T141	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T9	9		T12	4		T125	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T9	4		T168	1		T23	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	333	1			T125	1		T225	1		T138	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	316	1			T3	1		T30	2		T125	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17133	1			T1	58		T8	31		T9	95
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T222	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T240	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T237	13		T238	6		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T36	2		T128	23		T129	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T27	7		T130	13		T33	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T226	11		T14	2		T177	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T165	9		T24	11		T244	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T37	8		T129	4		T239	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T34	2		T14	1		T247	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T154	12		T231	2		T98	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T1	1		T27	1		T154	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1366	1			T1	2		T126	25		T129	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T165	6		T155	11		T32	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T29	11		T38	10		T142	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T37	4		T228	11		T146	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T35	14		T234	7		T245	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T12	2		T141	10		T245	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T9	3		T12	1		T125	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T9	2		T142	12		T231	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T125	10		T225	8		T130	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T30	1		T125	12		T165	4

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22297

1

T1

68

T2

27

T3

13

auto[1]

auto[0]

4191

1

T1

3

T9

5

T29

11

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26488

1

T1

71

T2

27

T3

13

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22900

1

T1

58

T2

27

T3

1

auto[ADC_CTRL_FILTER_COND_OUT]

3588

1

T1

13

T3

12

T4

24

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20293

1

T1

71

T3

13

T4

10

auto[1]

6195

1

T2

27

T4

14

T5

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22243

1

T1

61

T2

3

T3

2

auto[1]

4245

1

T1

10

T2

24

T3

11

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	12	1			T248	12		-	-		-	-
values[0]	71	1			T174	35		T249	22		T250	14
values[1]	700	1			T4	14		T37	5		T137	1
values[2]	753	1			T6	1		T8	1		T81	11
values[3]	776	1			T8	13		T27	18		T12	15
values[4]	792	1			T7	1		T81	7		T27	3
values[5]	722	1			T1	4		T3	1		T29	12
values[6]	753	1			T7	1		T12	1		T154	22
values[7]	741	1			T9	12		T30	3		T36	3
values[8]	2968	1			T2	27		T4	10		T5	3
values[9]	1067	1			T1	9		T3	12		T7	1
minimum	17133	1			T1	58		T8	31		T9	95

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	892	1			T4	14		T8	1		T37	5
values[1]	844	1			T6	1		T81	11		T168	1
values[2]	771	1			T8	13		T27	18		T35	32
values[3]	843	1			T1	4		T3	1		T7	1
values[4]	631	1			T7	1		T29	12		T12	5
values[5]	769	1			T12	1		T165	9		T154	22
values[6]	3049	1			T2	27		T5	3		T9	12
values[7]	625	1			T9	6		T125	13		T228	26
values[8]	703	1			T1	9		T4	10		T7	1
values[9]	217	1			T3	12		T37	9		T251	1
minimum	17144	1			T1	58		T8	31		T9	95

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22297

1

T1

68

T2

27

T3

13

auto[1]

4191

1

T1

3

T9

5

T29

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T8	1		T24	5		T174	21
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T4	1		T37	5		T127	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T6	1		T81	1		T165	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T168	1		T132	1		T244	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T38	11		T128	24		T154	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T8	1		T27	8		T35	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T3	1		T81	1		T141	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T1	4		T7	1		T27	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T7	1		T29	12		T129	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T12	3		T165	10		T252	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T154	12		T142	11		T139	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T12	1		T165	5		T141	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1721	1			T2	3		T5	3		T9	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T36	3		T142	5		T234	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T23	1		T143	1		T31	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T9	3		T125	13		T228	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T7	1		T130	17		T143	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T1	4		T4	1		T81	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T37	9		T251	1		T32	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T3	1		T163	14		T253	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16992	1			T1	53		T8	31		T9	94
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T254	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T24	10		T174	14		T33	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T4	13		T141	12		T243	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T81	10		T165	8		T142	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T132	18		T32	10		T33	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T38	19		T154	12		T129	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T8	12		T27	10		T35	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	297	1			T81	6		T141	6		T129	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T27	1		T24	12		T231	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T129	10		T172	14		T194	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T12	2		T165	10		T158	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T154	10		T142	8		T139	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T165	4		T141	12		T231	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1062	1			T2	24		T9	3		T11	31
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T142	5		T234	6		T131	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T31	1		T132	11		T32	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T9	3		T228	14		T138	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T186	13		T242	9		T162	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T1	5		T4	9		T139	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T32	14		T255	12		T256	24
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T3	11		T240	9		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T1	5		T9	1		T27	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T254	10		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T248	12		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T174	21		T250	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T249	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T24	5		T33	6		T34	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T4	1		T37	5		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T6	1		T8	1		T81	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T168	1		T127	1		T226	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T38	11		T154	13		T129	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T8	1		T27	8		T12	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T81	1		T128	24		T129	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T7	1		T27	2		T35	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T3	1		T29	12		T141	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T1	4		T12	3		T125	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T7	1		T154	12		T129	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T12	1		T146	13		T147	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T9	9		T30	2		T143	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T36	3		T165	5		T141	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1638	1			T2	3		T5	3		T11	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T4	1		T9	3		T228	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T7	1		T37	9		T23	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	318	1			T1	4		T3	1		T81	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16992	1			T1	53		T8	31		T9	94
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T174	14		T250	13		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T249	21		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T24	10		T33	2		T162	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T4	13		T141	12		T243	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T81	10		T165	8		T142	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T132	18		T32	10		T33	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T38	19		T154	12		T129	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T8	12		T27	10		T12	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T81	6		T129	15		T155	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T27	1		T35	17		T24	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T141	6		T144	8		T184	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T12	2		T165	10		T158	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T154	10		T129	10		T142	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T146	12		T147	8		T257	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T9	3		T30	1		T139	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T165	4		T141	12		T142	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	975	1			T2	24		T11	31		T233	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T4	9		T9	3		T228	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T31	1		T132	8		T32	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T1	5		T3	11		T139	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T1	5		T9	1		T27	2