Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26488

1

T1

71

T2

27

T3

13

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23071

1

T1

67

T2

27

T4

24

auto[ADC_CTRL_FILTER_COND_OUT]

3417

1

T1

4

T3

13

T7

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20143

1

T1

58

T3

1

T7

2

auto[1]

6345

1

T1

13

T2

27

T3

12

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22243

1

T1

61

T2

3

T3

2

auto[1]

4245

1

T1

10

T2

24

T3

11

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	54	1			T259	12		T318	12		T272	29
values[0]	69	1			T319	11		T235	12		T320	12
values[1]	823	1			T3	12		T7	1		T9	6
values[2]	572	1			T8	13		T36	3		T37	5
values[3]	630	1			T3	1		T4	14		T6	1
values[4]	826	1			T1	9		T12	15		T30	3
values[5]	579	1			T1	4		T81	12		T165	20
values[6]	776	1			T4	10		T29	12		T35	32
values[7]	775	1			T7	1		T8	1		T37	9
values[8]	690	1			T12	5		T23	1		T129	14
values[9]	3561	1			T2	27		T5	3		T7	1
minimum	17133	1			T1	58		T8	31		T9	95

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	907	1			T3	12		T27	18		T12	1
values[1]	724	1			T3	1		T6	1		T7	1
values[2]	649	1			T4	14		T81	7		T12	15
values[3]	787	1			T1	13		T81	11		T30	3
values[4]	560	1			T81	1		T141	13		T129	21
values[5]	814	1			T4	10		T29	12		T35	32
values[6]	3158	1			T2	27		T5	3		T7	1
values[7]	736	1			T9	12		T12	5		T228	26
values[8]	793	1			T30	1		T165	15		T129	14
values[9]	207	1			T7	1		T38	30		T142	10
minimum	17153	1			T1	58		T8	31		T9	95

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22297

1

T1

68

T2

27

T3

13

auto[1]

4191

1

T1

3

T9

5

T29

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T27	8		T127	1		T154	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T3	1		T12	1		T141	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T6	1		T9	3		T27	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T3	1		T7	1		T8	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T4	1		T81	1		T127	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T12	7		T36	3		T37	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T1	4		T125	17		T165	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T1	4		T81	1		T30	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T132	5		T13	3		T184	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T81	1		T141	7		T129	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T4	1		T168	1		T128	24
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T29	12		T35	15		T168	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1746	1			T2	3		T5	3		T7	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T154	12		T142	11		T245	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T9	9		T12	3		T228	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T142	13		T139	1		T145	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T30	1		T129	5		T130	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T165	7		T144	1		T133	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T38	11		T142	5		T143	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T7	1		T177	9		T96	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17004	1			T1	53		T8	31		T9	94
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T291	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T27	10		T154	12		T234	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T3	11		T141	12		T25	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T9	3		T27	1		T100	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T8	12		T144	8		T174	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T4	13		T81	6		T165	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T12	8		T175	13		T241	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T1	5		T165	10		T129	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T81	10		T30	1		T155	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T132	3		T13	1		T184	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T141	6		T129	10		T171	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T4	9		T138	10		T24	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T35	17		T147	8		T212	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1039	1			T2	24		T11	31		T233	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T154	10		T142	8		T231	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T9	3		T12	2		T228	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T142	9		T139	4		T145	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T129	9		T31	1		T146	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T165	8		T144	9		T170	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T38	19		T142	5		T162	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T96	1		T264	1		T321	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T1	5		T9	1		T27	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T259	12		T318	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T272	15		T181	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T322	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T319	1		T235	1		T320	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T9	3		T27	8		T127	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T3	1		T7	1		T12	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T292	16		T194	1		T73	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T8	1		T36	3		T37	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T4	1		T6	1		T81	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T3	1		T139	1		T175	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T1	4		T125	17		T127	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T12	7		T30	2		T225	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T165	10		T251	1		T131	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T1	4		T81	2		T141	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T4	1		T168	1		T138	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T29	12		T35	15		T168	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T7	1		T8	1		T37	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T154	12		T142	11		T245	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T12	3		T23	1		T129	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T139	1		T140	1		T145	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1866	1			T2	3		T5	3		T9	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	308	1			T7	1		T165	7		T142	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16992	1			T1	53		T8	31		T9	94
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T318	11		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T272	14		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T319	10		T235	11		T320	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T9	3		T27	10		T154	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T3	11		T25	1		T174	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T292	14		T194	2		T100	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T8	12		T141	12		T144	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T4	13		T81	6		T27	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T175	13		T100	2		T323	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T1	5		T129	15		T144	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T12	8		T30	1		T155	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T165	10		T131	15		T282	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T81	10		T141	6		T129	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T4	9		T138	10		T24	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T35	17		T14	2		T159	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T141	12		T175	8		T282	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T154	10		T142	8		T231	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T12	2		T129	9		T139	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T139	4		T145	7		T175	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1100	1			T2	24		T9	3		T11	31
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T165	8		T142	9		T144	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T1	5		T9	1		T27	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T27	11		T127	1		T154	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T3	12		T12	1		T141	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T6	1		T9	4		T27	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T3	1		T7	1		T8	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T4	14		T81	7		T127	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T12	13		T36	1		T37	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T1	8		T125	1		T165	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T1	2		T81	11		T30	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T132	4		T13	3		T184	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T81	1		T141	7		T129	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T4	10		T168	1		T128	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T29	1		T35	18		T168	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1393	1			T2	27		T5	3		T7	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T154	11		T142	9		T245	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T9	9		T12	4		T228	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T142	10		T139	5		T145	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T30	1		T129	10		T130	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T165	9		T144	10		T133	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T38	20		T142	6		T143	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T7	1		T177	1		T96	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17141	1			T1	58		T8	31		T9	95
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T291	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T27	7		T154	12		T234	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T141	11		T33	1		T280	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T9	2		T27	1		T73	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T174	20		T33	2		T246	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T165	4		T24	11		T186	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T12	2		T36	2		T37	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T1	1		T125	16		T165	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T1	2		T30	1		T225	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T132	4		T13	1		T184	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T141	6		T129	10		T245	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T128	23		T24	4		T131	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T29	11		T35	14		T125	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1392	1			T37	8		T125	12		T126	25
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T154	11		T142	10		T245	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T9	3		T12	1		T228	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T142	12		T268	10		T242	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T129	4		T130	13		T31	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T165	6		T170	6		T32	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T38	10		T142	4		T259	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T177	8		T98	8		T272	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T176	11		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T259	1		T318	12		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T272	15		T181	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T322	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T319	11		T235	12		T320	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T9	4		T27	11		T127	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T3	12		T7	1		T12	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T292	15		T194	3		T73	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T8	13		T36	1		T37	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T4	14		T6	1		T81	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T3	1		T139	1		T175	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T1	8		T125	1		T127	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T12	13		T30	2		T225	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T165	11		T251	1		T131	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T1	2		T81	12		T141	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T4	10		T168	1		T138	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T29	1		T35	18		T168	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T7	1		T8	1		T37	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T154	11		T142	9		T245	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T12	4		T23	1		T129	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T139	5		T140	1		T145	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1478	1			T2	27		T5	3		T9	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	347	1			T7	1		T165	9		T142	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17133	1			T1	58		T8	31		T9	95
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T259	11		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T272	14		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T324	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T9	2		T27	7		T154	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T174	20		T33	1		T246	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T292	15		T73	14		T100	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T36	2		T37	4		T141	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T27	1		T165	4		T24	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T175	4		T100	1		T323	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T1	1		T125	16		T129	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T12	2		T30	1		T225	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T165	9		T131	15		T241	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T1	2		T141	6		T129	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T24	4		T146	10		T132	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T29	11		T35	14		T125	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T37	8		T125	12		T128	23
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T154	11		T142	10		T245	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T12	1		T129	4		T130	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T268	10		T323	8		T264	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1488	1			T9	3		T38	10		T228	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T165	6		T142	12		T170	6

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22297

1

T1

68

T2

27

T3

13

auto[1]

auto[0]

4191

1

T1

3

T9

5

T29

11